Single Chip Dual–Issue RISC Processor for Real–Time MPEG–2 Software Decoding

A single chip system for real–time MPEG–2 decoding can be created by integrating a general purpose dual–issue RISC processor, with a small dedicated hardware for the variable length decoding (VLD) and block loading processes; a 32KB instruction RAM; and a 32KB data RAM. The VLD hardware performs Huffman decoding on the input data. The block loader performs the half–sample prediction for motion compensation and acts as a direct memory access (DMA) controller for the RISC processor by transferring data between an external 2MB DRAM and the internall 32 KB data RAM. The dual-issue RISC processor, running at 250MHz, is enhanced with a set of key sub-word and multimedia instructions for a sustained peak performance of 1000 MOPS. With this setup for MPEG-2 decoding applications, bi-directionally predicted non-intra video blocks are decoded in less than 800 cycles, leading to a single-chip, real-time MPEG-2 decoding system.     

Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata

Quantum-dot cellular automata is one of the candidate technologies used in Nano scale computer design and a promising replacement for conventional CMOS circuits in the near future. Since memory is one of the significant components of any digital system, designing a high speed and well-optimized QCA random access memory (RAM) is a remarkable subject. In this paper, a new robust five-input majority gate is first presented, which is appropriate for implementation of simple and efficient QCA circuits in single layer. By employing this structure, a novel RAM cell architecture with set and reset ability is proposed. This architecture has a simple and robust structure that helps achieving minimal area, as well as reduction in hardware requirements and clocking zone numbers. Functional correctness of the presented structures is proved by using QCADesigner tool. Simulation results confirm efficiency and usefulness of the proposed architectures vis-à-vis state-of-the-art.     

A novel memory cell for multiport RAM on 0.5 μm CMOSSea-of-Gates

A novel memory cell circuit for multiport RAM on CMOS Sea-of-Gates (SOG) has been proposed. It contributes to the operation both at high speed and at low voltage. In addition, a fourfold read bit line technique is also proposed to reduce the access time. A multiport RAM generator with the novel memory cell has been developed. 2-port or 3-port RAM's with flexible bit-word configurations are available. Test chips containing seven generated RAM's were designed and fabricated on 0.5 μm CMOS SOG. The experimental results of the chip show that each RAM operates at over 1.4 V and that the address access time of the 3-port RAM (16b×256w) is 4.8 ns at 3.3 V     

0.5-μm 2 M-transistor BiPNMOS channelless gate array

A channelless gate array has been realized using 0.5-μm BiCMOS technology integrating more than two million transistors on a 14-mm×14.4-mm chip. A small-size PMOS transistor and a small-size inverter are added to the conventional BiNMOS gate to form the BiPNMOS gate. The gate is suitable for 3.3-V supply and achieves 230-ps gate delay for a two-input NAND with full-swing output. Added small-size MOS transistors in the BiPNMOS basic cell can also be used for memory macros effectively. A test chip with four memory macros-a high-speed RAM, a high-density RAM, a ROM, and a CAM macro-was fabricated. The high-speed memory macros utilize bipolar transistors in bipolar middle buffers and in sense amplifiers. The high-speed RAM macro achieves an access time of 2.7 ns at 16-kb capacity. The high-density RAM macro is rather slow but the memory cell occupies only a half of the BiPNMOS basic cell using a single-port memory cell     

基于无冲突地址生成的高性能FFT处理器设计

提出一种基于存储器交织架构的FFT处理器设计方法,并且针对基-8FFT提出一种无冲突地址生成算法,数据按帧进行操作。每个存储器均划分为8个独立的存储体,通过对循环移位寄存器译码,蝶式运算单元并行无冲突读写操作数,8通道输入数据进行并行的复数乘法运算。每级运算引入完全流水,减少了运算的时钟周期开销,同时推导出局部流水线设计必须满足的不等式条件。输入、输出存储器采用乒乓操作,按帧轮换,FFT运算连续输入、输出,采样频率与系统工作频率一致,具有很好的实时性,运算精度通过块浮点得到保证。该设计方法可以扩展至基-16FFT处理器设计。     

A Small-Scale Distributed Microprocessor System Using Shared Memory Technique

A simple technique for arranging interprocessor communication through a shared random access memory (RAM) in a small-scale distributed microprocessor system is presented. An arbiter which employs a simple hardware and requires no external clock is proposed. The arbiter consists of a controller and a scanner. The controller receives a shared memory request from a microprocessor and sends a GRANT or WAIT signal back to the microprocessor according to a command from the scanner. The scanner schedules the shared memory accessing for each microprocessor. The technique can be used for interprocessor communication at a rate of less than 87 kbytes/s with 4 Z-80 microprocessors working at a 2-MHz clock signal. The microprocessors in the system need not be identical, but are required to have a WAIT state and a FETCH state indicator. The system can be increased up to 6 microprocessors and is good for a small-to-medium scale real-time control application. A front-end communication system using the proposed system is also presented as an application.     

A fully operational 1 kb variable threshold Josephson RAM

The first fully operational Josephson RAM in LSI level integration is described. The chip is designed as a 4 b× 256-word data RAM unit for a 4 b Josephson computer. A variable-threshold memory cell and the related memory architecture are used. They are so simple in structure that the fabrication can be accomplished using current Josephson junction technology. A directly coupled driver gate for a resistive bit line applies an accurate and stable driving current to the memory cell array. The RAM chip is fabricated with a 3 μm Nb/Al-oxide/Nb junction technology. For obtaining reliable RAM chips, a plasma-enhanced CVD (chemical-vapor-deposited) silicon dioxide layer is introduced for insulation between the ground plane and the base electrode. The thermal uniformity of the wafer is improved during the oxidation process for making a tunnel barrier. Installing this RAM chip together with a Josephson processor permitted the functions of a computer, including a memory access, to be successfully demonstrated. The access time was found to be 500-520 ps by measuring a test chip     

A 32 K ASIC synchronous RAM using a two-transistor basic cell

A 32 K synchronous RAM using a two-transistor basic cell has been developed for use with a 100 K compact gate array. The basic cell consists of only two transfer gates and a storage capacitor and thus results in a very dense memory array. The RAM operates as a static RAM during system operations and provides both serial and parallel data ports. It can be reconfigured into 1 K×32, 2 K×16, 4 K×8, etc. depending on the system needs. An access time of 40 ns was achieved for a test chip at an operating power of 175 mW     

Board-level built-in self-repair method of RAM

This paper describes the method of built-in self-repairing of RAM on board, designs hardware circuit, and logic for the RAM’s faults self-repairing system based on FPGA. The key technology is that it utilizes FPGA to test RAM according to some algorithm to find out failure memory units and replace the faulty units with FPGA. Then it can build a memory that has no fault concern to external controller, and realizes the logic binding between external controller and RAM. Micro Controller Unit (MCU) can operate external RAM correctly even if RAM has some fault address units. Conventional MCS-51 is used to simulate the operation of MCU operating external memory. Simulation shows FPGA can complete the faulty address units’ mapping and MCU can normally read and write external RAM. This design realizes the RAM’s built-in self-repairing on board.     

双口RAM在图像处理系统中的应用研究

基于图像处理系统实时性和大数据量冲突的问题,提出了在图像处理系统中使用双口RAM的方法。介绍了双口RAM的功能和特点,以IDT70V09芯片为例给出了图像处理系统中应用双口RAM的系统架构设计、硬件接口设计、系统软件设计以及FPGA和DSP对双口RAM操作软件的详细设计,并针对双口RAM的端口争用问题与解决方法进行了详细讨论,对系统的印制板设计和电路调试提出了建议。最后对图像处理系统进了功能测试,证明了采用双口RAM设计的系统的稳定性和可行性。     

铁电存储器FRAM在风速仪中的应用

本文介绍了一种具有SPI接口的铁电存储器FM25L256,以及其与C8051F020单片机的接口电路在风速仪中的应用,并给出了相应的硬件连接图和读写软件流程.这种方式具有非易失性、高速读写、超低功耗、几乎无限次擦写,并且占用极少单片机引脚数的优点.以后必将成为MCU外扩数据存储器的主要方式.     

双口RAM在大屏幕LED显示系统中的应用开发

双口RAM与常规RAM的最大区别是双口RAM具有两套独立的地址、数据和控制线,允许两个独立的CPU或控制器同时异步地访问存储单元,双口RAM由片内的仲裁逻辑来确定哪一侧的CPU可以访问内部RAM单元.IDT7132是2kB的标准双口RAM.文中重点介绍采用以自顶向下方法设计的基于CLD(复杂可编程逻辑器件)的大屏幕LED(发光二极管)显示系统中双口RAM的应用,并给出了系统设计方法及相关硬件电路.本设计中IDT7132双口RAM用来连接单片机信号处理模块和CPLD扫描模块.     

基于ARM和DSP的微机线路保护装置

在微机线路保护中,利用数字信号处理器（DSP）高效快速的数字信号处理能力和嵌入式先进的精简指令集芯片机器（ARM）处理器强大的以太网通信功能,采用DSP＋ARM9的双中央处理器（CPU）的硬件结构,两者之间采用双口随机存储器（RAM）进行数据交换。软件设计基于嵌入式Linux操作系统,移植了Bootloader、内核,构建了Ramdisk的根文件系统,并移植了应用程序。     

A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates

A 1.5-ns address access time, 256-kb BiCMOS SRAM has been developed. To attain this ultra-high-speed access time, an emitter-coupled logic (ECL) word driver is used to access 6-T CMOS memory cells, eliminating the ECL-MOS level-shifter time delay. The RAM uses a low-power active pull down ECL decoder. The chip contains 11-K, 60-ps ECL circuit gates. It provides variable RAM configurations and general logic functions. RAM power consumption is 18 W; chip power consumption is 35 W. The chip is fabricated by using a 0.5-μm BiCMOS process. The memory cell size is 58 μm² and the chip size is 11×11 mm     

基于FPGA的微光视频采集与预处理系统设计

针对当前微光视频图像采集与处理系统中数据处理量与系统实时性之间的矛盾,设计了一种基于现场可编程门阵列(Field Programmable Gate Array, FPGA)的实时信号采集与预处理系统。该系统以高性能Xilinx A7系列芯片为主控芯片,使用两片第二代双倍数据率同步动态随机存取存储器(Double-Data-Rate Two Synchronous Dynamic Random Access Memory, DDR2 SDRAM)作为核心存储器件,并定制超感光互补金属氧化物半导体(Complementary Metal Oxide Semiconductor, CMOS)传感镜头作为视频图像采集器件。完成系统的硬件设计之后,通过Xilinx Vivado平台以及Matlab进行软件系统的工程设计与仿真分析,实现了微光环境下视频图像的采集、存储、处理与显示的全过程。实验结果表明,该系统采集的微光视频图像实时性好、动态画面流畅。     

A 7.5-ns 32 K×8 CMOS SRAM

A 256 K (32 K×8) CMOS static RAM (SRAM) which achieves an access time of 7.5 ns and 50-mA active current at 50-MHz operation is described. A 32-block architecture is used to achieve high-speed access and low power dissipation. To achieve faster access time, a double-activated-pulse circuit which generates the word-line-enable pulse and the sense-amplifier-enable pulse has been developed. The data-output reset circuit reduces the transition time and the noise generated by the output buffer. A self-aligned contact technology reduces the diffused region capacitance. This RAM has been fabricated in a twin-tub CMOS 0.8-μm technology with double-level polysilicon (the first level is polycide) and double-level metal. The memory cell size is 6.0×11.0 μm² and the chip size is 4.38×9.47 mm ²     

内存条的结构与应用研究

采用大容量的存储器扩大单片机数据空间，常用的器件有：RAM、FLASH RAM、NVRAM以及DRAM。其中，DRAM具有容量特点大、价格低的优点。介绍了内存条的刷新原理和工作时序，详细讨论了89C51单片机与内存条接口设计的方法。最后采用ispLSI1032进行了集成处理，简单可靠，可使单片机系统拥有大容量的数据存储空间。     

Reliability Modeling and Analysis of Fault-Tolerant Memories

A memory array reliability model is developed that can be applied to a wide range of memory organizations including random-access memories (RAM) and read-only memories (ROM). The model is particularly useful for computing the reliability of fault-tolerant memories that employ techniques such as hardware redundancy, error-correcting codes, and software error-correcting algorithms. The model accommodates the effect of faults masked by data. Reliability models that incorporate the array model are given for a simplex RAM, an N-modular-redundant RAM, a spared RAM, a single-error-correcting RAM, a multiple-error-correcting RAM, and a ROM. Reliability characteristics of these memories are compared. The results suggest that memories with error-correcting capability and spare bit-planes provide the best reliability. Memories with sparing at the array level are next best followed by NMR and simplex organizations. ROM reliability is shown to be more optimistic when masked faults are considered.     

激光加工多自由度工作台控制系统

主要对激光加工多自由度工作台控制系统的硬件和软件进行了设计。系统选用多轴运动控制器(PMAC)作为核心控制器,实现对激光加工5个运动轴的控制。介绍了双端口RAM实现上位机与PMAC的通讯方法,这种方法可以大大提高系统的通信速度。设计了可视化人机交互界面,为用户联系控制系统提供了一个友好的交互窗口。表述了PMAC运动程序及PLC程序的编写过程,为用户自主进行程序开发提供了指导。这些研究分析对硬件设计和软件开发都具有重要的参考意义。     

便携式测量仪大容量RAM及USB接口的设计

以CH372A(USB接口)和LH5P8512(伪静态RAM)芯片为例,介绍基于AT89C51微处理器的便携式测量仪大容量RAM及USB接口的设计方案。对RAM存储器和USB接口电路的组成和管理做了详细说明,并对CH372A的命令字和通信模式做了介绍,针对数据上传和下传通信程序以及API函数做了系统地论述。实践证明,该设计方案硬件成本低、软件编写简便,有通用性。