Electron traps created in gate oxides by Fowler–Nordheim injections

Two types of electron traps, donor-like and acceptor-like, are created in the gate oxide of metal-oxide-semiconductor capacitors by Fowler–Nordheim electron injections. Electrical properties (areal density, capture cross-section, centroid) of each type of trap are determined by using the avalanche electron injection method and by combining capacitance–voltage and current–voltage measurements. These properties are measured with regard to the Fowler–Nordheim fluence up to breakdown and for both injection modes (electrons injected either from the gate or from the substrate of capacitors).     

Hot-carrier-induced MOSFET degradation under AC stress

The effects of gate and drain voltage waveforms on the hot-carrier-induced MOSFET degradation are studied. Drain votage transients have little effect on the degradation rate. Only the falling edge of the gate pulse in the presence of a high drain voltage enhances the degradation rate. For devices in typical inverter circuits, dc stress results together with the substrate current waveform can predict the degradation rate under ac stress for a wide range of rise and delay times.     

Parasitic MOSFET degradation induced by Fowler-Nordheim injection

Degradation induced by Fowler-Nordheim (F-N) electron injection is observed in a parasitic MOS transistor associated with a MOS transistor's edge region. A bump appears in the subthreshold region of both an n-channel transistor after positive gate biased F-N injection and a p-channel transistor after negative gate biased F-N injection. It is found that the effective gate-oxide thickness of a parasitic transistor is 30 nm. As thinner gate oxide is used, the amount of the charge injected into the gate oxide may increase due to increased electric fields     

Structure-enhanced MOSFET degradation due to hot-electron injection

Device degradation due to channel hot-electron injection in several nonconventional MOSFET structures including minimum-overlap gate, offset gate, graded drain, and lightly doped drain (LDD) structures are evaluated. In these nonconventional structures the device degradation is much faster than that in conventional devices when biased with the same amount of hot electrons in the channel. This faster degradation rate is proposed to be due to external channel pinchoff at the more lightly doped drain edge. This behavior implies even more severe constraints on the operating regime for these nonconventional device structures at submicrometer gatelengths to maintain adequate reliability margins.     

New positive charge trapping dynamics in SiO2 gate oxide, based on bulk impact ionization processes under Fowler–Nordheim stress

A new charge trapping dynamics is proposed to analyze theoretically the gate oxide degradation in metal oxide silicon structures under Fowler–Nordheim (F–N) stress (6–10 MV/cm) at a low injected electron fluence. Devices studied were MOS capacitors with 22-, 27-, and 33-nm-thick, thermally grown silicon dioxide (SiO₂) on (100) n-Si. Our model includes tunneling electron initiated band-to-band impact ionization and trap-to-band ionization, as the possible mechanisms for the generation of hole and positive charge in the bulk of the oxide, respectively. The results from our model are in good agreement with the experimental results of gate voltage shift with injected electron fluence under constant current stress. Based on the developed coupled dynamics, we have compared the degradation under F–N stress at a constant current and gate voltage.     

Comments on "Structure-enhanced MOSFET degradation due to hot-electron injection"

Hsu and Grinolds recently compared channel hot-electron (CHE) stress results of conventional and "extended drain" NMOS FET's. [1]. They observe increasing degradation as the extended drain resistance increases when the drain bias is defined as that which produces a fixed substrate current. A model in which the hot-electron stress induces surface states within the extended drain region is proposed. We argue that the drain bias condition chosen for these measurements does not produce equal numbers of channel hot electrons in all devices as is claimed. Since the ratio of substrate current to source current is a measure of the mean electron energy, we claim that this ratio (and hence the mean electron energy) increases as extended drain resistance increases.     

Dynamic Fowler–Nordheim injection in EEPROM tunnel oxides at realistic time scales

The purpose of this work is to investigate the dynamic behaviour of Fowler–Nordeim injection through EEPROM tunnel oxides, in conditions representative of the standard device operation. An experimental procedure based on the acquisition of current transients induced by trapezoidal-shape short voltage pulses is presented. It is then used to evidence a rapid positive charging and to determine some of its properties. Implications regarding the device behaviour and modelling are finally discussed.     

Switching times variation of power MOSFET devices after electrical stress

The switching performance of three power MOSFET devices with different oxide thicknesses is studied after several periods of electrical stress. The thickest oxide reveals a large accumulation of positive charges in the oxide bulk after small periods of stress. These charges affect the switching parameters by increasing the rise time and by decreasing the fall time. Larger periods of stress reduce the effect of positive charges by increasing the number of interface states. The threshold voltage is decreased by the effect of a positive oxide charge and increases with the appearance of interface states. All these phenomena are less observable as we reduce the oxide thickness.     

Hot-electron-induced MOSFET degradation at low temperatures

The n-channel LDD MOSFET lifetime is observed to followtau=(A/I_{d})(I_{sub}/I_{d})^{-n}from 77 to 295 K when the device is stressed near the maximum Isub. Here Idis the drain current andAis the proportionality constant. The experimental result indicates thatnis approximately 2.7 and is independent of temperature. However, the proportionality constantAfollowsA = A_{0} exp (-E_{a}/kT), withE_{a} = 39meV. The smaller proportionality constant at low temperatures suggests that hot-electron injection (HEI) degradation is caused by the electron trapping in the oxide.     

MOSFET degradation kinetics and its simulation

In this work, the time-dependence of Si/SiO/sub 2/ interface trap formation is considered by solving an improved set of Si-H defect kinetics equations that take into account interface disorder and the Si-H bond activation energy evolution as the bonds are broken. This model is applied to the simulation of metal oxide semiconductor field effect transistor (MOSFET) high field and hot carrier degradation, and then verified with various experimental data. An estimation of the potential barrier of the Si/SiO/sub 2/ interface is given.     

Indirect fitting procedure to separate the effects of mobility degradation and source-and-drain resistance in MOSFET parameter extraction

A new procedure is presented to separate the effects of source-and-drain series resistance and mobility degradation factor in the extraction of MOSFET model parameters. It requires only a single test device and it is based on fitting the I_D(V_GS, V_DS) equation to the measured characteristics. Two types of bidimensional fitting are explored: direct fitting to the drain current and indirect fitting to the measured source-to-drain resistance. The indirect fitting is shown to be advantageous in terms of fewer number of iterations needed and wider extent of initial guess values range.     

Intrinsic MOSFET parameter fluctuations due to random dopantplacement

Intrinsic fluctuations in threshold voltage, subthreshold swing, saturation drain current and subthreshold leakage of ultrasmall-geometry MOSFETs due to random placement of dopant atoms in the channel are examined using novel physical models and a Monte Carlo simulator. These fluctuations are shown to pose severe barriers to the scaling of supply voltage and channel length and thus, to the minimization of power dissipation and switching delay in multibillion transistor chips of the future. In particular, using the device technology and the level of integration projections of the National Technology Roadmap for Semiconductors for the next 15 years, standard and maximum deviations of threshold voltage, drive current, subthreshold swing and subthreshold leakage are shown to escalate to 40 and 600 mV, 10 and 100%, 2 and 20 mV/dec, and 10 and 10⁸%, respectively, in the 0.07 μm, 0.9 V complementary metal-oxide-semiconductor (CMOS) technology generation with 1.3-64 billion transistors on a chip in 2010. While these deviations can be reduced to some degree by selecting optimal values of channel width, the associated penalties in dynamic and static power, and in packing density demand improved MOSFET structures aimed at minimizing parameter deviations     

Extracting MOS parameter variations using dual-drain MOSFET offset

We have developed two offset models for dual-drain MOSFETs-one for surface-channel and one for buried-channel MOSFETs. By fitting the models to offsets measured at selected biases, estimates of various MOS parameter variations can be extracted. The models are originally intended to demonstrate that, contrary to current belief, channel implant variations can contribute as much offset to magnetic sensor MOSFETs as mobility variations. The utility of the method, however, extends beyond magnetic sensors. The same approach can be used to extract MOS parameter variations important in circuits such as MOS differential pairs     

Analysis of Fowler–Nordheim injection in NO nitrided gate oxide grown on n-type 4H–SiC

Fowler–Nordheim injection in NO nitrided gate oxides, grown on n-type 4H–SiC, has been investigated at room temperature and 300°C. The results show that NO increases the electron injection barrier height to a value which is very close to the theoretical value at room temperature. Excessive temperature dependence of the electron injection barrier height is also significantly reduced by the nitridation.     

Experimental extraction of degradation parameters after constant voltage stress and substrate hot electron injection on ultrathin oxides

The impact of hot electrons on gate oxide degradation is studied by investigating devices under constant voltage stress and substrate hot electron injection in thin silicon dioxide (2.5–1.5 nm). The build-up defects measured using low voltage stress induced leakage current is reported. Based on these results, we propose to extract the critical parameter of the degradation under simultaneous tunnelling and substrate hot-electron stress. During a constant voltage stress the oxide field, the injected charge and the energy of carriers are imposed by V_G and cannot be studied independently. Substrate hot electron injection allows controlling the current density independent of the substrate bias and oxide voltage. The results provide an understanding for describing the reliability and the parameters dependence under combined substrate hot electron injection and constant voltage stress tunnelling.     

A comprehensive analytical study of an undoped symmetrical double-gate MOSFET after considering quantum confinement parameter

This paper presents analytical models of threshold voltage, carrier concentration and drain current for undoped symmetrical double-gate (SDG) MOS devices. The analytical models are derived after solving the Poisson's equation under Gradual Channel Approximation (GCA). Quantum mechanical effect in ultrathin silicon film is studied by introducing quantum confinement parameter and quantum corrected potential in the Poisson's equation instead of solving complex Schrödinger–Poisson's equation. The confinement parameter, which depends on film thickness, work function and gate bias decreases with film thickness. Quantum corrected potential attains its maximum value near the interface and minimum value at the centre of the silicon film. The mobile carrier density and surface potential are reduced due to quantum confinement effect. The simulation result of the threshold voltage shows excellent agreement with quantum numerical results.     

MOSFET degradation due to stressing of thin oxide

Oxide and interface traps in 100 Å SiO2created by Fowler-Nordheim tunneling current have been investigated using capacitor C-V, I-V, and transistor I-V measurements. The net oxide trapped charge is initially positive due to hole trapping near the anode interface and, at sufficiently high fluence, it becomes negative due to the trapping of electrons with a centroid of 60 Å from the injector (cathode) interface. Interface traps (Surface states) are created by tunneling electrons flowing to and from the substrate. The interface-trap energy distribution gives a distinct peak at 0.65 eV above the valence band edge. The positive charge trapping and interface traps generation saturate at high electron fluence, but not the electron trap generation. The generation rates for electron traps and interface traps are weak functions of tunneling current density over the range tested. The interface traps cause degradations in subthreshold current slope and surface electron mobility. The threshold-voltage shift can be either positive or negative under the combined influence of the oxide charges and the interface charges.     

An improved method of MOSFET modeling and parameter extraction

A method is presented to accurately determine MOSFET modeling parameters from a single linear region (VDS< 2kBT/q)ID- VGSmeasurement based on the operation of a single transistor in the strongly inverted regime. The intrinsic values of the surface scattering parameter θsand the transistor gain β0may be separated from the series resistance Rsand drain bias VDSeffects while including band bending beyond the 2φFpoint. The mobility (excluding surface scattering effects), threshold voltage, bulk doping, and flat-band voltage are also determined.     

Effect of final annealing on hot-electron-induced MOSFET degradation

The effect of the post metallization final annealing step on hot-electron-induced device degradation in MOSFET's with various drain/source structures has been studied. It is shown that the hydrogen ambient during the final annealing enhances the hot-electron-induced degradation rate. By performing the final annealing in the nitrogen ambient, the device reliability can be significantly improved without sacrificing any of the device performances.     

Hot carrier-induced SOI MOSFET degradation under AC stressconditions

The hot-carrier-induced device degradation in partially depleted silicon-on-insulator (SOI) devices has been investigated under AC stress conditions. The device degradation of both floating-body SOI devices and body contacted SOI devices have been measured and analyzed for different AC stress frequencies and gate bias voltages. Possible degradation mechanisms are suggested