Wafer charging in process equipment and its relationship to GMRheads charging damage

Significant know-how and understanding of device charging damage in processing equipment exists in complementary metal oxide semiconductor (CMOS) integrated circuit (IC) manufacturing. This paper introduces the basic charging mechanisms responsible for gate oxide damage in CMOS ICs, illustrates these mechanisms with examples of measurements obtained in contemporary IC processing equipment, and shows how this knowledge could be applied to the control of charging damage in GMR heads wafer processing. A wafer charging characterization method successfully used by integrated circuit and equipment manufacturers to quantify wafer charging in process equipment is also described     

半导体产业中晶圆片表面处理的发展

回顾当前IC制造中使用的清洗技术是如何减少、消除或避免晶圆片表面沾污的发展历史。同时探讨优化晶圆片表面状态的重要性和寻求一种“完全避免沾污”的方法。     

Control of MMST RTP: repeatability, uniformity, and integration forflexible manufacturing [ICs]

A real-time multivariable strategy is used to control the uniformity and repeatability of wafer temperature in rapid thermal processing (RTP) semiconductor device manufacturing equipment. This strategy is based on a physical model of the process where the model parameters are estimated using an experimental design procedure. The internal model control (IMC) law design methodology is used to automatically compute the lamp powers to a multizone array of concentric heating zones to achieve wafer temperature uniformity. Control actions are made in response to real-time feedback information provided by temperature sensing, via pyrometry, at multiple points across the wafer. Several modules, including model-scheduling and antiovershoot, are coordinated with IMC to achieve temperature control specifications. The control strategy, originally developed for prototype equipment at Stanford University, is analyzed via the customization, integration, and performance on eight RTP reactors at Texas Instruments conducting thirteen different thermal fabrication operations of two sub-half-micron CMOS process technologies used in the the Microelectronics Manufacturing Science and Technology (MMST) program     

Full Field Temperature Measurement of Specular Wafers During Rapid Thermal Processing

Many of the processes involved in the creation of semiconductor devices involve high-temperature processing of silicon wafers. The benefits of reduced thermal budget and faster cycle time make rapid thermal processing (RTP) a possible key technology for semiconductor manufacturing. However, the problem of nonuniform wafer temperature has prevented it from further spread among the industry. The first step in developing controls to maintain a uniform wafer temperature is accurate temperature measurement during processing. In this paper, a system was developed to exploit the specular reflectivity of silicon wafers and obtain a measurement of the wafer temperature profile. The spectral reflectivity is determined by measuring the intensity of an incident beam and the beam reflected from the wafer surface. With this measured reflectivity value the spectral-directional wafer emissivity was determined using Kirchhoff's law. The obtained emissivity then was used to calculate the wafer temperature profile from an image obtained with an infrared camera. An experimental study of the transmittance of an undoped silicon calibration wafer at an elevated temperature is also discussed     

An In Situ Approach to Real-Time Spatial Control of Steady-State Wafer Temperature During Thermal Processing in Microlithography

We proposed an in situ method to control the steady-state wafer temperature uniformity during thermal processing in microlithography. Thermal processing of wafer in the microlithography sequence is conducted by the placement of the wafer on the bake-plate for a given period of time. A physical model of the thermal system is first developed by considering energy balances on the system. Next, by monitoring the bake-plate temperature and fitting the data into the model, the temperature of the wafer can be estimated and controlled in real-time. This is useful as production wafers usually do not have temperature sensors embedded on it, these bake-plates are usually calibrated based on test wafers with embedded sensors. However, as processes are subjected to process drifts, disturbances, and wafer warpages, real-time correction of the bake-plate temperatures to achieve uniform wafer temperature at steady state is not possible in current baking systems. Any correction is done based on run-to-run control techniques which depends on the sampling frequency of the wafers. Our approach is real-time and can correct for any variations in the desired steady-state wafer temperature. Experimental results demonstrate the feasibility of the approach     

Integrated modeling of Self-heating of confined geometry (FinFET,NWFET, and NSHFET) transistors and its implications for the reliability of sub-20 nm modern integrated circuits

The evolution of transistor topology from planar to confined geometry transistors (i.e., FinFET, Nanowire FET, Nanosheet FET) has met the desired performance specification of sub-20 nm integrated circuits (ICs), but only at the expense of increased power density and thermal resistance. Thus, self-heating effect (SHE) has become a critical issue for performance/reliability of ICs. Indeed, temperature is one of the most important factors determining ICs reliability, such as Negative Bias Temperature Instability (NBTI), Hot Carrier Injection (HCI), and Electromigration (EM). Therefore, an accurate SHE model is essential for predictive, reliability-aware ICs design. Although SHE is collectively determined by the thermal resistances/capacitances associated with various layers of an IC, most researchers focus on isolated components within the hierarchy (i.e., a single transistor, few specific circuit configurations, or specialized package type). This fragmented approach makes it difficult to verify the implications of SHE on performance and reliability of ICs based on confined geometry transistors. In this paper, we combine theoretical modeling and systematic transistor characterization to extract thermal parameters at the transistor level to demonstrate the importance of multi-time constant thermal circuits to predict the spatio-temporal SHE in modern sub-20 nm transistors. Based on the refined Berkeley Short-channel IGFET Model Common Multi-Gate (BSIM-CMG) model, we examine SHE in typical digital circuits (e.g., ring oscillator) and analog circuits (e.g., two-stage operational amplifier) by Verilog-A based HSPICE simulation. Similarly, we develop a physics-based thermal compact model for packaged ICs using an effective media approximation for the Back End Of Line (BEOL) interconnects and ICs packaging. We integrate these components to investigate SHE behavior implication on ICs reliability and explain why one must adopt various (biomimetic) strategies to improve the lifetime of self-heated ICs.     

圆片级封装技术——超CSPTM

文章论述了超CSPTM圆片级封装技术工艺。在封装制造技术方面此CSP封装技术的优越性在于其使用了标准的IC工艺技术。这不仅便于圆片级芯片测试和老炼筛选,而且在圆片制造末端嵌入是理想的。同时,文章也论述了超CSP封装技术的电热性能特征。     

基于神经网络方法的半导体生产工艺优化

以提高生产成品率为目标,利用神经网络的非线性和容错性,对半导体芯片生产过程进行了分析和优化,具体内容如下：（１）使用神经网络方法建立模型,确定生产线上工艺参数和成品率之间的映射关系,构造以工艺参数为输入,成品率为输出的多维函数曲面．（２）对上述多维函数曲面进行搜索,搜索成品率最高的最优点,以该最优点的工艺参数值为依据确定工艺参数的规范值．（３）对工艺参数规范进行优化,在实际生产工艺中反复实践,直至达到提高成品率的目的．生产实践证明,神经网络的分析结果是合理的．根据神经网络分析提出的优化建议,有效地提高了工     

Study of hybrid orientation structure wafer

Two types of 5μm thick hybrid orientation structure wafers,which were integrated by（110）or（100） orientation silicon wafers as the substrate,have been investigated for 15-40 V voltage ICs and MEMS sensor applications.They have been obtained mainly by SOI wafer bonding and a non-selective epitaxy technique,and have been presented in China for the first time.The thickness of BOX SiO₂ buried in wafer is 220 nm.It has been found that the quality of hybrid orientation structure with（100）wafer substrate is better than that with（110）wafer substrate by"Sirtl defect etching of HOSW".     

Microelectronics fabrication training using multimedia and the Web

Integrated circuits are the driving force behind technological breakthroughs and innovative product development in electronics today. ICs are fabricated by a sophisticated series of steps that range in number from dozens to hundreds, depending on the complexity of the circuit function. Although comprehensive training in the field of semiconductor manufacturing requires thorough understanding of all phases of the fabrication process, the study of IC fabrication requires an unusually diverse familiarity with physics, inorganic chemistry, semiconductor devices, and statistics. To alleviate impediments resulting from resource constraints as well as to enhance students' educational experience, we are developing ways to teach microelectronic processing using interactive multimedia at the Georgia Institute of Technology. Our overall vision is to develop a Virtual Cleanroom, in which a student can use a high-performance multimedia workstation (equipped with the necessary audio, video, and graphics capabilities) to follow a semiconductor wafer through a complete processing sequence-from bare silicon to finished IC     

Wafer mapping of ESD performance

This paper reports, for the first time, on a variation of the ESD performance of CMOS ICs across the wafer. A variation of the TLM-ESD failure threshold by as much as a factor of 4 (four) was found within a singel wafer. Comparable results were found for HBM-ESD tests. Implications of this finding for process control and ESD qualification are discussed. As main conclusion, ESD wafer mapping for process and IO libray qualification is proposed.     

A wafer-handling interface under processing ambient conditions fora single-wafer cluster tool

The pretreatment process used in semiconductor manufacturing can include over one-hundred processes, and about 90% of the wafer transfers are done between processors or process chambers that have different ambient conditions from each other; that is, between the atmosphere and a vacuum ambient or between a low and a high vacuum ambient. The throughput and yield from a semiconductor manufacturing line can be greatly improved by reducing the pumping and setting time of each process chamber ambient that is needed when transferring a wafer. We previously proposed a wafer-handling interface that operates under processing ambient conditions (the WHIPAC), with which the processing ambient conditions in the process chamber need not be changed for every wafer exchange and processing ambient fluctuations can be made smaller. We have developed a WHIPAC that allows the wafer in a process chamber under processing ambient conditions to be exchanged with a small mobile buffer chamber located in the transfer chamber at the center of a cluster tool used for single-wafer processing. This paper describes the principle of the WHIPAC for a single-wafer cluster tool and discusses the experimental results obtained from tests of a prototype system     

Low thermal budget processing of organic dielectrics

Low dielectric constant organic materials are ideal for use as interconnect dielectrics for integrated circuits (ICs) to reduce power dissipation, crosstalk and RC delays. For high performance and reliability of ICs, reduced thermal and intrinsic stress is highly desirable. Low thermal budget rapid isothermal processing (RIP) can provide materials with lower stress. In this paper, we demonstrate the role of photoeffects in the curing of polyimide films using a rapid isothermal processor as a source of optical and thermal energy. The availability of large a number of ultraviolet and vacuum ultraviolet photons on the film surface allowed a lower curing temperature and also resulted in the lowest leakage current and film stress. We demonstrate a direct one-to-one correlation between electrical, mechanical, and structural properties of the organic dielectrics     

Prediction of defect onset conditions in heat cycling based on athermoelastic wafer model

A thermoelastic wafer model is proposed for predicting defect onset conditions during heat cycling in a furnace. This model is formulated for application to the plane stress state under thermal loading. The wafer temperature is calculated by a wafer temperature model proposed in a previous work. Predictions are tested by comparison with the thermal stresses resolved on the slip systems of the silicon crystal under the process conditions (i.e. furnace temperature, insertion velocity, and wafer spacing). When the proposed model is applied to 125-mm diameter and 150-mm-diameter wafers, it is shown that the thermal stress level is reduced to about a half by increasing the wafer spacing by a factor of two or three. Accordingly, the predicted defect onset results based on this model are in reasonable agreement with experiments     

Requirements of CAM in IC technology

Ultra clean technology (ultra clean processing environment, ultra clean wafer surface, perfect process-parameter control) is a crucial factor in developing high quality process technology for future ULSI fabrication. Wafers should never be exposed to air. The possibility of performing all wafer processes in equipment having the same hardware configuration is discussed based on the concept of a closed manufacturing system in conjunction with highly advanced super clean systems.     

Low-K Dielectric Compatible Wafer-Level Compliant Chip-to-Substrate Interconnects

Performance, power, size, and cost requirements in the microelectronics industry are pushing for smaller feature size, innovative on-chip dielectric materials, higher number of interconnects at a reduced pitch, etc., without compromising the microelectronics reliability. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill material. These compliant interconnects are beneficial for integrated circuits (ICs) with low-K dielectric material. They are also potentially cost effective as they can be fabricated using conventional wafer fabrication infrastructure. In this paper we discuss the assembly and experimental reliability assessment, through thermal cycling, of G-Helix interconnects assembled on an organic substrate. Results from mechanical characterization experiments are also presented. It is shown that the proposed interconnects are not likely to delaminate or crack the low-K dielectric material. Also, a unique integrative approach is discussed, with interconnects having varying compliance for optimum electrical and mechanical performance.     

Role of rapid photothermal processing in process integration

The smaller dimension devices and larger scales of integration are demanding constant reduction of the macroscopic and microscopic defects in the manufacturing of silicon integrated circuits. Increasing capital investment in manufacturing is forcing us toward processes and equipment that are effective not only in reduction of the cost of ownership but can also increase the effectiveness of equipment of current as well as future applications. Rapid thermal processing (RTP) based on incoherent light as the source of energy is playing an important role in the manufacturing of 300 nm and larger diameter wafers. The dominance of ultraviolet and vacuum ultraviolet photons in RTP results in rapid photothermal processing (RPP). The results presented in this paper show that the materials and devices processed by RPP are better than those processed by other thermal processes. This paper discusses the manufacturing science, operating principles of RPP and experimental results supporting its role in future process integration     

Improvement in oxide thickness uniformity by repeated spikeoxidation

A new repeated spike oxidation (RSO) method used in a rapid thermal processing system was proposed in this work. Simulation results predict the temperature distribution on the wafer would be improved by this RSO method. We proposed that the improvement in wafer temperature uniformity is mainly caused by self-compensation in radiation heat absorption rate. Experimental data pointed out that the new method can produce more uniform oxide thickness than the conventional one under an intentionally created nonuniform heating environment     

300 mm Si片加工及最新发展

65 nm及以下线宽对Si片表面的各方面性能要求越来越高,主要体现在两个方面,一个是加工工艺,另一个是加工设备.在加工方法上,65 nm线宽用300 mm Si片不同于90 nm,如运用多步单片精密磨削,不仅可以提高表面几何参数,还可以减小表面特别是亚表面的损伤层.而对于加工设备,要求更加精密,特别是单面精抛光,在保证去除量的同时还要使Si片表面各点的去除量保持均匀.对目前300 mm Si片的磨削、抛光及清洗的每一道工艺流程,特别是相对于65 nm技术的一些加工流程及方法的最新发展进行了详细的论述,指出了300 mm Si片加工工艺的发展趋势.     

近场热辐射的最新研究进展

主要从理论数值模拟和近场辐射实验研究的角度介绍了近几年在近场热辐射传热方面的最新研究成果。理论研究的焦点主要集中在石墨烯复合材料、人工加工或合成超材料等方面的传热研究。实验研究的焦点是实验室基于纳米尺度近场热辐射测量的设备制造与方法创新。目前实验上已经实现了最小距离仅为2 nm的极近场热辐射测量。近场热辐射的进一步研究可为热光伏、辐射制冷以及高效能源收集应用提供理论基础。