Electrical characterization of ultra-shallow np junctions formed by AsH3 plasma immersion implantation

Electrical characteristics of ultra-shallow (90 nm) n⁺p junctions fabricated using plasma immersion implantation of arsenic ions are investigated. With the arsenic source, a more uniform doping profile was obtained. In addition, both forward and reverse current–voltage (IV) characteristics at operation temperature ranging from 100 to 450 K were measured. Results show that the ideality factor varies from unity to two indicating both diffusion and generation-recombination (GR) processes are important in these devices. The ideality factor is found to fluctuate with the temperature due to discrete trap centers in the junction. Annealing has profound effect on the reverse diode characteristics. For fully activated sample, the IV relationship in the reverse region essentially follows a power law, i.e. I∝ V^m. The power index (m) is about 3 and almost remains unchanged at different temperatures.     

Characteristics of sub-100-nm p+/n junctions fabricatedby plasma immersion ion implantation

Plasma immersion ion implantation (PIII) is an efficient method for fabricating high-quality p⁺/n diodes with junction depths below 100 nm. SiF₄ is implanted to create an amorphous Si layer to retard B channeling and diffusion, and then BF₃ is implanted. Ultrashallow p⁺/n junctions are formed by annealing at 1060 °C for 10 s. With the shallow implants, no extended defects are observed in device or peripheral areas due to rapid outdiffusion of fluorine. Diode electrical characteristics yield forward ideality factor of 1.05-1.06 and leakage current density below 2 nA/cm ² in the diode bulk. Minority-carrier lifetime below the junction is greater than 250 μs     

Microwave annealing for ultra-shallow junction formation

We propose a new method for activation of source/drain junctions by microwave annealing. A study with B/BF₂ implants at ultralow energies (300/500 eV) and high doses (1E15/5E15 cm⁻²) was completed. The samples were subjected to a high-power cyclotron resonance maser, called a “gyrotron,” for annealing. There appears to be some evidence of electromagnetic field-aided activation. The activation levels achieved exceed the levels reported by thermal means at the corresponding temperatures. Secondary ion mass spectroscopy (SIMS) was used to examine the impurity profile after ion implantation and diffusion. Spreading resistance profiling was used to examine the activated dopant profile.     

等离子体浸没离子注入介质材料鞘层演化规律

等离子体浸没离子注入(Plasma-immersion-ion-implantation,简称PIII)已被广泛应用于金属、半导体以及绝缘介质材料改性等领域.通过一维流体力学模型,利用C语言实现编程,对一维平面介质靶鞘层特性进行了数值模拟,得到了鞘层的演化规律,模拟的结果可以为优化实际的工艺参数提供参考.     

Ultra-shallow np junction formed by PH3 and AsH3 plasma immersion ion implantation

Ultra-shallow 28–88 nm n⁺p junctions formed by PH₃ and AsH₃ plasma immersion ion implantation (PIII) have been studied. The reverse leakage current density and intrinsic bulk leakage current density of the diodes are found to be as low as 4.2 nA cm⁻² and 2.4 nA cm⁻², respectively. The influences of pre-annealing condition and the carrier gas on the junction depth and the sheet resistance are also studied. It is found that the increase of H or He content in the PH₃ PIII can slow down the phosphorus diffusion and shallower junction can been obtained. Annealing conditions have pronounced effect on the sheet resistance. It was found that sample annealed at 850 °C for 20 s has reverse results to that annealed at 900 °C for 6 s. For AsH₃ PIII samples, it is observed that two-step annealing is more effective to activate the dopant and a lower reverse current density resulted.     

Effect of number of laser pulses on p+/n silicon ultra-shallow junction formation during non-melt ultra-violet laser thermal annealing

We investigate the effect of the number of laser pulses on the formation of p⁺/n silicon ultra-shallow junctions during non-melt ultra-violet laser (wavelength, 355 nm) annealing. Through surface peak temperature calculating by COMSOL Multiphysics, the non-melt laser thermal annealing is performed under the energy density of 130 mJ/cm². We demonstrate that increasing the number of laser pulses without additional pre-annealing is an effective annealing method for achieving good electrical properties and shallow junction depth by analyzing sheet resistance and junction depth profiles. The optimal number of laser pulses is eight for achieving a high degree of activation of dopant without further increase of junction depth. We have also explained the improved electrical characteristics of the samples on the basis of fully recovered crystallinity as revealed by Raman spectroscopy. Thus, it is suggested that controlling the number of laser pulses with moderate energy density is a promising laser annealing method without additional pre-annealing.     

Plasma immersion ion implantation doping using a microwavemultipolar bucket plasma

Using plasma immersion ion implantation, silicon has been doped with boron in a high-voltage pulsed microwave multipolar bucket plasma system. Diborane gas (1%) diluted in helium is used as an ion source. A sheet resistance of 57 Ω/□ and an implanted dose of 1.9×10¹⁵/cm² are obtained in 10 min. when the target potential is pulsed to -10 kV with a 1% duty cycle. The boron profile in the silicon substrate is different from that predicted for a conventional 10-keV ion implantation. Silicon p-n junctions fabricated by this technique are of good quality     

Application of plasma immersion ion implantation doping tolow-temperature processed poly-Si TFTs

This work applied, for the first time, plasma immersion ion implantation (PIII) for source/drain doping on low-temperature processed polysilicon thin-film transistors (poly-Si TFTs). Experimental results indicate that PIII doping can provide adequate dopant concentration and junction depth for source/drain. In addition, H₂-diluted phosphorus PIII can promote dopant activation more efficiently during RTA at 600°C than with conventional ion implantation (II) technology. The excellent characteristics of PIII doped poly-Si TFTs resemble those of conventional II doped ones     

PMOS integrated circuit fabrication using BF3 plasma immersion ion implantation

The feasibility of plasma immersion ion implantation (PHI) for multi-implant integrated circuit fabrication is demonstrated. Patterned Si wafers were immersed in a BF₃ plasma forp-type doping steps. Boron implants of up to 3 × 10¹⁵ atoms/cm² were achieved by applying microsecond negative voltage (-2 to -30 kV) pulses to the wafers at a frequency of 100 Hz to 1 kHz. After implantation the wafers were annealed using rapid thermal annealing (RTA) at 1060° C for 20 sec to activate the dopants and to recrystallize the implant damaged Si. For the PMOS process sequence both the Si source-drain and polycrystalline Si (poly-Si) gate doping steps were performed using PIII. The functionality of several types of devices, including diodes, capacitors, and transistors, were electrically measured to evaluate the compatibility of PIII with MOS process integration.     

Trench doping conformality by plasma immersion ion implantation(PIII)

Plasma immersion ion implantation (PIII) is a technique which can be used to conformally dope sidewalls of Si trenches. Using junction staining techniques and subsequently calibrating the observed stained depth to measured dose, dopant distributions inside Si trenches with aspect ratios ranging from 1 to 12 are studied for various bias voltages from 5 to 20 kV. Unlike conventional collimated beam implantation, PIII was able to conformally dope all aspect ratios studied with no evidence of abrupt discontinuities in the dopant distribution along the trench surface as a result of beam shadowing by trench geometry. Furthermore, it is shown that the higher implant biases results in more directional trajectories. Thus, dopant distributions along irregular geometries can be controlled by PDIII process conditions     

Characterization of ultra-shallow p+-n junction diodesfabricated by 500-eV boron-ion implantation

Ultrashallow gated diodes have been fabricated using 500-eV boron-ion implantation into both Ge-preamorphized and crystalline silicon substrates. Junction depths following rapid thermal annealing (RTA) for 10 s at either 950°C or 1050°C were determined to be 60 and 80 nm, respectively. These are reportedly the shallowest junctions formed via ion implantation. Consideration of several parameters, e.g. reduced B⁺ channeling, increased activation, and reduced junction leakage current, lead to the selection of 15 keV as the optimal Ge preamorphization energy. Transmission electron microscope results indicated that an 850°C/10-s RTA was sufficient to remove the majority of bulk defects resulting from the Ge implant. Resulting reverse leakage currents were as low as 1 nA/cm² for the 60-nm junctions and diode ideality factors for crystalline and preamorphized substrates ranged from 1.02 to 1.12. Even at RTA temperatures as low as 850°C, the leakage current was only 11 nA/cm ². The final junction depths were found to be approximately the same for both preamorphized and nonpreamorphized samples after annealing at 950°C and 1050°C. However, the preamorphized sample exhibited significantly improved dopant activation     

An evaluation of contamination from plasma immersion ion implantation on silicon device characteristics

Silicon devices including diodes, metal oxide semiconductor capacitors, and p-channel metal oxide semiconductor transistors were fabricated by plasma immersion ion implantation (PHI) doping technique using a microwave multipolar bucket plasma system. B₂H₆ diluted in helium (1%) was used as the gas source. The contamination by helium, hydrogen, iron, sodium, and aluminum impurities was evaluated by secondary ion mass spectrometry measurements. During PHI processing in an aluminum chamber with a stainless steel wafer holder, no aluminum and a dose of 4.1 x 10¹²/cm² of Fe were detected. Most of Fe ions were shielded by a thin layer of SiO₂ during the device fabrications. Good quality devices have been demonstrated including low reverse current of 15 nA/cm² (V_R = -5 V) in diodes and reasonable lifetimes of the minority carriers such as t_g = 55.0 μsec and = τ_r 54.2 μsec.     

Effects of aluminum incorporation on hafnium oxide film using plasma immersion ion implantation

The effects of aluminum implantation on HfO₂ thin films using plasma immersion ion implantation (Al–PIII samples) are investigated. X-ray photoelectron spectroscopy measurements reveal that most of the implanted aluminum atoms accumulated near the surface region of the oxide film. The greatly reduced leakage current, smaller flatband shift and steep transition from the accumulation to the depletion region in the capacitance–voltage characteristics for Al–PIII samples indicate that both bulk oxide and interface traps are significantly reduced by aluminum incorporation. Even though the aluminum concentration at the Si/HfO₂ interface is very low the results indicate that trace amount of aluminum at the interface leads to significant improvements in both material and electrical characteristics of the thin HfO₂ films.     

Charge retention improvement of charge-trapping type flash device by plasma immersion ion implantation

Electrical characteristics of charge trapping-type flash devices with HfAlO charge trapping layer nitrided by plasma immersion ion implantation (PIII) technique with different implantation energies and time are studied. Utilizing Fowler–Nordheim (FN) operation, the programming speed of flash memory with charge trapping layer nitrided at low implantation energy is faster than that of control sample. The erasing speed of PIII-treated sample is slightly slower than that of control one, which might be due to the formation of silicon nitride in the tunneling oxide. The retention characteristics of all PIII-treated samples are significantly improved. Different peak locations of implanted nitrogen concentrations are formed by different implantation energies, which cause various electrical characteristics of flash devices.     

GaN p–n junction diode formed by Si ion implantation into p-GaN

²⁸Si⁺ implantation into Mg-doped GaN, followed by thermal annealing in N₂ was performed to achieve n⁺-GaN layers. The carrier concentrations of the films changed from 3×10¹⁷ (p-type) to 5×10¹⁹ cm⁻³ (n-type) when the Si-implanted p-type GaN was properly annealed. Specific contact resistance (ρ_c) of Ti/Al/Pt/Au Ohmic contact to n-GaN, formed by ²⁸Si⁺ implantation into p-type GaN, was also evaluated by transmission line model. It was found that we could achieve a ρ_c value as low as 1.5×10⁻⁶ Ω cm² when the metal contact was alloyed in N₂ ambience at 600 °C. Si-implanted GaN p–n junction light-emitting diodes were also fabricated. Electroluminescence measurements showed that two emission peaks at around 385 and 420 nm were observed, which could be attributed to the near band-edge transition and donor-to-acceptor transition, respectively.     

Comparison of plasma formation in n+p and p+n and TRAPATT diodes

A numerical solution of the plasma-trapping part of the cycle for equivalent `N? and `P?-type TRAPATT diodes shows that, if the conventional criteria for plasma formation are used, the results predicted are contradictory to experimental observations. These calculations, however, do show evidence for a different physical mechanism of plasma formation, with negative electric fields, than has been assumed previously. This mechanism can help explain the observed superiority of `P?-type diodes. In addition, it is suggested that the material parameters of p?p+ epitaxial layers may be significantly different for the general run of wafers.     

Effects of nitrogen incorporation by plasma immersion ion implantation on electrical characteristics of high-k gated MOS devices

Nitridation treatments are generally used to enhance the thermal stability and reliability of high-k dielectric. It is observed in this work that, the electrical characteristics of high-k gated MOS devices can be significantly improved by a nitridation treatment using plasma immersion ion implantation (PIII). Equivalent oxide thickness, (EOT) and interface trap density of MOS devices are reduced by a proper PIII treatment. At an identical EOT, the leakage current of devices with PIII nitridation can be reduced by about three orders of magnitude. The optimal process conditions for PIII treatment include nitrogen incorporation through metal gate, ion energy of 2.5 keV, and implantation time of 15 min.     

激光气相化学诱导掺杂制作超薄结硅光电池及其参数研究

用XeCl准分子激光作光源,以BBr_3为工作物质,在n型硅片表面进行激光气相化学诱导掺杂硼,制作太阳电池。获得的PN结表面最大掺杂浓度为1.2×10~(21)B~+/cm~3;在10~(17)B~+/cm~3处的结深为0.08μm;未镀增透膜的光电转换效率为9.5％。     

Thermal stability of tantalum nitride diffusion barriers for Cu metallization formed using plasma immersion ion implantation

Plasma immersion ion implantation (PIII) technique was employed to form Tantalum nitride diffusion barrier films for copper metallization on silicon. Tantalum coated silicon wafers were implanted with nitrogen at two different doses. A copper layer was deposited on the samples to produce Cu/Ta(N)/Si structure. Samples were heated at various temperatures in nitrogen ambient. Effect of nitrogen dose on the properties of the barrier metal was investigated by sheet resistance, X-ray diffraction and scanning electron microscopy measurements. High dose nitrogen implanted tantalum layer was found to inhibit the diffusion of copper up to 700 °C.