Electrical characteristics of Au/<Emphasis Type="Italic">n</Emphasis>-GaAs structures with thin and thick SiO<Subscript>2</Subscript> dielectric layer

The aim of this study, to explain effects of the SiO₂ insulator layer thickness on the electrical properties of Au/n-GaAs Shottky barrier diodes (SBDs). Thin (60 Å) and thick (250 Å) SiO₂ insulator layers were deposited on n-type GaAs substrates using the plasma enganced chemical vapour deposition technique. The current-voltage (I–V) and capacitance-voltage (C-V) characteristics have been carried out at room temperature. The main electrical parameters, such as ideality factor (n), zero-bias barrier height (? _Bo ), series resistance (R _s ), leakage current, and interface states (N _ss ) for Au/SiO₂/n-GaAs SBDs have been investigated. Surface morphologies of the SiO₂ dielectric layer was analyzed using atomic force microscopy. The results show that SiO₂ insulator layer thickness very affects the main electrical parameters. Au/n-GaAs SBDs with thick SiO₂ insulator layer have low leakage current level, small ideality factor, and low interface states. Thus, Au/n-GaAs SBDs with thick SiO₂ insulator layer shows better diode characteristics than other.     

A study of the interface states in MIS-structures with thin SiO2 and SiOxNy layers using deep level transient spectroscopy

Deep level transient spectroscopy (DLTS) and quasistatic CV measurements were used for the study of the interface states of thin SiO₂ and SiO_xN_y layers of 6–9 nm thickness, grown by rapid thermal processing in O₂ or N₂O ambient. DLTS was applied either in the saturating pulse or in the small pulse (energy resolved) mode. From an Arrhenius evaluation of the peaks obtained by temperature-scan measurements with small pulse excitation we derived the distribution of the capture cross section σ_n in the upper half of the gap, which exhibits a drastic decrease towards the conduction band edge.     

Impact of nitrogen incorporation on interface states in (1 0 0)Si/HfO2

The energy distribution of (1 0 0)Si/HfO₂ interface states and their passivation by hydrogen are studied for different levels of nitrogen incorporation using different technological methods. The results are compared to those of N-free samples. The nitrogen in the (1 0 0)Si/HfO₂ entity is found to increase the trap density in the upper part of the Si band gap and to hinder the passivation of traps in molecular hydrogen in this energy range. At the same time, the passivation of fast interface traps in the lower part of the band gap proceeds efficiently, provided the thickness of the grown Si₃N₄ interlayer is kept minimal. However, the lowest achievable interface trap density below midgap is set by the presence of slow N-related states, likely related to traps in the insulator.     

A FinFET memory with remote carrier trapping in ONO buried insulator

Advanced FinFETs fabricated on SiO₂-Si₃N₄-SiO₂ (ONO) buried insulator are investigated for flash memory applications. Systematic measurements reveal that the Si₃N₄ layer can easily trap charges by applying appropriate drain bias. The amount of trapped/detrapped charges in the buried nitride is sensed remotely by gate coupling through the variation of the drain current flowing at the front-gate interface. The front-channel threshold voltage variation, ΔV_THF, resulting from the charge trapping, induces a hysteresis “window” proper to non-volatile memory devices. Finally, our measurements highlight the geometrical parameter effects on the memory window size.     

Carrier trapping centers and interface states induced by r.f. sputtering of molybdenum electrodes in MOS-structure diodes

Electronic properties of interface and oxide layers of Si MOS diodes with an r.f. sputtered molybdenum metal electrodes have been studied. A remarkable density increase of both oxide charge and interface states by the sputtering has been found. IMA data show that the sputtered Mo atoms are implanted into the SiO₂ less than 100 Å from the surface. It is also found from photo I–V data that the charge centroid in the SiO₂ is shifted to a depth of 100 Å below the SiO₂ surface. The energy distribution of the carrier trapping centers having a capture cross section of the order of 10^?13 to 10^?16 cm² has been observed. The interface states density can be reduced about one order of magnitude by an annealing in N₂ 10 min/H₂ 15 min/N₂ 10 min at 450°C. The mechanism of the increase of the carrier trapping centers and the interface states is also studied. Especially it is concluded that the increase of the interface states originates from the ultraviolet-light irradiation emitted from the plasma during the r.f. sputtering.     

Electrical characterisation of Si3N4/SiO2 double layers on p-type 6H–SiC

MNOS, MNS and MOS devices have been fabricated on p-type 6H–SiC substrates without epitaxial layers. They have been characterised using high frequency CV, GV, and IV measurements. The high frequency CV characteristics of p-type 6H–SiC MNOS structures indicate a very similar interface quality to p-type 6H–SiC MOS devices. A lower effective fixed insulator charge Q_I is found in MNOS devices with a higher oxide thickness x_ox. An x_ox of 10 nm is effective in avoiding charge instability. The effective fixed insulator charge Q_I can be modified in the 10 nm oxide SiC MNOS devices by injecting carriers into the nitride. Similar leakage current characteristics compared to p-type 6H–SiC MNS structures have been found for p-type 6H–SiC MNOS devices, but the SiO₂/Si₃N₄ insulator current is lower, particularly for positive electric fields. At the oxide breakdown limit (−10 MV/cm), Poole–Frenkel conduction is observed in the nitride for negative electric fields due to direct tunnelling of holes into the nitride.     

Nonvolatile Memories Using Quantum Dot (QD) Floating Gates Assembled on II–VI Tunnel Insulators

This paper presents preliminary data on quantum dot gate nonvolatile memories using nearly lattice-matched ZnS/Zn_0.95Mg_0.05S/ZnS tunnel insulators. The GeO _x -cladded Ge and SiO _x -cladded Si quantum dots (QDs) are self-assembled site-specifically on the II–VI insulator grown epitaxially over the Si channel (formed between the source and drain region). The pseudomorphic II–VI stack serves both as a tunnel insulator and a high-κ dielectric. The effect of Mg incorporation in ZnMgS is also investigated. For the control gate insulator, we have used Si₃N₄ and SiO₂ layers grown by plasma- enhanced chemical vapor deposition.     

On the SILC mechanism in MOSFET’s with ultrathin oxides

In this paper, n-channel MOSFET’s with oxides 1.2, 1.5 and 1.8 nm thick are studied. In such devices the trap assisted tunnelling (TAT) current required to fit the gate current vs. gate voltage, I_g(V_g), characteristics is thought to flow through Si–SiO₂ interface traps. After stress, it becomes a stress induced leakage current (SILC) which should allow to obtain interface trap density variations with stress. The TAT mechanism is discussed. Then, the Si–SiO₂ interface trap densities extracted using the SILC and charge pumping (CP) are compared. Much larger trap creation rates are viewed by the SILC with regard to CP, questioning the occurrence of the SILC through interface traps. To answer this question the interaction between SILC and CP measurements is investigated.     

Insights on trap generation and breakdown in ultra thin SiO2 and SiON dielectrics from low voltage stress-induced leakage current measurements

We review the advancements in the understanding of breakdown and trap generation that have been achieved using low voltage stress-induced leakage current as a probe of the interface states created during electrical stress of ultra thin SiO₂ and SiON gate dielectrics. The technique separates the effects of bulk and interface states on the post-stress I–V characteristics; senses interface traps at both contact interfaces, identifies the regime where interface rather than bulk state generation is the rate limiting step for breakdown, is useful for determining the operative trap creation processes, and reveals the role of trap generation mechanism in driving which stress-induced defect controls breakdown.     

Interface states and deep-level centers in silicon-on-insulator structures

Deep-level centers in a split-off silicon layer and trap levels were studied by deep-level transient spectroscopy both at the Si/SiO₂ interface obtained by direct bonding and also at the Si(substrate)/〈thermal SiO₂〉 interface in the silicon-on-insulator structures formed by bonding the silicon wafers and delaminating one of the wafers using hydrogen implantation. It is shown that the Si/〈thermal SiO₂〉 interface in a silicon-on-insulator structure has a continuous spectrum of trap states, which is close to that for classical metal-insulator-semiconductor structures. The distribution of states in the upper half of the band gap for the bonded Si/SiO₂ interface is characterized by a relatively narrow band of states within the range from E _c −0.17 eV to E _c −0.36 eV. Furthermore, two centers with levels at E _c −0.39 eV and E _c −0.58 eV are observed in the split-off silicon layer; these centers are concentrated in a surface layer with the thickness of up to 0.21 μm and are supposedly related to residual postimplantation defects. __________ Translated from Fizika i Tekhnika Poluprovodnikov, Vol. 35, No. 8, 2001, pp. 948–953. Original Russian Text Copyright ? 2001 by Antonova, Stano, Nikolaev, Naumova, Popov, Skuratov.     

Characterization of the switching in tunnel MISS devices

The observed bistable characteristics of metal-insulator-silicon switch (MISS) devices with moderate epi-layer doping levels are proven to be controlled by trap assisted tunneling. The switching current and the switching voltage are shown to depend on the reverse saturation current of the MIS substructure and on fabrication parameters (insulator thickness and epi-layer doping level). A method to obtain the metal-semiconductor barrier height, the injection factor at the interface and the trap density in the insulator is presented. The results have been applied to characterize AlSiO₂Si(n)Si(p⁺) structu in which the switching point and the reverse saturation current have been measured. The observed dispersion in the values of the current can be explained by assuming a unique value of the barrier height and the trap density for all devices, allowing the values of the tunneling damping factors to be different from those obtained in the two-band model, which validity is also discussed.     

Electrical characterization of ultrathin oxides of silicon grown by N2O plasma assisted oxidation

The ultrathin (2.0–3.5 nm) oxides of silicon have gained renewed importance in view of ultra large scale integration (ULSI) of the silicon devices. In the present investigation, the ultrathin oxides are grown on (100) oriented p-type single side polished silicon using N₂0 plasma assisted oxidation in a PECVD reactor at 200°C. The oxide growth as a function of oxidation time is studied. The oxidation growth conforms to the reaction limited regime. In order to understand the electrical quality of Si/ultrathin SiO₂ interface, Al-thin SiO₂-Si tunnel capacitors are fabricated and their capacitance-voltage (C-V) and current-voltage (I–V) characteristics are studied. The effect of annealing on these oxides (termed as “post oxidation annealing”) has also been studied. The C-V characteristics of tunnel capacitors with “as grown” oxide showed a frequency dependence, possibly due to the presence of large fast interface state density. These fast interface states are observed to decrease with increasing oxidation time. The tunnel capacitors that the oxides undergone “post oxidation annealing” (POA) at 350°C in N₂ ambient for 20 minutes have shown practically no frequency dependence of the C-V characteristics; this observation along with the data on I-V characteristics confirms that POA reduces the interface state density considerably. The forward and reverse currents of POA capacitors are observed to decrease considerably indicating the reduction in the trap assisted tunneling transport process across the tunnel insulator.     

Admittance spectroscopy of traps at the interfaces of (1 0 0)Si with Al2O3, ZrO2, and HfO2

Admittance (ac) measurements were carried out to determine the interface trap density (D_it) as a function of energy E in the Si bandgap at interfaces of Si with different insulating oxides (Al₂O₃, ZrO₂, HfO₂). The results are compared to those of the conventional thermal SiO₂/Si interface. The results show that a significant portion of the interface trap density in the as-deposited and de-hydrogenated samples is related to the amphoteric Si dangling bond defects (P_b0 -centers). The D_it is much enhanced for the Al-containing insulators as compared to Si/SiO₂ but can be reduced by annealing in O₂. As to annealing in H₂, efficient passivation of P_b0 centers by hydrogen is achieved for Si/ZrO₂ and Si/HfO₂ interfaces, yet it fails for Si/Al-containing oxide entities. Among the insulators studied, the results suggest HfO₂ to be the best choice of an alternative insulator.     

Nitrogen implantations for rapid thermal oxinitride layers

Oxidation of nitrogen implanted substrates results in so called silicon-oxinitride layers (Si_xO_yN_z layers) which are dependent on implantation dose and energy always thinner than pure silicon-oxides (SiO₂) produced under the same oxidation conditions. Elastic recoil detection profiles indicate that the implanted nitrogen diffuses out of the substrate into the silicon-oxide layer what improves the electrical quality of these insulators. The Si_xO_yN_z layers show lower Fowler–Nordheim tunnelling currents as well as lower interface state densities (D_it) than the corresponding SiO₂ layers or N₂O–silicon-oxinitride insulators. NH₃–Si_xO_yN_z layers show the lowest D_it values because of H₂-annealing effects but contain fixed charges.     

高介电常数栅介质/二氧化硅界面偶极子成因研究

The formation of an electric dipole at the high-k/SiO2 interface is quantitatively analyzed. The band lineups and physical origin of dipole formation at the high-k/SiO2 interface are explained by the dielectric contact induced gap states(DCIGS). The charge neutrality level(CNL) of the DCIGS, which represents a distribution of high-k and SiO2 contact induced gap states, is utilized to study the dipole moment. The charge transfer due to different CNLs of high-k and SiO2 is considered as the dominant origin of dipole formation. The theoretically calculated dipole strengths of high-k/SiO2 systems based on this model are in good agreement with the experimental data.     

Potentiality of trap charge effects and SiON induced interface defects in a-Si3N4/SiON based MIS structure for resistive NVM device

Potential application of amorphous silicon nitride (a-Si₃N₄)/silicon oxy-nitride (SiON) film has been demonstrated as resistive non-volatile memory (NVM) device by studying the Al/Si₃N₄/SiON/p-Si metal–insulator–semiconductor (MIS) structure. The existence of several deep trap states was revealed by the photoluminescence characterizations. The bipolar resistive switching operation of this device was investigated by current–voltage measurements whereas the trap charge effect was studied in detail by hysteresis behavior of frequency dependent capacitance–voltage characteristics. A memory window of 4.6 V was found with the interface trap density being 6.4 × 10¹¹ cm⁻² eV⁻¹. Excellent charge retention characteristics have been observed for the said MIS structure enabling it to be used as a reliable non-volatile resistive memory device.     

Stability of SCCDs with extremely low interface state density

Very low fast defect state densities (N_IT) at the SiSiO₂ interface can be obtained using annealing with a layer containing hydrogen. These hydrogenated interface states, enabling SCCDs with low transfer inefficiencies have been investigated by means of conductance measurements under bias temperature stress. The least stable conditions occur with negative gate voltage, where N_IT reacts more sensitively than for a normally grown oxide due presumably to the dissociation of Si_sH bonds and reaction of H with a new oxide trap.     

Improved Interface and Electrical Properties by Inserting an Ultrathin SiO2 Buffer Layer in the Al2O3/Si Heterojunction

An ultrathin SiO₂ interfacial buffer layer is formed using the nitric acid oxidation of Si (NAOS) method to improve the interface and electrical properties of Al₂O₃/Si, and its effect on the leakage current and interfacial states is analyzed. The leakage current density of the Al₂O₃/Si sample (8.1 × 10^?9 A cm^?2) due to the formation of low‐density SiO_x layer during the atomic layer deposition (ALD) process, decreases by approximately two orders of magnitude when SiO₂ buffer layer is inserted using the NAOS method (1.1 × 10^?11 A cm^?2), and further decreases after post‐metallization annealing (PMA) (1.4 × 10^?12 A cm^?2). Based on these results, the influence of interfacial defect states is analyzed. The equilibrium density of defect sites (N_d) and fixed charge density (N_f) are both reduced after NAOS and then further decreased by PMA treatment. The interface state density (D_it) at 0.11 eV decreases about one order of magnitude from 2.5 × 10¹² to 7.3 × 10¹¹ atoms eV^?1 cm^?2 after NAOS, and to 3.0 × 10¹⁰ atoms eV^?1 cm^?2 after PMA. Consequently, it is demonstrated that the high defect density of the Al₂O₃/Si interface is drastically reduced by fabricating ultrathin high density SiO₂ buffer layer, and the insulating properties are improved.     

Variations of trap states and dangling bonds in CVD Si3N4 layer on Si substrate by NH3/SiH4 ratio

This study is concerned with deep trap densities and energy levels in CVD Si₃N₄ layers deposited on Si substrates at 700°C with various gas flow ratio NH₃/SiH₄. As the ratio NH₃/SiH₄ increases from 10 to 1000, the trap density decreases from 8 × 10^l9 t0 2 x l0¹⁹cm⁻³, and energetical distribution of trap states becomes lower and/or electron emission probability from trap states less. The results are discussed in terms of chemical and optical properties of Si₃N₄ film revealed by infrared absorption, Auger electron spectroscopy, and ellipsometry. It is shown that (i) Si dangling bonds create deep trap states and (ii) 0 and H atoms act as terminators to decrease trap density. A part of this paper was presented at the 23rd Annual Electronic Materials Conference, University of California, Santa Barbara, 1981. On leave from Yasu Plant, IBM Japan Ltd., Yasu-cho Shiga 520-23, Japan.     

On the influence of substrate cleaning method and rapid thermal annealing conditions on the electrical characteristics of Al/SiNx/SiO2/Si fabricated by ECR-CVD

We investigate the influence of the used cleaning method and rapid thermal annealing (RTA) conditions on the electrical characteristics of MIS devices based on SiN_y:H/SiO_x dielectric stack structures fabricated by electron-cyclotron-resonance plasma assisted chemical vapour deposition (ECR-CVD). We use capacitance–voltage (C–V) technique to study charge trapped in the insulator, Deep Level Transient Spectroscopy (DLTS) to study the trap distributions at the interface, and conductance transient (G–t) technique to determine the energy and geometrical profiles of electrically active defects at the insulator bulk as these defects follow the disorder-induced gap state (DIGS) model.