Stacked PMOS clamps for high voltage power supply protection

Large p-channel MOS (PMOS) field-effect transistors (FETs) with multiple gates can be arranged to provide ESD protection to high voltage on-chip power supplies in submicron integrated circuits. These clamps divide the supply voltage among several gate oxides; the circuitry accompanying the large series FETs provides near-maximum gate drive during the ESD for high pulsed current. Layouts are densely packed because minimum dimensions can be used and because no contact is needed between the stacked gates. The designs for high voltage are extensions of the large PMOS FET ESD clamps and timed drive circuitry that are used to clamp ordinary on-chip power supply lines.     

Techniques for measurement of input impedances of electronicequipment in the frequency range from 1 MHz to 1 GHz

Electromagnetic interference (EMI) can couple to electronic equipment through any number of interfaces of the equipment to its external environment, e.g. power and input/output signal cables or ventilation slots. The power cable interface to the equipment's power supply is investigated. Input impedances of power supplies in various electronic equipment operating under normal active conditions were measured in the common mode (phase-ground) from 1 MHz to 1 GHz. Such a wide frequency range is useful in studies of wideband EMI such as electrostatic discharge (ESD). The results of these measurements are discussed, and the possibilities of using them in further work are suggested     

2.4GHz低噪声放大器的全芯片ESD保护设计

设计并流片验证了一种0.18μmRFCMOS工艺的2.4GHz低噪声放大器的全芯片静电放电(ESD)保护方案。对于射频(RF)I/O口的ESD防护,主要对比了二极管、可控硅(SCR)以及不同版图的互补型SCR,经流片与测试,发现岛屿状互补型SCR对I/O端口具有很好的ESD防护综合性能。对于电源口的ESD防护,主要研究了不同触发方式的ESD保护结构,结果表明,RCMOS触发SCR结构(RCMOS-SCR)具有良好的ESD鲁棒性和开启速度。基于上述结构的全芯片ESD保护设计,RF I/O口采用岛屿状布局的互补SCR结构的ESD防护设计,该ESD防护电路引入0.16dB的噪声系数和176fF的寄生电容,在人体模型(HBM)下防护能力可达6kV;电源口采用了RCMOS-SCR,实现了5kV HBM的ESD保护能力,该设计方案已经在有关企业得到应用。     

ESD protection design to overcome internal damage on interface circuits of a CMOS IC with multiple separated power pins

This paper reports a real case of electrostatic discharge (ESD) improvement on a complementary metal oxide semiconductor integrated circuit (IC) product with multiple separated power pins. After ESD stresses, the internal damage have been found to locate at the interface circuit connecting between different circuit blocks with different power supplies. Some ESD designs have been implemented to rescue this IC product to meet the required ESD specification. By adding only an extra ESD clamp N-channel metal oxide semiconductor with a channel width of 10 /spl mu/m between the interface node and the ground line, the human-body-model (HBM) ESD level of this IC product can be improved from the original 0.5 to 3 kV. By connecting the separated vertical sync signal (VSS) power lines through the ESD conduction circuit to a common VSS ESD bus realized by the seal ring, the HBM ESD level of the enhanced version IC product with 12 separated power supplies pairs can be significantly improved from original 1 kV up to > 5 kV, without the noise coupling issue.     

电源技术的应用研究与发展趋势

电源设计是电路设计中的重要部分,电源的稳定性在很大程度上决定了电路的稳定性。本文从电源技术的发展历程出发,详细介绍了线性电源和开关电源的工作原理及二者的区别,并指出未来电源＂两高两低＂的发展趋势。＂绿色电源＂已经成为下一代电源产品的发展方向。     

Gate-controlled field-effect diodes and silicon-controlled rectifier for charged-device model ESD protection in advanced SOI technology

Silicon-controlled rectifier (SCR) devices are used as local clamping ESD devices. However, conventional designs suffer from slow turn-on, which causes problems in sub 10 ns charged-device model (CDM) protection, especially in deeply scaled technologies. In this paper, a double-well field-effect diode (DWFED) and an improved field-effect diode (FED) are designed to address this challenge. They are fabricated and characterized in 45 nm silicon-on-insulator (SOI) technology and experimentally demonstrated to be suitable for pad-based local clamping under a normal supply voltage (V_dd) range (at or below 1 V) in high-speed applications. ESD protection capabilities are investigated using very fast transmission line pulse (VF-TLP) tests to predict the device performance in CDM events. FED’s advantages in improving transient turn-on behavior and reducing DC leakage current are analyzed and compared with the regular SCR and the DWFED. Technology CAD (TCAD) simulations are used to interpret turn-on behavior and guide design. The improved devices may be implemented in a local clamping scheme that expands the ESD design window for advanced technology nodes.     

高鲁棒性N型沟道RF-LDMOS在TLP应力下的电学机理研究

提高射频功率器件的鲁棒性有利于增强器件的抗静电放电能力和抗失配能力.为了直观地了解器件内部发生的电学过程，本文研究了高鲁棒性N型沟道RF-LDMOS（Radio Frequency Lateral Diffusion MOS）在TLP（Transmission Line Pulse）应力下的电学机理.利用0.18μm BCD（Bipolar/CMOS/DMOS）先进制程，实现了特定尺寸器件的设计与流片.通过实测与仿真的对比，发现静电放电失效的随机性、芯片内部的热效应是导致仿真和实测差异的非理想因素.通过对TLP仿真的各阶段重要节点的分析，证明了源极下方的P型埋层有利于提高空穴电流的泄放能力，从而提高RF-LDMOS的鲁棒性.     

A High Gain and Low Supply Voltage LNA for the Direct Conversion Application With 4-KV HBM ESD Protection in 90-nm RF CMOS

A 2.4-GHz low noise amplifier (LNA) for the direct conversion application with high power gain, low supply voltage and plusmn4 KV human body model (HBM) electrostatic discharge (ESD) protection level implemented by a 90-nm RF CMOS technology is demonstrated. At 12.9 mA of current consumption with a supply voltage of 1.0 V, the LNA delivers a power gain of 21.9 dB and the noise figure (NF) of 3.2 dB, while maintaining the input and output return losses below -11 dB and -18.3 dB, respectively. The power gain and NF are only 0.2 dB lower and 0.64 dB higher than those of LNA without ESD protection     

Circular under-pad multiple-mode ESD protection structure for ICs

A novel circular pad-oriented low-parasitic all-mode electrostatic discharge (ESD) protection structure is designed in BiCMOS for RF and mixed-signal (MS) ICs, featuring tunable triggering, low voltage clamping (~2 V), low discharge impedance (~Ω) and low leakage current (~pA). It consumes limited silicon and achieves 14 kV ESD protection     

1.5 V high-speed electrostatic discharge free BiCMOS digitalcircuit

A novel circuit design that effectively eliminates the need for input protection circuits is described. Besides having an excellent electrostatic discharge (ESD) robustness, the simulation results have shown that this design outperforms current BiCMOS circuits in terms of speed, power, crossover capacitance, and chip area for a wide range of load capacitances, power supply voltages and technologies. The proposed circuit remains functional after an ESD test     

一种低功耗的PDP驱动波形设计

介绍了一种新型的三电极表面放电型等离子体的驱动方法,与传统驱动方法相比较,可以减少所用电源的个数,降低所需电源的电压.     

Novel ESD strategy for high voltage non-volatile programming pin application

This paper presents a novel ESD strategy for non-volatile memory (NVM) programming pin in a 0.13um/30V technology. Suggested scheme can provide not only a major current discharge path to protect the internal circuit from ESD damage but also a voltage clamping function to prevent the soft error of programmed data during the ESD event. It has been validated by TLP experiments and TCAD simulation.     

High holding current SCRs (HHI-SCR) for ESD protection and latch-up immune IC operation

This paper presents a novel Silicon Controlled Rectifier (SCR) for power line and local I/O ESD protection. The High holding current SCRs (HHI-SCR) exhibits a dual ESD clamp characteristic: low-current high-voltage clamping and high-current low-voltage clamping. These operation modes enable latch-up immune normal operation as well as superior full chip ESD protection. The minimum latch current can be controlled by specific SCR design. The HHI-SCR is demonstrated in a 0.10 μm-CMOS and in a 0.4 μm-BiCMOS technology. The design is area efficient.     

基于增量负载扰动和最小二乘拟合的通信电源效率测量法

为了克服传统的通信电源效率测量方法在实际操作中的困难,提出了一种基于增量负载扰动和最小二乘拟合的通信电源效率测量方法。对于工作在＂效率—输出负载电流＂曲线中段的通信电源,对其施加增量负载扰动,并运用最小二乘拟合去除测量中奇异点对结果的影响,最终得到通信电源的效率。本文列出了运用该方法测得的实验结果,并讨论了实验结果的相对误差。通过该方法也可以对通信电源的欠载或过载状态进行定性的判断。最后本文提出了该方法在通信电源规模生产的自动化测试中的应用。因此该方法是一种实用的新型通信电源效率测量方法。     

Low-power CMOS digital design with dual embedded adaptive powersupplies

A low-power CMOS design methodology with dual embedded adaptive power supplies is presented. A variable supply-voltage scheme for dual power supplies, namely, the dual-VS scheme, is presented. It is found that the lower supply voltage should be set at 0.7 of the higher supply voltage to minimize chip power dissipation. This knowledge aids designers in the decision of the optimal supply voltages within a restricted design time. An MEPG-4 video codec chip is designed at 2.5 and 1.75 V for internal circuits that are generated from an external power supply of 3.3 V by the dual-VS circuits. Power dissipation is reduced by 57% without degrading circuit performance compared to a conventional CMOS design     

高功率激光器新型谐振变换型开关电源

采用新型谐振技术,成功地研制出激励高功率激光器的零电流开关谐振式开关电源,其工作频率为５０ｋＨｚ,功率转换效率为８２％以上,输出电流为０～８０ｍＡ连续可调,放电电流波动小于±１ｍＡ。实现了功率管的低损耗工作,无需镇流电阻实现稳定放电,使起辉电流及电流的稳定度与放电管气体浓度和气压等无关。     

On a dual-polarity on-chip electrostatic discharge protectionstructure

A novel dual-polarity on-chip electrostatic discharge (ESD) protection structure is designed. The new ESD structure protects IC chips against ESD stressing in the two opposite directions. The ESD structure features symmetric deep-snapback current-voltage (I-V) characteristics, low-impedance active overcurrent discharging path, low holding voltage for overvoltage clamping, fast ESD response of ~0.18 ns, low leakage (~pA), adjustable triggering voltage, and good scalability. It passes 14 KV HBM ESD zapping tests and achieves high ESD-performance-to-Si ratio of ~80 V/μm width. The new ESD structure reduces Si areas consumed by ESD protection units and ESD-induced parasitic effects significantly     

IC设计中的ESD保护技术探讨

ESD是集成电路设计中最重要的可靠性问题之一。IC失效中约有40%与ESD/EOS(电学应力)失效有关。为了设计出高可靠性的IC,解决ESD问题是非常必要的。文中讲述一款芯片ESD版图设计,并且在0.35μm 1P3M 5V CMOS工艺中验证,成功通过HBM-3000V和MM-300V测试。这款芯片的端口可以被分成输入端口、输出端口、电源和地。为了达到人体放电模型(HBM)-3000V和机器放电模型(MM)-300V,首先要设计一个好的ESD保护网络。解决办法是先让ESD的电荷从端口流向电源或地,然后从电源或地流向其他端口。其次,给每种端口设计好的ESD保护电路,最后完成一张ESD保护电路版图。     

Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS

On-chip decoupling capacitors (decaps) in the form of MOS transistors are widely used to reduce power supply noise. This paper provides guidelines for standard cell layouts of decaps for use within Intellectual Property (IP) blocks in application-specific integrated circuit (ASIC) designs. At 90-nm CMOS technology and below, a tradeoff exists between high-frequency effects and electrostatic discharge (ESD) reliability when designing the layout of such decaps. In this paper, the high-frequency effects are modeled using simple equations. A metric is developed to determine the optimal number of fingers based on the frequency response. Then, a cross-coupled design is described that has been recently introduced by cell library developers to handle ESD problems. Unfortunately, it suffers from poor response times due the large resistance inherent in its design. Improved cross-coupled designs are presented that properly balance issues of frequency response with ESD performance, while greatly reducing thin-oxide gate leakage.      

由版图引起的CMOS ESD保护电路失效的分析

ESD保护电路已经成为CMOS集成电路不可或缺的组成部分,在当前CMOS IC特征尺寸进入深亚微米时代后,如何避免由ESD应力导致的保护电路的击穿已经成为CMOS IC设计过程中一个棘手的问题.光发射显微镜利用了IC芯片失效点所产生的显微红外发光现象可以对失效部位进行定位,结合版图分析以及微分析技术,如扫描电子显微镜SEM、聚焦离子束FIB等的应用可以揭示ESD保护电路的失效原因及其机理.通过对两个击穿失效的CMOS功率ICESD保护电路实际案例的分析和研究,提出了改进ESD保护电路版图设计的途径.