Surface‐Modified High‐k Oxide Gate Dielectrics for Low‐Voltage High‐Performance Pentacene Thin‐Film Transistors

In this study, pentacene thin‐film transistors (TFTs) operating at low voltages with high mobilities and low leakage currents are successfully fabricated by the surface modification of the CeO₂–SiO₂ gate dielectrics. The surface of the gate dielectric plays a crucial role in determining the performance and electrical reliability of the pentacene TFTs. Nearly hysteresis‐free transistors are obtained by passivating the devices with appropriate polymeric dielectrics. After coating with poly(4‐vinylphenol) (PVP), the reduced roughness of the surface induces the formation of uniform and large pentacene grains; moreover, –OH groups on CeO₂–SiO₂ are terminated by C₆H₅, resulting in the formation of a more hydrophobic surface. Enhanced pentacene quality and reduced hysteresis is observed in current–voltage (I–V) measurements of the PVP‐coated pentacene TFTs. Since grain boundaries and –OH groups are believed to act as electron traps, an OH‐free and smooth gate dielectric leads to a low trap density at the interface between the pentacene and the gate dielectric. The realization of electrically stable devices that can be operated at low voltages makes the OTFTs excellent candidates for future flexible displays and electronics applications.     

Radiation damage and its effect on hot-carrier induced instability of 0.5 μm CMOS devices patterned using synchrotron x-ray lithography

The device characteristics and the radiation damgae ofn-channel andp-channel MOSFETs patterned using synchrotron x-ray lithography are examined. The effect of radiation damage caused by x-ray lithography on the device reliability during hot electron injection is investigated. In addition to neutral traps, large amounts of positive oxide charge and interface states, particularly acceptor-like interface states, which cause degradation of MOSFET characteristics are found to be created by x-ray irradiation during the lithography process. Although several annealing steps are performed throughout the entire fabrication process, the radiation damage, particularly neutral traps, is not completely annealed out. The hot-electron induced instability inp-channel MOSFETs is significantly increased due to the enhanced electron trapping in the oxide by residual traps. The effect of radiation damage on hot electron induced instability is found to be more severe inn ⁺-poly buried-channelp-MOSFETs than inp ⁺-poly surface-channel p-MOSFETs. However, the degradation inn-channel MOSFETs due to channel hot carriers is not significantly increased by x-ray lithography. These results suggest that the major degradation mechanism due to hot-carrier inp-channel MOSFETs is electron trapping and inn-channel MOSFETs is interface state generation. It also suggests thatp-channel MOSFETs, in addition ton-channel MOSFETs, needs to be carefully examined in terms of hot carrier induced instability in CMOS VLSI circuits patterned using x-ray lithography.     

Effect of hydrogen annealing on hot-carrier instability of X-Ray irradiated CMOS devices

In the very large scale integration (VLSI) technology, the need for high density and high performance integrated circuit (IC) chip demands advanced processing techniques that often result in the generation of high energy particles and photons. Frequently, the radiation damage are introduced by these energetic particles and photons during device processing. The radiation damage created by x-ray irradiation, which can often occur during metal sputtering process, has been shown to potentially enhance hot-carrier instability if the neutral traps which act as electron or hole traps in the silicon dioxide is not annealed out. In this paper, we investigate the effects of annealing using different hydrogen contents and temperatures on the device characteristics and hot carrier instability of 0.5 μm CMOS devices after 1500 mJ/cm² synchrotron x-ray irradiation. Three different annealing conditions were employed; 400° C H₂, 450° C H₂, and 400° C H₂ + N₂. It is found that for all three different hydrogen anneals the normal characteristics of irradiated CMOS devices can be effectively recovered. The hot-carrier instability of bothp- andn-channel MOSFETs are significantly enhanced after x-ray irradiation due to the creation of neutral traps and positively charged oxide traps. After high H₂ (100%) concentration anneals at 450° C, the hot-carrier instability in irradiatedn-channel devices is greatly reduced and comparable to the non-irradiated devices. Although the hot-carrier instability inp-channel devices is also significantly reduced after annealing, the threshold voltage shifts are still enhanced as compared to the devices without exposure to x-ray irradiation during maximum gate current stress. For those non-irradiated, but hydrogen-annealedp-channel devices, the hot-carrier instability was observed to be worse than the non-irradiated device without hydrogen annealing.     

Fluorinated Organic A-Cation Enabling High-Performance Hysteresis-Free 2D/3D Hybrid Tin Perovskite Transistors

2D tin-based perovskites have gained considerable attention for use in diverse optoelectronic applications, such as solar cells, lasers, and thin-film transistors (TFTs), owing to their good stability and optoelectronic properties. However, their intrinsic charge-transport properties are limited, and the insulating bulky organic ligands hinder the achievement of high-mobility electronics. Blending 3D counterparts into 2D perovskites to form 2D/3D hybrid structures is a synergistic approach that combine the high mobility and stability of 3D and 2D perovskites, respectively. In this study, reliable p-channel 2D/3D tin-based hybrid perovskite TFTs comprising 3D formamidinium tin iodide (FASnI₃) and 2D fluorinated 4-fluoro-phenethylammonium tin iodide ((4-FPEA)₂SnI₄) are reported. The optimized FPEA-incorporated TFTs show a high hole mobility of 12 cm² V⁻¹ s⁻¹, an on/off current ratio of over 10⁸, and a subthreshold swing of 0.09 V dec⁻¹ with negligible hysteresis. This excellent p-type characteristic is compatible with n-type metal-oxide TFT for constructing complementary electronics. Two procedures of antisolvent engineering and device patterning are further proposed to address the key concern of low-performance reproducibility of perovskite TFTs. This study provides an alternative A-cation engineering method for achieving high-performance and reliable tin-halide perovskite electronics.     

Active Layer Thickness Effects on the On-State Current and Pulse Measurement at Room Temperature on Deposited Zinc Oxide Thin-Film Transistors

This study reports on the fabrication of thin-film transistors (TFTs) with transparent zinc oxide (ZnO) semiconductors serving as the active channel and silicon dioxide (SiO₂) serving as the gate insulator. The ZnO films were deposited by radiofrequency magnetron sputtering at room temperature. Moreover, the effects of channel thickness on the structural and pulse current?Cvoltage characteristics of ZnO TFTs using a bottom gate configuration were investigated. As the channel thickness increased, the crystalline quality and the channel conductance were enhanced. The electrical characteristics of TFTs exhibited field-effect mobilities of 8.36?cm²/Vs to 16.40?cm²/Vs and on-to-off current ratios of 10⁸ to 10⁷ for ZnO layer thickness of 45?nm and 70?nm, respectively. The threshold voltage was in the range of 10?V to 31?V for ZnO layer thicknesses from 35?nm to 70?nm, respectively. The low deposition and processing temperatures make these TFTs suitable for fabrication on flexible substrates.     

Experimental investigation on liquid-phase fabrication techniques for multilayer infrared hollow fiber

Infrared hollow fiber with metal and dielectric inner-coatings has found applications in medical and industrial fields. It is a commonly used method to lower the loss by inner-coating multi dielectric layers. In this paper, SiO₂ and AgI were selected to fabricate the multilayer mid-infrared hollow fiber. Liquid-phase coating techniques were experimentally discussed in order to control the film thickness. It is shown that concentration and flow speed of the coating solution are key parameters to modify SiO₂ film thickness. AgI film was obtained by firstly coating a silver layer and then iodinating the silver layer into AgI. SiO₂ and AgI films were deposited orderly on the inner wall of a 0.7-mm bore glass capillary. Both thicknesses for SiO₂ and AgI films were well controlled and optimized according to the theoretical calculation. The measured infrared loss spectrum of SiO₂/AgI/SiO₂/Ag multilayer hollow fiber has a good agreement with the calculated result and shows band gap effect around the wavelength of 5.3 μm.     

Synthesis and Characterization of Magnesium-Alloyed Hematite Thin Films

We have synthesized pure and Mg-alloyed hematite thin films on F-doped, SnO₂-coated glass substrates by radiofrequency magnetron cosputtering of iron oxide with and without MgO sources in mixed Ar/O₂ and mixed N₂/O₂ ambient. We found that hematite films deposited in N₂/O₂ ambient exhibited much poorer crystallinity than those deposited in Ar/O₂ ambient. We determined that Mg alloying led to increased crystallinity and bandgap. Furthermore, we found that Mg alloying inverted the type of conductivity of the thin films: pure hematite thin films exhibited n-type conductivity, whereas Mg-alloyed hematite thin films exhibited p-type conductivity.     

Influence of the channel layer thickness on electrical properties of indium zinc oxide thin-film transistor

Thin-film transistors (TFTs) were fabricated on SiO₂/n⁺-Si substrates using amorphous binary In₂O₃-ZnO (a-IZO) films with different thickness for active channel layers deposited by the rf magnetron sputtering at room temperature. The performance of devices was found to be thickness dependent. With the active layer thickness from 33 to 114 nm, the field-effect mobility μ_FE increased from 1.60 to 4.59 cm²/V s, the threshold voltage V_TH decreased from 62.26 to 20.82 V, and the subthreshold voltage swing S decreased from 4.06 V/decade to 1.30 V/decade. Further, the dependence of TFTs’ electrical properties on active layer thickness was investigated in detail on the basis of free carrier density and interface scattering.     

Temperature-dependent ambipolar electrical characteristics of pentacene-based thin-film transistors: The impact of opposite-sign charge carriers

The temperature-dependent electrical and charge transport characteristics of pentacene-based ambipolar thin-film transistors (TFTs) were investigated at temperatures ranging from 77 K to 300 K. At room temperature (RT), the pentacene-based TFTs exhibit balanced and high charge mobility with electron (μ_e) and hole (μ_h) mobilities, both at about 1.6 cm²/V s. However, at lower temperatures, higher switch-on voltage of n-channel operations, almost absent n-channel characteristics, and strong temperature dependence of μ_e indicated that electrons were more difficult to release from opposite-signed carriers than that of holes. We observed that μ_e and μ_h both followed an Arrhenius-type temperature dependence and exhibited two regimes with a transition temperature at approximately 210–230 K. At high temperatures, data were explained by a model in which charge transport was limited by a dual-carrier release and recombination process, which is an electric field-assisted thermal-activated procedure. At T < 210 K, the observed activation energy is in agreement with unipolar pentacene-based TFTs, suggesting a common multiple trapping and release process-dominated mechanism. Different temperature-induced characteristics between n- and p-channel operations are outlined, thereby providing important insights into the complexity of observing efficient electron transport in comparison with the hole of ambipolar TFTs.     

Optical and Electrical Properties of TixSi1‐xOy Films

Ti_xSi_1xO_y (TSO) thin films are fabricated using plasma‐enhanced atomic layer deposition. The Ti content in the TSO films is controlled by adjusting the sub‐cycle ratio of TiO₂ and SiO₂. The refractive indices of SiO₂ and TiO₂ are 1.4 and 2.4, respectively. Hence, tailoring of the refractivity indices from 1.4 to 2.4 is feasible. The controllability of the refractive index and film thickness enables application of an antireflection coating layer to TSO films for use as a thin film solar cell. The TSO coating layer on an Si wafer dramatically reduces reflectivity compared to a bare Si wafer. In the measurement of the current‐voltage characteristics, a nonlinear coefficient of 13.6 is obtained in the TSO films.     

Atomic-layer-deposited silicon-nitride/SiO2 stack––a highly potential gate dielectrics for advanced CMOS technology

An extremely thin (2 monolayers) silicon nitride layer has been deposited on thermally grown SiO₂ by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness (T_eq=2.2 nm) efficiently reduce the boron diffusion from p⁺ poly-Si gate without the pile up of nitrogen atoms at the SiO₂/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO₂ especially in the thin (<0.5 nm) thickness region.An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO₂ stack gate dielectrics compared with those of conventional SiO₂ dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO₂ and SiO₂/Si-substrate interfaces for the SiO₂ gate dielectrics and only near the SiO₂/Si-substrate interface for the stack gate dielectrics.Employing annealing in NH₃ at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO₂, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH₃ annealing.Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.     

Spatial Localization of Carrier Traps in 4H-SiC MOSFET Devices Using Thermally Stimulated Current

Carrier traps in 4H-SiC metal–oxide–semiconductor (MOS) capacitor and transistor devices were studied using the thermally stimulated current (TSC) method. TSC spectra from p-type MOS capacitors and n-channel MOS field-effect transistors (MOSFETs) indicated the presence of oxide traps with peak emission around 55 K. An additional peak near 80 K was observed due to acceptor activation and hole traps near the interface. The physical location of the traps in the devices was deduced using a localized electric field approach. The density of hole traps contributing to the 80-K peak was separated from the acceptor trap density using a gamma-ray irradiation method. As a result, hole trap density of N _t,hole = 2.08 × 10¹⁵ cm⁻³ at 2 MV/cm gate field and N _t,hole = 2.5 × 10¹⁶ cm⁻³ at 4.5 MV/cm gate field was extracted from the 80-K TSC spectra. Measurements of the source-body n ⁺–p junction suggested the presence of implantation damage in the space-charge region, as well as defect states near the n ⁺ SiC substrate.     

Characterization of ultra-thin SiO2 by capacitance-voltage and charge pumping measurements

In this paper, we present results on electrical measurements of ultra thin SiO₂ layers (from 3.5 nm down to 1.7 nm), used as gate dielectric in metal-oxide-semiconductors (MOS) devices. Capacitance-voltage (C-V) measurements and simulations on MOS capacitors have been used for extracting the electrical oxide thickness. The SiO₂/Si interface and oxide quality have been analyzed by charge pumping (CP) measurements. The mean interface traps density is measured by 2-level CP, and the energy distribution within the semiconductor bandgap of these traps are investigated by 3-level charge pumping measurements. A comparison of the energy distribution of the SiO₂/Si interface traps is made using classical and quantum simulations to extract the surface potential as a function of the gate signal. When the gate oxide thickness <3.5 nm, we prove that it is mandatory to take into account the quantum effects to obtain a more accurate energy distribution of the SiO₂/Si interface traps. We also explain the increase of the apparent interface traps density measured by 2-levels CP with the increase of the oxide thickness, for transistors made from the same technological process.     

ZnO TFT Devices Built on Glass Substrates

ZnO thin-film transistors (TFTs) were built on glass substrates. The device with a top gate configuration operates in the depletion mode. The ZnO channel was grown by metalorganic chemical vapor deposition (MOCVD) on glass at low temperature. SiO₂ was used as the gate dielectric. The TFT has an on/off ratio of ∼4.0 × 10⁴ and a channel field-effect mobility of ∼4.0 cm²/V s. The average transmittance of the ZnO film in the visible wavelength is ∼80%. To compare the characteristics of the TFTs prepared by using a poly-ZnO and epitaxial-ZnO channel, an epi-ZnO TFT with the same configuration and dimensions was made on an r-Al₂O₃ substrate. The epi-ZnO TFT shows higher field-effect mobility of ∼35 cm²/V s and on/off ratio of ∼10⁸.     

SiO2 single layer for reduction of the standing wave effects in the interference lithography of deep photoresist structures on Si

We demonstrate that the use of a single SiO₂ film, with thickness corresponding to one standing wave (SW) period allows the recording of deep photoresist structures on silicon substrates by laser interference, without use of any additional antireflecting coating. This condition corresponds just to the opposite thickness (half SW period) previously proposed for using the SiO₂ films for phase-shifting the SW pattern. Theoretical and experimental results demonstrated that for the lithography of deep structures, the contrast of the SW pattern, the minimum light intensity of the SW pattern and the photoresist adhesion are the most important parameters of the process.     

Velocity of surface carriers in inversion layers on silicon

Velocity-field curves for surface free-carriers in silicon are determined from measurements on resistivegate IGFETs. The measurements were performed on n-channel devices fabricated on both (100) and (111) substrates and on p-channel devices fabricated on (100) substrates. The channel length of the devices is ～8 μm and the impurity concentration of the substrates is ～ 10¹⁵ cm^?3. The dependence of velocity on the field strength along the channel is found to be well approximated by an empirical relationship involving three parameters: low-field mobility μ₀, a critical field $\text{E}{}_{\mathrm{cy}}$ signalling the onset of velocity saturation, and a parameter α that determines the curvature between the constant-mobility and constant-velocity branches of the curve. The curve-fitting parameters are given in tabular form for the two n-channel and one p-channel systems studied. The dependence of the velocity-field curves on temperatures in the range 100–350K is also reported.     

Effects of radiative processing steps on inversion layer mobility and channel hot carrier damage in reoxidized nitrided oxide mosfets

The effects of x-ray irradiation and a subsequent low temperature anneal on the properties of reoxidized nitrided oxide (RNO) MOSFET's were examined. Irradiation was found to degrade conventional SiO₂ MOSFET lifetime under channel hot carrier stress far more strongly than RNO lifetime, particularly for p-channel devices. This is attributed to reduced bulk neutral electron trap generation in RNO. The inversion layer mobility of RNOn-MOSFET's (and, to a lesser degree,p-MOSFET's) was found toincrease after irradiation and anneal. 1/f noise measurements indicate that this change in mobility is due to a reduction in the density of near-interface electron traps.     

Deposition and characterization of Pb TiO3 thin films on silicon wafers using metalorganic sources

Ferroelectric PbTiO₃ thin films were deposited on bare silicon and Pt/SiO₂/Si substrates by metalorganic chemical vapor deposition in a temperature range from 270 to 550°C. The deposition of a single phase PbTiO₃ thin film did not occur on bare silicon substrates. Instead a double layer of lead-silicate and PbTiO₃ was formed owing to a serious diffusion of lead and oxygen ions into silicon substrates. But on Pt/SiO₂/Si substrates, a single phase PbTiO₃ oriented parallel to a-and c-axis was grown at a substrate temperature as low as 350°C even without a high temperature post-annealing. To get an optimal film, a precise control of input gas composition and also a deposition in a low temperature range from 350 to 400°C are necessary.     

Electron surface trapping effects on the switching voltage of metal-insulator (tunnel)-Si(n)-Si(p+) devices

Using double-delay pulse method for investigation of the dynamic characteristics of MIS switching devices, we have observed an abnormal dependence of the switching voltage on the pulse separation time in AuSiO₂ (tunnel)-Si(n)-Si(p⁺) diodes. This abnormal dependence may be attributed to the electron trapping and detrapping in the surface states at the SiSiO₂ interface. A simple model of the surface discrete traps is given and the calculation is in good agreement with experiment.     

The effect of oxide layer thickness on the quantification of 1.5 MeV γ–radiation induced interface traps in the Ag/SiO2/Si MOS devices

This work presents the effect of varied thickness of oxide layer and radiation dose on electrical characteristics of Ag/SiO₂/Si MOS devices irradiated by 1.5 MeV γ–radiations of varied doses. SiO₂ layers of 50, 100, 150 and 200 nm thickness were grown on Si substrates using dry oxidation and exposed to radiation doses of 1, 10 and 100 kGy. The exposure to radiation resulted in generation of fixed charge centers and interface traps in the SiO₂ and at the Si/SiO₂ interface. Capacitance-conductance-voltage (C-G-V) and capacitance-conductance-frequency (C-G-f) measurements were performed at room temperature for all MOS devices to quantify the active traps and their lifetimes. It is shown that accumulation and minimum capacitances decreased as the thickness of SiO₂ layer increased. For the unexposed MOS devices, the flat band voltage V_FB decreased at a rate of −0.12 V/nm, density of active traps increased by 4.5 times and depletion capacitance C_DP, increased by 2.5 times with the increase of oxide layer thickness from 50 to 200 nm. The density of active traps showed strong dependence on the frequency of the applied signal and the thickness of the oxide layer. The MOS device with 200 nm thick oxide layer irradiated with 100 kGy showed density of active interface traps was high at 50 kHz and was 3.6×10¹⁰ eV⁻¹ cm⁻². The relaxation time of the interface traps also increased with the exposure of γ–radiation and reached to 9.8 µs at 32 kHz in 200 nm thick oxide MOS device exposed with a dose of 100 kGy. It was inferred that this was due to formation of continuum energy states within the band gap and activation of these defects depended on the thickness of oxide layer, applied reverse bias and the working frequency. The present study highlighted the role of thickness of oxide layer in radiation hard environments and that only at high frequency, radiation induced traps remain passivated due to long relaxation times.