薄膜厚埋层SOI材料的新制备技术

在结合低剂量注氧隔离(SIMOX)技术和键合技术的基础上,研究了制备薄膜(薄顶层硅膜)厚埋层SOI材料的新技术--注氧键合技术.采用该新技术成功制备出薄膜厚埋层SOI材料,顶层硅厚度130nm,埋氧层厚度lμm,顶层硅厚度均匀性±2%.并分别采用原子力显微镜(AFM)和剖面透射电镜(XTEM)对其表面形貌和结构进行了表征.研究结果表明,SIMOX材料顶层硅通过键合技术转移后仍能够保持其厚度均匀性,且埋氧层和顶层硅之间具有原子级陡峭的分界面,因此注氧键合技术将会是一项有广阔应用前景的SOI制备技术.     

薄膜厚埋层SOI材料的新制备技术

在结合低剂量注氧隔离(SIMOX)技术和键合技术的基础上,研究了制备薄膜(薄顶层硅膜)厚埋层SOI材料的新技术--注氧键合技术.采用该新技术成功制备出薄膜厚埋层SOI材料,顶层硅厚度130nm,埋氧层厚度lμm,顶层硅厚度均匀性±2%.并分别采用原子力显微镜(AFM)和剖面透射电镜(XTEM)对其表面形貌和结构进行了表征.研究结果表明,SIMOX材料顶层硅通过键合技术转移后仍能够保持其厚度均匀性,且埋氧层和顶层硅之间具有原子级陡峭的分界面,因此注氧键合技术将会是一项有广阔应用前景的SOI制备技术.     

SIMOX薄膜材料的红外光谱特性和薄膜厚度的非破坏性测量方法

报道了 SOI材料薄膜厚度的非破坏性快速测量方法 ,详细地研究了 SIMOX材料的红外吸收光谱特性 ,求出了特征峰对应的吸收系数 .提出利用红外吸收光谱测量 SIMOX绝缘埋层厚度的非破坏性方法 ,并根据离子注入原理计算出表面硅层的厚度 .SIMOX薄膜的表层硅和绝缘埋层的厚度是 SOI电路设计时最重要的两个参数 ,提供的非破坏性测量方法 ,测量误差小于5% .在 SIMOX材料开发利用、批量生产中 ,用此方法可及时方便地检测 SIMOX薄膜的表层硅和绝缘埋层的厚度 ,随时调整注入能量和剂量     

SIMOX薄膜材料的红外光谱特性和薄膜厚度的非破坏性测量方法

报道了SOI材料薄膜厚度的非破坏性快速测量方法,详细地研究了SIMOx材料的红外吸收光谱特性,求出了特征峰对应的吸收系数.提出利用红外吸收光谱测量SIMOX绝缘埋层厚度的非破坏性方法,并根据离子注入原理计算出表面硅层的厚度.SIMOX薄膜的表层硅和绝缘埋层的厚度是SOI电路设计时最重要的两个参数,提供的非破坏性测量方法,测量误差小于5％.在SIMOX材料开发利用、批量生产中,用此方法可及时方便地检测SIMOX薄膜的表层硅和绝缘埋层的厚度,随时调整注入能量和剂量.     

屏蔽槽SOI高压器件新结构和耐压机理

提出具有屏蔽槽的SOI高压器件新结构和自适应界面电荷耐压模型.该结构在屏蔽槽内产生跟随漏极电压变化的界面电荷,此电荷使埋层介质的纵向电场增加,同时使顶层硅的纵向电场降低,并对表面电场进行调制,因此屏蔽了高电场对顶层硅的影响.借助二维器件仿真研究器件耐压和电场分布与结构参数的关系.结果表明,该结构使埋氧层的电场从传统的3Es升高到近600V/μm,突破了传统SOI器件埋氧层的耐压值,大大提高了SOI器件的击穿电压.     

屏蔽槽SOI高压器件新结构和耐压机理

提出具有屏蔽槽的SOI高压器件新结构和自适应界面电荷耐压模型.该结构在屏蔽槽内产生跟随漏极电压变化的界面电荷,此电荷使埋层介质的纵向电场增加,同时使顶层硅的纵向电场降低,并对表面电场进行调制,因此屏蔽了高电场对顶层硅的影响.借助二维器件仿真研究器件耐压和电场分布与结构参数的关系.结果表明,该结构使埋氧层的电场从传统的3Es升高到近600V/μm,突破了传统SOI器件埋氧层的耐压值,大大提高了SOI器件的击穿电压.     

SDB/SOI硅材料顶层硅膜均匀性控制研究

介绍了SDB/SOI(Silicon Direct Bonging/Silicon On Insulator)硅材料顶层硅膜均匀性的控制方法.顶层硅膜均匀性控制不好,会直接影响到IC或者其他元器件参数的一致性,造成器件成品率低,材料浪费大.因此,在制备SOI材料时,必须严格控制材料顶层硅厚度的均匀性和重复性.     

半导体材料

0205855低剂量 SIMOX 圆片线缺陷的针孔的研究[刊]/郑望//功能材料与器件学报.—2001.7(4).—431～433(C)用 Secco 法、Cu-plating 法分别表征了低剂量SIMOX 圆片顶层硅线缺陷、埋层的针孔密度。结果显示,低剂量 SIMOX 圆片的顶层硅缺陷密度低,但埋层质量稍差。通过注入工艺和退火过程的进一步优化,低剂量 SIMOX 将是一种有前途的 SOI 材料制备工艺。参7     

基于等效电容法对SOI器件自加热效应研究

针对目前常规SOI器件高温特性存在的问题,提出了采用等效电容法分析器件自加热效应的新观点,对抑制自加热效应原理进行了新的解析,根据埋层材料的介电常数不同,按等效电容法进行埋层厚度折算。在此基础上,提出了SOI器件的埋层新结构,并从介电常数的角度较好地验证了提出观点的正确性。最后得到,高介电常数等效埋层厚度的减小利于热泄散,高热导率的埋层材料提高了导热能力,在双重因素作用下有效抑制了自加热效应。     

氧离子和氮离子共注入硅形成SOI结构的俄歇能谱研究

本文中研究了O~+(200keV,1.8 ×10~(18)cm~(-2))和 N~+(180keV,4 ×10~(17)cm~(-2))共注入Si形成 SOI(Silicon on Insulator)结构的界面及埋层的微观结构.俄歇能谱(AES)和光电子能谱(XPS)的测量和研究结果表明:O~+和N~+共注入的SOI结构在经1200℃,2h退火后,O~+和N~+共注入所形成的绝缘埋层是由SiO_2相和不饱和氧化硅态组成;在氧化硅埋层的两侧形成氮氧化硅薄层;表面硅-埋层的界面和埋层-体硅的界面的化学结构无明显差异.这些结果与红外吸收和离子背散射谱的分析结果相一致.对这种SOI结构界面与埋层的形成特征进行了分析讨论。     

Fabrication and Characterization of 150-mm Silicon-on-Polycrystalline Silicon Carbide Substrates

Silicon-on-insulator (SOI) substrates can reduce radiofrequency (RF) substrate losses due to their buried oxide (BOX). On the other hand, the BOX causes problems since it acts as a thermal barrier. Oxide has low thermal conductivity and traps heat generated by devices on the SOI. This paper presents a hybrid substrate which uses a thin layer of polycrystalline silicon and polycrystalline silicon carbide (Si-on-poly-SiC) to replace the thermally unfavorable BOX and the silicon substrate. Substrates of 150 mm were fabricated by wafer bonding and shown to be stress and strain free. Various electronic devices and test structures were processed on the hybrid substrate as well as on a low-resistivity SOI reference wafer. The substrates were characterized electrically and thermally and compared with each other. Results showed that the Si-on-poly-SiC wafer had 2.5 times lower thermal resistance and exhibited equal or better electrical performance compared with the SOI reference wafer.     

Study of hybrid orientation structure wafer

Two types of 5μm thick hybrid orientation structure wafers,which were integrated by（110）or（100） orientation silicon wafers as the substrate,have been investigated for 15-40 V voltage ICs and MEMS sensor applications.They have been obtained mainly by SOI wafer bonding and a non-selective epitaxy technique,and have been presented in China for the first time.The thickness of BOX SiO₂ buried in wafer is 220 nm.It has been found that the quality of hybrid orientation structure with（100）wafer substrate is better than that with（110）wafer substrate by"Sirtl defect etching of HOSW".     

Back-gated buried oxide MOSFETs in a high-voltage bipolartechnology for bonded oxide/SOI interface characterization

A novel back-gated P-MOSFET structure is fabricated in a high-voltage complementary bipolar technology using BESOI (bonded etch back SOI) substrates. The P+ buried layer regions, used for the PNP BJT are used as the source and drain regions, the N- epi as the channel region, the silicon handle wafer as the gate, and the BOX (buried oxide) as the gate oxide. The P-MOSFET was used to characterize the interface between the BOX and the SOI. The devices exhibit high sub-threshold slope which is attributed to a high interface state density of about 2×10¹²/cm² at the bonding interface. Bias-temperature stress measurements show an effective mobile charge density of 4×10¹⁰/cm² in the buried oxide     

Hot-carrier degradation behavior of thin-film SOI nMOSFET withisolation scheme and buried oxide thickness

Hot-carrier degradation behavior of thin-film SOI (silicon-on-insulator) nMOSFETs with various isolation techniques and buried oxide (BOX) thickness has been investigated focused on the stress behavior in the SOI structure. LOCOS (local oxidation of silicon) and STI (shallow trench isolation) processes are used as isolation techniques. Buried oxide thickness is 100 and 400 nm, respectively. From the isolation point of view, STI-processed SOI devices have better hot-carrier immunity than LOCOS-isolated SOI devices. In terms of BOX thickness, the thick BOX case has better hot-carrier degradation characteristics than the thin one. It is found that STI process and thick BOX cases induce smaller stress than LOCOS process and thin BOX cases, resulting in better hot-carrier immunity     

Super-High Breakdown Voltage (>1200V) SOI LDMOS with A Buried P-type Layer and A Thin BOX

为探索在薄埋氧层SOI衬底上实现超高耐压LDMOS的途径,提出了一种具有P埋层（BPL）的薄埋氧层SOI LDMOS结构,耐压1200V以上。该BPL SOI LDMOS在传统SOI LDMOS的埋氧层和N型漂移区之间引入了一个P型埋层。当器件正向截止时,N型漂移区与P埋层之间的反偏PN结将承担器件的绝大部分纵向压降。采用2维数值仿真工具Silvaco TCAD对BPL SOI LDMOS进行虚拟制造和器件仿真,结果表明该结构采用适当的参数既能实现1280V的耐压,将BOX层减薄到几百纳米以下又可以改善其热特性。     

Nanoscale FD/SOI CMOS: thick or thin BOX?

The question of buried-oxide (BOX) thickness scaling for nanoscale fully depleted (FD) silicon-on-insulator (SOI) CMOS is addressed via insightful quantitative and qualitative analyses. Whereas, FD/SOI MOSFETs with thin BOX give better control of short-channel effects (SCEs), they complicate the material and/or process technologies and undermine CMOS speed. We show that the improved SCE control afforded by thin BOX is due to high transverse electric field in the body defined by the device asymmetry, and not only to the suppression of electric-field fringing in the BOX as is commonly presumed. Since conventional FD/SOI CMOS with thick BOX can be scaled via ultrathin bodies, we conclude that thin BOX is not needed nor desirable.     

Comparison of GaAs grown on standard Si (511) and compliant SOI (511)

Gallium arsenide (GaAs) films were grown by molecular beam epitaxy (MBE) on a (511) silicon substrate and a compliant (511) silicon-on-insulator (SOI) substrate. The top silicon layer of the compliant (511) SOI was thinned to ～1000 Å. The five inch diameter SOI wafer was created by wafer bonding. The GaAs (004) x-ray diffraction (XRD) reflection showed a 25% reduction in the full width half maximum (FWHM) for GaAs on a compliant (511) SOI as compared to GaAs on a silicon substrate. Cross section transmission electron microscopy (XTEM) clearly indicates a different dislocation structure for the two substrates. The threading dislocation density is reduced by at least an order of magnitude in the compliant (511) SOI as compared to the (511) silicon. XTEM found dislocations and damage was generated in the top silicon layer of the compliant SOI substrate after GaAs growth.     

具有T型电荷补偿区的横向超结SOILDMOS

非平衡超结器件的电荷补偿能力在薄层SOI器件中受到限制,文中提出一种具有T型电荷补偿区的器件结构。通过漏端刻蚀的PSOI结构使硅衬底与埋氧层同时参与纵向耐压,可以提高非平衡超结n区的电荷补偿能力;在埋氧层刻蚀区增加垂直的n型补偿区,弥补埋氧层的缺失。由横向的非平衡超结n区和漏端垂直的n区共同构成T型补偿区,可以有效缓解薄层SOI超结器件中的衬底辅助耗尽效应,优化横向电场,提高器件的耐压。器件的制作可以通过改进传统的PSOI工艺实现,应用于SOI功率集成电路。三维器件仿真结果表明,新结构下的器件耐压达到290V,相对于常规的SOI超结器件和非平衡超结器件提高了267%和164%。     

Three-interface pseudo-MOSFET models for the characterization of SOI wafers with ultrathin film and BOX

The electrical characterization of unprocessed fully depleted silicon-on-insulator (SOI) layers relies on the pseudo-MOSFET (Ψ-MOSFET) technique. We propose three-interface models which are more appropriate for addressing the case of SOI wafers with ultrathin body and BOX (UTB²). The novel models for threshold voltage and subthreshold swing account for the channel-to-surface and channel-to-substrate coupling which are important effects, respectively, in ultrathin films and thin BOX. The influence of the density of traps at each of the three interfaces (free surface, channel/BOX and BOX/substrate) is discussed. The models are validated with experimental results from a range of SOI film thicknesses.     

A new integrated SOI power device based on self-isolation technology

A new SOI LDMOS structure with buried n-islands(BNIs) on the top interface of the buried oxide(BOX) is presented in a p-SOI high voltage integrated circuits(p-SOI HVICs),which exhibits good self-isolation performance between the power device and low-voltage control circuits.Furthermore,both the donor ions of BNIs and holes collected between depleted n-islands not only enhance the electric field in BOX from 32 to 113 V/μm,but also modulate the lateral electric field distribution,resulting in an improvemen...