Underfill selection methodology for fine pitch Cu/low-k FCBGA packages

A systematic underfill selection approach has been presented to characterize and identify suitable underfill encapsulants for large size flip chip ball grid array (FCBGA) packages. In the selection scheme, a total of six evaluation factors such as fracture toughness, coefficient of moisture expansion, flowability, delamination performance and filler settlement were considered. Driving stresses for package failure were also included as a factor of consideration, which clearly depends on the package size and geometry. Based on the approach adopted, underfill material that is suitable for 35 × 35 mm² packages with 15 mm die size and 45 × 45 mm² packages with 21 mm die size was selected. Target value for underfill properties has also been revised.     

Measurement and Simulation of Stacked Die Thermal Resistances

Packages with multiple dies provide additional challenges when documenting their thermal performance. One style of multiple dies packages stacks the die on top of each other with a die attach adhesive. This paper explores the thermal performance of such packages in a wire bond plastic ball grid array package with three different die configurations. The thermal performance of the package was determined using the JEDEC JESD51 specifications. Since there were three different effective die sizes, the data allowed a better validation of the finite element thermal simulation techniques than can be obtained with only a single die size. Die size is usually the most important predictor of plastic ball grid array thermal performance. In this case, packages built with the same materials and substrate had a Theta-JA (2s2p board, natural convection) that differed by 100% as a result of a change in effective die size. With a validated simulation method, additional power distributions were simulated and compared to results obtained by superposition techniques.      

Accurate RF electrical characterization of CSPs using MCM-D thin film technology

The thin film multilayer multichip module-deposited (MCM-D) technology of IMEC is used for characterising the RF electrical performance of two types of chip scale packages (CSPs). The measurement technique called MCM-on-package-on-MCM (MoPoM) enables accurate measurements and de-embedding in the gigahertz (GHz) range of frequencies. Wafer processing of the MCM-D technology allows for several design structures to be integrated on a single mask. The packages chosen are a 120-pin plastic ball grid array (PBGA) and an 80-pin polymer stud grid array (PSGA). Lumped element models extracted from measurements and three-dimensional simulations show good agreement with the measurements up to 6 GHz for the BGA and the PSGA. The electrical performance of the packages is compared at 1.8 GHz (GSM), 2.4 GHz (Bluetooth), and 5.2 GHz (HiperLAN) and at 5.2 GHz both the packages exhibit a return loss of lower than -10 dB and hence cannot be used in most cases without design improvement. We also show that the influence of encapsulant is significant while transmission line detuning due to the package is not significant at microwave frequencies. We also briefly mention about the crosstalk effects. We demonstrate the significant degradation in the performance of a 5.2 GHz MCM-D low noise amplifier (LNA) after packaging. A significant improvement in package performance is observed by conjugate matching the package interconnects.     

Cost-effective chip-on-heat sink leadframe package for 800-Mb/s/lead applications

Chip-on-heat sink leadframe (COHS-LF) packages offer a simple, low-cost chip encapsulation structure with advanced electrical and thermal performance for high-speed integrated circuit applications. The COHS-LF package is a novel solution to the problems of increased power consumption and signal bandwidth demands that result from high-speed data transmission rates. Not only does it offer high thermal and electrical performance, but also provides a low-cost short time-to-market package solution for high-speed applications. In general, there are two main memory packages employed by the most popular high-speed applications, double data rate (DDR) SDRAM. One is the cheaper, higher parasitic leadframe packages, such as the thin small outline packages (TSOPs), and the other is the more expensive, lower parasitic substrate-based packages, such as the ball grid array (BGA). Due to the requirement for higher ambient temperature and operating frequency for high-speed devices, DDR2 SDRAM packages were switched from conventional TSOPs to more expensive chip-scale packages (i.e., BGA) with lower parasitic effects. And yet, by using an exposed heat sink pasted on the surface of the chip and packed in a conventional leadframe package, the COHS-LF is a simpler, lower cost design. Results of a three-dimensional full-wave electromagnetic field solver and SPICE simulator tests show that the COHS-LF package achieves less signal loss, propagation delay, edge rate degradation, and crosstalk than the BGA package. Furthermore, transient analysis using the wideband T-3/spl pi/ models optimized up to 5.6 GHz for signal speeds as high as 800 Mb/s/lead demonstrates the accuracy of the equivalent circuit model and reconfirms the superior electrical characteristics of COHS-LF package.     

Mechanical cycling fatigue of PBGA package interconnects

Increased packaging density in micro-electronic products has advantaged attach of BGA, micro-BGA, CSP, and DCA packages. These area array packages are assembled to circuit boards that are reduced in size and thickness, by necessity. These assemblies would include flexible thin laminate circuit boards with area array components attached by solder balls. In normal use, these assemblies would be subjected to numerous ultra-low frequency mechanical deflections; consider a keypad when the user enters telephone numbers. Most of the reliability studies of area array packages have dealt with temperature cycling induced fatigue. However, less attention has been paid to mechanical bending fatigue of these packages.A test method has been developed to elucidate the mechanical bending fatigue issues of BGA, micro-BGA, CSP, and DCA packages attached to printed circuit boards. Appropriate bending fatigue reliability models and their theoretical basis are being developed. The test method and preliminary mechanical cyclic fatigue data on a PBGA package will be presented as a function of printed circuit board thickness. Consideration will be given to fatigue fracture morphology and its relation to solder joint location and rate of crack growth.     

Modeling of lead-frame plastic CSPs for accurate prediction oftheir low-pass filter effects on RFICs

This paper presents a direct extraction method to construct the electrical models of lead-frame plastic chip scale packages for RF integrated circuits (RFICs) from the measured S-parameters. To evaluate the package effects on the reciprocal passive components, the insertion and return losses for an on-chip 50-Ω microstrip line housed in a 32-pin bump chip carrier (BCC) package were analyzed based on the established package model. Excellent agreement with measurement has been found up to 15 GHz. When applied to the nonreciprocal active components, the gain variations for a heterojunction-bipolar-transistor array housed in an 8-pin BCC package have also been successfully predicted up to 22 GHz. Both cases have demonstrated that the package acts as a low-pass filter to cause a sharp cutoff for the RFIC components above a certain frequency     

全铜通孔柔性LED封装热学性能仿真分析

柔性基板封装(COF)是一种新型LED封装形式。本研究在柔性基板中的高分子绝缘层(PI)中添加全铜通孔,通过有限元仿真分析全铜通孔对LED封装热学性能的影响。研究结果表明：在柔性LED封装中,PI层热阻最大,是导致芯片结温高的主要因素。PI层中全铜通孔的添加使PI层热阻大幅降低,显著提升LED封装的垂直散热能力。基于仿真计算结果,建立了PI层中添加全铜通孔数量与LED封装热阻间的对应关系。针对本研究中的封装结构,采用8*8 的全铜通孔阵列对LED封装的热学性能提升效果显著。     

Known good die meets chip size package

The increasing density, functionality, and high speed performance of integrated circuit components are fueling demands for smaller and faster portable electronic systems. Designers are becoming more experienced at cutting size, delays, and costs wherever possible. One area that offers attractive benefits for reducing size and improving performance is in the IC package itself, either eliminating it altogether, or reducing the size to the point where it takes up very little more space than the IC. In that context, chip size packages (CSPs) offer a viable solution to the problem. The electrical performance of a circuit is degraded by any capacitance, inductance, and lead length added to the IC bond pads. In addition to the performance limitations of the IC package itself, the larger footprint of the package implies that the next level of interconnect will also be sub optimal due to size and fanout of the IC interconnections. CSPs address these problems, too     

Thermal analysis of a flip chip ceramic ball grid array (CBGA) package

The function of an electronic cooling package is to dissipate heat to ensure proper operation and reliability. The flip chip ball grid array package is probably the most suitable package for high-level thermal performance applications. A high thermal performance flip chip ceramic ball grid array (FC-CBGA) package with an aluminum silicon carbide (AlSiC) lid and one without lid were evaluated using the computational fluid dynamics (CFD) technique. This paper compares the thermal performance of a 35 × 35 mm FC-CBGA package with three different die sizes of 5 × 5 mm, 15 × 15 mm and 20 × 20 mm. The performance of a lid fitted with different heat sinks was investigated in standard JEDEC defined natural and in forced convection environments. Thermal measurements were performed using a functional application specific integrated circuit (ASIC) chip, in compliance with the JEDEC standards. Excellent agreement was found between the numerical results and the measured data. Improved thermal performance was observed with a lidded package as compared to the unlidded one. However, no significant improvement was observed between lidded and unlidded packages when fitted with a heat sink subjected to forced convection. This paper also discusses the package thermal budget estimate with and without heat sinks. Printed circuit board and package top surface temperature patterns were measured using an infrared thermal camera. The usefulness of the thermal characterization parameter is demonstrated in system level applications. Parametric studies were carried out to understand the effect of die size, radiation effect, gird size variations and airflow rate on die junction temperature and package thermal resistance. This study also incorporates the effects of substrate, lid, die and PCB temperatures for different die sizes in natural and forced convection environments.     

BGA器件及其常见的形式

BGA器件不仅能够满足现在已有的其它组件所不能够提供的高性能、大量I/O数量的应用要求,也给如今的有引脚元器件提供了一种可靠的可替换方案。对于在组件体的底部位置安置有大量焊球阵列的BGA器件来说有四种主要的类型。表面阵列配置的组装技术将会成为电子组装业最主要的发展潮流。     

Wafer-level chip scale packaging: benefits for integrated passivedevices

Chip scale packaging continues to draw attention for applications that require high performance or small form factor solutions. The term chip scale package (CSP) has become synonymous with “fine pitch BGA” as the distinction between a ball grid array (EGA) and some chip scale packages becomes nearly indistinguishable. The cost of chip scale packages also continues to draw attention as one of the barriers to wide scale industry adoption. Sometimes lost in the chip scale debate is the discussion about wafer level chip scale packages, which offer the fastest path to small form factor, high performance and cost effective solutions. In this paper, we describe an approach to wafer level chip scale packaging that is an extension of integrated passive device processing, which results in low cost     

Thermal design of a broadband communication system with detailed modeling of TBGA packages

This paper presents a thermal modeling of a broadband network communication box partitioned into two stacked modules. A printed circuit board (PCB) is inside each module where an array of 16 tape ball grid array (TBGA) packages is surface mounted to the PCB. The TBGA package dissipates 6 W power each. In addition, 12 W of power is dissipated from four plastic ball grid array (PBGA) packages on the PCB. Pin-fin heat sinks are attached to the TBGA packages using silica-filled epoxy to enhance heat dissipation. Pin-fin heat sinks are also attached to the PBGA packages. Two exhaust fans are mounted at the flow exit to draw ambient air into the system at approximately 200 linear feet per minute (LFM) of velocity. The full Navier–Stokes equations for airflow are solved to simulate the forced convection cooling in the electronic module. Buoyancy effect was considered in the numerical model by incorporating Boussinesq-approximation. The TBGA packages are modeled in detail in order to obtain the package junction temperatures for system reliability evaluation and thermal design optimization. Detailed models of the attached pin-fin heat sinks and the epoxy interfaces are also utilized in this study. Compact heat sink model composed of a base plate and a resistance fluid volume is applied to model heat dissipation from the heat sinks attached to the four PBGA packages. System fan curve is used to simulate the fan operating conditions. The effect of changing system thermal design on the TBGA package junction temperatures as well as the hydraulic operating conditions of the system fans are examined and reported herein. The effect of radiation heat transfer is also examined. The importance of detailed modeling of the high power TBGA packages is demonstrated in this study. Simulation results were compared with JEDEC thermal test data under similar conditions of airflow.     

方形扁平无引线QFN封装的研究及展望

方形扁平无引线(QFN)封装是方形扁平封装(QFP)和球栅阵列(BGA)封装相结合发展起来的先进封装形式,是SMT技术中产品体积进一步小型化的换代产品.讨论了QFN技术的改进及工艺自动化发展进程,指出其必将成为半导体器件高端主流封装形式之一.     

Drop impact reliability analysis of CSP packages at board and product levels through modeling approaches

Chip scale package (CSP) and fine pitch ball grid array (BGA) packages have been increasingly used in portable electronic products such as mobile cell phones and PDA, etc. Drop impact which is inevitable during its usage could cause not only housing crack but also package to board interconnect failure, such as BGA solder breaks. Various drop tests have been used to ensure high reliability performance of packaging to withstand such impact and shock load. Due to extreme difficulty in directly measuring responses in solder joint during drop shock event, computer simulation based modeling approach has been increasingly played an important role in evaluating product reliability performance during product development. An advanced modeling technique with a comprehensive failure criterion including high strain rate effect needs to be developed to quantitatively evaluate package reliability performance especially in cross comparisons between different board and system level designs. In this paper, three drop tests have been modeled, namely, bare board drop, board with fixture drop or shock, and system level phone drop. Submodeling and explicit-implicit sequential modeling techniques are used to characterize the dynamic responses of CSP/BGA packages in different board designs. Failure criteria and effects of strain rate and edge support on BGA in multicomponent boards are also investigated. A validation test with data acquisition is used to correlate the test results with numerical results.     

Accurate measurement of ground-ring inductance in ball grid arraypackage

A new technique has been developed to measure the ground-ring inductance in a ball grid array (BGA) package. A simple parallel LC circuit is used to model the ground-ring parasitics at frequencies up to 1 GHz. After connecting an SMA connector to the ground ring of the BGA package, a network analyser can be used to measure the reflection coefficient (S₁₁) up to 1 GHz from which the ground-ring inductance can be extracted. It has been found that the ground-ring inductance depends very strongly on the phase of S₁₁. This leads to the advantage of excellent accuracy for the extracted quantities. The experimental ground-ring inductance data for a variety of BGA packages are verified by Ansoft simulation results     

An X-band small outline leaded plastic package for MMIC applications

A new small outline (SO) leaded plastic package has been developed that improves return loss, insertion loss, and isolation performance over that of a shrink small outline package (SSOP) in the same body size. A custom TRL calibration kit was developed, and prototype packages built and measured. The measured package showed an increase in the application bandwidth of SO-type packages from 5 GHz to over 8 GHz. Further investigations using full-wave electromagnetic simulations reveal a potential increase in return loss of better than 30 dB to 10 GHz, giving the package a usable bandwidth well into the X-band (8-12GHz). Applications for the new package are in microwave and RFIC applications.     

WLCSP封装技术中的集成无源器件

芯片规模封装技术一直倍受高性能、小形状因素解决方案在各类应用中的关注。芯片规模封装与球栅阵列(BGA)封装之间的区别变得不可分辨,已成为“细间距BGA”的同义词。芯片规模封装成本也是业界关注的焦点之一。芯片规模晶圆级封装是提供小形状、高性能和低成本的最快途径。论述了集成无源器件加工、低成本化的晶圆级芯片规模封装技术。     

Thermal performance impacts of heat spreading lids on flip chip packages: With and without heat sinks

Heat spreading lids on a flip chip package can provide many thermal and mechanical advantages. Major drawbacks are higher module costs and potentially poorer thermal performance with a heat sink. This study compares thermal performance of direct lid attach (DLA) and bare die flip chip packages and addresses the roles of interface resistance and lid thickness. The IBM SLC^TM package is tested and modeled. JEDEC standard wind tunnel tests as well as CFD models are used for analysis. The study reveals that the DLA design without additional heat sinking can provide significantly better thermal performance compared to the bare die package, depending on package size and airflow rate. With a heat sink the performance of the lidded package can be superior or inferior depending on interface resistance, lid design and the standard used for comparison.     

QFN封装元件组装工艺技术的研究

QFN(Quad Flat No-lead Package,方形扁平无引脚封装)是一种焊盘尺寸小、体积小、 以塑料作为密封材料的新兴表面贴装芯片封装技术。由于底部中央大暴露焊盘被焊接到PCB的散热焊 盘上,这使得QFN具有极佳的电和热性能。QFN封装尺寸较小,有许多专门的焊接注意事项。文章 介绍了QFN的特点、分类、工艺要点和返修。     

QFN封装元件组装工艺技术研究

QFN是一种焊盘尺寸小、体积小、以塑料作为密封材料的新兴的表面贴装芯片封装技术。由于底部中央的大暴露焊盘被焊接到PCB的散热焊盘上,这使得QFN具有极佳的电和热性能。QFN封装尺寸较小,有许多专门的焊接注意事项。介绍了QFN的特点、分类、工艺要点和返修。