DSP-Based Implementation of an LQR With Integral Action for a Three-Phase Three-Wire Shunt Active Power Filter

This paper presents the design and implementation of a Linear Quadratic Regulator (LQR) with Integral action (LQRI) for a three-phase three-wire shunt active filter (SAF). The integral action is added so as to cancel the steady-state errors for reference tracking or disturbance rejection, knowing that the standard LQR provides only proportional gains. The controller is designed to achieve dc bus voltage regulation and harmonics and reactive power compensation. The converter model is set in the $d{-}q$ rotating reference frame. The latter is augmented with the integral of the $q$ component of the SAF currents and dc bus voltage to achieve integral action. The controller's performance depends on the weighting matrix, which is chosen to ensure satisfactory response. The converter is controlled as a whole, i.e., a multi-input–multioutput system and a fixed pulsewidth modulation at 10 kHz is used to generate the gating signals of the power devices. The system is tested for harmonics, reactive power, and load unbalance compensation for balanced/unbalanced loads. The experimental results obtained with a digital signal processor-based implementation of the controller on the DS1104 of dSPACE show good performance in terms of dc bus voltage regulation (small overshoot and very fast time response) and a low total harmonic distortion of ac line currents.      

Regulated Switched-Capacitor Doubler With Interleaving Control for Continuous Output Regulation

A dual-branch 1.8 V to 3.3 V regulated switched-capacitor voltage doubler with an embedded low dropout regulator is presented. For the power stage, the power switches are individually controlled by their phase signals using a phase-delayed gate drive scheme, and are turned on and off in proper sequence to eliminate both short-circuit and reversion currents during phase transitions. For the regulator, the two branches operate in an interleaving fashion to achieve continuous output regulation with small output ripple voltage. Dual-loop feedback capacitor multiplier is adopted for loop compensation and a P-switch super source follower with high current sinking capability is inserted to drive switching capacitive load, and push the pole at the gate of the output power transistor to high frequency for better stability. The regulated doubler has been fabricated in a 0.35 $mu{hbox {m}}$ CMOS process. It operates at a switching frequency of 500 kHz with an output capacitor of 2 $muhbox{F}$ , and the maximum output voltage ripple is only 10 mV for a load current that ranges from 10 mA to 180 mA. The load regulation is 0.0043%/mA, and the load transient is 7.5 $mu{hbox {s}}$ for a load change of 160 mA to 10 mA, and 25 $mu{hbox {s}}$ for a load change of 10 mA to 160 mA.      

Tunable Linear MOS Resistors Using Quasi-Floating-Gate Techniques

A family of tunable MOS resistors based on quasi-floating-gate (QFG) transistors biased in the triode region is analyzed in this paper. From the study results, a new device that outperforms previous implementations, is presented. By means of a capacitive divider, the ac component of the drain-to-source voltage scaled with a factor $alphaleq 1$ is added to the gate-to-source voltage leading to a cancellation of the nonlinear terms. The effect of $alpha$ on resistor linearity is analytically studied. Simulation results are also provided for different technologies. Finally, a complete transconductor has been built which preserves the linearity of the MOS resistor. Three versions of the transconductor have been fabricated for different values of $alpha$ ($alpha=$ 0, 0.5, and 1) in a 0.5 $mu{hbox {m}}$ CMOS technology with $pm$1.65-V supply voltage. Experimental results show (for $alpha=1$ ) a THD of $-$ 57 dB $({rm HD}2=-70 {hbox {dB}})$ at 1 MHz for 2-V peak-to-peak differential input signal with a nominal ac-transconductance of 200 $muhbox{A/V}$ and a power consumption of 3.2 mW.      

Single-Stage Soft-Switching AC–DC Converter With Input-Current Shaping for Universal Line Applications

In this paper, a novel single-stage soft-switching ac–dc converter for universal line applications is presented. Unlike the conventional single-stage designs, the proposed input-current shaping scheme is intentionally arranged to be charged in the duty-off time. With this design, the switch current stress in the duty-on time is significantly reduced. Meanwhile, this design produces ac modulation effect on the charging time of the boost inductor so that the input $i{-}nu$ curve drawn by the proposed converter has nearly linear relationship. Moreover, an active-clamp flyback–forward topology is used as the downstream dc–dc cell to alleviate voltage stress across the bulk capacitor. By deactivating the flyback subconverter and keeping the forward subconverter supplying the output power at light-load condition, the bulk-capacitor voltage can be alleviated effectively and guaranteed below 450 V in wide ranges of output load and line input (90–265 $hbox{V}_{rm rms}$). Experimental results, obtained from a prototype circuit with 20-V/100-W output, have verified that three achievements can be obtained simultaneously, including the compliance with the line-current harmonic regulations, the reliable alleviation of the bulk-capacitor voltage stress, and the substantially promoted conversion efficiency.      

A 67 dBm $OIP_{3}$ Multistacked Junction Varactor

A multistacked varactor is presented for ultra-linear tunable radio frequency applications. The varactor elements are applied in anti-series configuration and are characterized by an “exponential” $C$- $V _{R}$ relationship. Third-order intermodulation ($IM_{3}$) is cancelled through proper harmonic loading of the terminals of the anti-series configuration. Multiple stacking is used to further increase the power handling and to minimize the remaining fifth-order distortion. The measured output intercept point ($OIP_{3}$ ) at 2 GHz is $ > 67~{rm dBm}$ for modulated signals up to 10 MHz bandwidth, while providing a capacitance tuning ratio of 3:1 with an average quality factor of 40 and maximum control voltage of 10 V.      

Fundamental Frequency Switching Strategies of a Seven-Level Hybrid Cascaded H-Bridge Multilevel Inverter

This paper presents a cascaded H-bridge multilevel inverter that can be implemented using only a single dc power source and capacitors. Standard cascaded multilevel inverters require $n$ dc sources for 2$n + hbox{1}$ levels. Without requiring transformers, the scheme proposed here allows the use of a single dc power source (e.g., a battery or a fuel cell stack) with the remaining $n-1$ dc sources being capacitors, which is referred to as hybrid cascaded H-bridge multilevel inverter (HCMLI) in this paper. It is shown that the inverter can simultaneously maintain the dc voltage level of the capacitors and choose a fundamental frequency switching pattern to produce a nearly sinusoidal output. HCMLI using only a single dc source for each phase is promising for high-power motor drive applications as it significantly decreases the number of required dc power supplies, provides high-quality output power due to its high number of output levels, and results in high conversion efficiency and low thermal stress as it uses a fundamental frequency switching scheme. This paper mainly discusses control of seven-level HCMLI with fundamental frequency switching control and how its modulation index range can be extended using triplen harmonic compensation.      

Decoupled Current Control of Sensorless Induction-Motor Drives by Integral Sliding Mode

This paper discusses the problems of current decoupling control and controller tuning associated with sensorless vector-controlled induction-motor (IM) drives. In field-oriented control, the $d$–$q$ synchronous-frame currents should be regulated to have independent dynamics such that the torque production of the IM resembles that of a separately excited dc motor. However, these currents are not naturally decoupled, and decoupling compensators should be used. Current loop tuning is an additional problem, since controller gains obtained by theoretical methods or simulation, quite often, do not work well on the real system. This paper proposes a new approach for current control that uses integral-sliding-mode (ISM) controllers to achieve decoupling. The synchronous-frame control voltages are synthesized as the sum of two controller outputs: a traditional one (PI) that acts on an ideal plant model and an ISM controller. The ISM controller decouples the $d$–$q$ currents and compensates the parameter variations in the current loops of the machine. Simulations and experimental tests on a 0.25-hp three-phase induction machine show satisfactory results.      

HID Lamp Electronic Ballast With Reduced Component Number

A reduced-component-number single-stage power-processing electronic ballast to drive high-intensity discharge lamps is presented in this paper. A dc–dc buck converter, which controls the current and the power of the lamp, a power factor preregulator based on a discontinuous conduction mode boost converter, and the inverter are combined in a boost integrated with buck rectifier/energy storage/dc–dc converter. It operates with a line-frequency square-wave current driving the lamp. The signals of the power stages are provided by a dedicated microcontroller. Ballast for sodium vapor lamps of 70 W without acoustic resonance was implemented, resulting in a $pf = 0.97$ with 22% total harmonic distortion and $eta = 84%$.      

Pulsed $I_{d}$– $V_{g}$ Methodology and Its Application to Electron-Trapping Characterization and Defect Density Profiling

The pulsed current–voltage ($I$– $V$) measurement technique with pulse times ranging from $sim$17 ns to $sim$ 6 ms was employed to study the effect of fast transient charging on the threshold voltage shift $Delta V_{t}$ of MOSFETs. The extracted $Delta V_{t}$ values are found to be strongly dependent on the band bending of the dielectric stack defined by the high-$kappa$ and interfacial layer dielectric constants and thicknesses, as well as applied voltages. Various hafnium-based gate stacks were found to exhibit a similar trap density profile.      

A 300 nW, 15 ppm/$^{circ}$C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs

A low-power CMOS voltage reference was developed using a 0.35 $mu$m standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, which was about 745$~$mV for the MOSFETs we used. The temperature coefficient of the voltage was 7 ppm/ $^{circ}$C at best and 15 ppm/$^{circ}$C on average, in a range from ${-}$ 20 to 80$^{circ}$ C. The line sensitivity was 20 ppm/V in a supply voltage range of 1.4–3 V, and the power supply rejection ratio (PSRR) was ${-}$45 dB at 100 Hz. The power dissipation was 0.3 $mu$W at 80$^{circ}$C. The chip area was 0.05 mm$^2$ . Our device would be suitable for use in subthreshold-operated, power-aware LSIs.      

Gain-Enhancement Techniques for CMOS Folded Cascode LNAs at Low-Voltage Operations

In this paper, gain-enhancement techniques suitable for folded cascode low-noise amplifiers (LNAs) at low-voltage operations are presented. By employing a forward bias and a capacitive divider at the body of the MOSFETs, the LNA circuit can operate at a reduced supply voltage while maintaining an enhanced gain due to suppression of the negative impact of the body transconductance. In addition, a $G_{m}$-boosting stage is introduced to further increase the LNA gain at the cost of circuit linearity. Using a standard 0.18-$mu{hbox {m}}$ CMOS process, two folded cascode LNAs are demonstrated at the 5-GHz band based on the proposed topologies. Consuming a dc power of 1.08 mW from a 0.6-V supply voltage, the LNA with the forward-body-bias technique demonstrates a gain of 10.0 dB and a noise figure of 3.37 dB. The measured $P_{{rm in}-1 {rm {dB}}}$ and ${rm IIP}_{3}$ are $-$18 and $-$ 8.6 dBm, respectively. For the LNA with a $G_{m}$-boosting feedback, a remarkable gain of 14.1 dB gain is achieved with a dc power of 1.68 mW.      

Designing an Adjustable Wide Range Regulated Current Source

LLC resonant converter has been used widely as dc–dc converter for achieving constant dc voltage. In this paper, an LLC resonant converter, by adding an inductance to its conventional topology and considering the rectifying stage stray inductances, is proposed for an adjustable wide range regulated current source (20–200 ${rm A}_{rm dc}$) for using as ion implanter's filament power supply. The additional inductor increases output current adjustment range and efficiency, especially at light loads. Transformer's leakage inductances and rectifying stage stray inductances have been considered. Because of these inductances, the rectifier stage always works in continuous conduction mode, and its conduction angle is forced to be larger than $pi$, and peak current of the rectifier stage and the output capacitor have been reduced effectively. Switching losses and electromagnetic interference noises have been reduced as well due to zero-voltage switching at the primary and secondary sides of the converter, and zero-current switching at its secondary side. Soft switching is achieved for all power devices under all operating conditions. A developed prototype of the converter has been tested under different load (2.5–12.5 m$Omega$) and input voltage conditions (320–370 $V_{rm dc}$) with maximum efficiency of 87%. Experimental results confirm high performance of the designed adjustable and regulated current source even under the worst-case conditions.      

$hbox{TiN/ZrO}_{2}$/Ti/Al Metal–Insulator–Metal Capacitors With Subnanometer CET Using ALD-Deposited $hbox{ZrO}_{2}$ for DRAM Applications

We provide the first report of the structural and electrical properties of $hbox{TiN/ZrO}_{2}$/Ti/Al metal–insulator–metal capacitor structures, where the $hbox{ZrO}_{2}$ thin film (7–8 nm) is deposited by ALD using the new zirconium precursor ZrD-04, also known as Bis(methylcyclopentadienyl) methoxymethyl. Measured capacitance–voltage ($C$– $V$) and current–voltage ( $I$–$V$) characteristics are reported for premetallization rapid thermal annealing (RTP) in $hbox{N}_{2}$ for 60 s at 400 $^{circ}hbox{C}$, 500 $^{circ}hbox{C}$, or 600 $^{ circ}hbox{C}$. For the RTP at 400 $^{circ}hbox{C}$ , we find very low leakage current densities on the order of nanoamperes per square centimeter at a gate voltage of 1 V and low capacitance equivalent thickness values of $sim$ 0.9 nm at a gate voltage of 0 V. The dielectric constant of $ hbox{ZrO}_{2}$ is 31 $pm$ 2 after RTP treatment at 400 $^{circ}hbox{C}$.      

Fabrication and Characterization of High-Current-Gain 4H-SiC Bipolar Junction Transistors

This paper reports on newly developed high-performance 4H-SiC bipolar junction transistors (BJT) with improved current gain and power handling capabilities based on an intentionally designed continuously grown 4H-SiC BJT wafer. The measured dc common-emitter current gain is as high as 70, the specific on -state resistance $(R_{{rm SP}hbox{-}{rm ON}})$ is as low as 3.0 $hbox{m}Omegacdothbox{cm}^{2}$, and the open-base breakdown voltage $(V_{rm CEO})$ reaches 1750 V. Large-area 4H-SiC BJTs with a footprint of 4.1 $times$ 4.1 mm have been successfully packaged into a high-gain $(beta = hbox{50.8})$ high-power (80 A $times$ 700 V) all-SiC copack and evaluated at high temperature up to 250 $^{circ}hbox{C}$. Small 4H-SiC BJTs have been stress tested under a continuous collector current density of 100 $hbox{A}/hbox{cm}^{2}$ for 24 h and, for the first time, have shown no obvious forward voltage drift and no current gain degradation. Numerical simulations and experimental results have confirmed that simultaneous high current gain and high open-base breakdown voltage could be achieved in 4H-SiC BJTs.      

A Long-Range UHF-Band Passive RFID Tag IC Based on High- $Q$ Design Approach

We present a fully integrated long-range UHF-band passive radio-frequency-identification tag chip fabricated in 0.35-$muhbox{m}$ CMOS using titanium (Ti/Al/Ta/Al)–silicon Schottky diodes. The diodes showed low turn-on voltages of 95 and 140 mV for diode currents of 1 and 5 $muhbox{A}$, respectively. In addition, the Schottky diodes exhibited low-resistive loss, and a high-$Q$ -factor design approach was exploited to achieve a long read range for the tag integrated circuit (IC). An optimized voltage multiplier resulted in an excellent sensitivity of $-$ 14.8 dBm and corresponding power-conversion efficiency of 36.2% for generating an output voltage of 1.5 V at 900 MHz. The range analysis of the measured multiplier performance indicated an operating range of more than 9 m at 4-W Effective Isotropically Radiated Power reader power. The subthreshold-mode operation of an ASK demodulator allowed ultralow power operation. Under power consumption as low as 27 nW, the demodulator supported a data rate of 150 kb/s and a modulation depth of 40%. A new architecture for generating a stable system clock (2.2 MHz) for the tag IC was employed to deal with supply voltage and temperature variations. Measurements showed that the clock generator had an error of 0.91% from the center frequency owing to an 8-b digital calibration scheme.      

A Slew Controlled LVDS Output Driver Circuit in 0.18 $mu$m CMOS Technology

This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power pre-driver stage. A slew control technique has also been introduced to reduce the impedance mismatch effect between the output driver circuit and the line. The pre-driver stage shows a total input capacitance of 50 fF and also controls the voltage swing and common-mode voltage at the input of the LVDS driver output stage. This makes the operation at low supply voltages using a conventional 0.18 $muhbox{m}$ CMOS technology feasible. The output driver circuit consumes 4.5 mA while driving an external 100 $Omega $ resistor with an output voltage swing of $V_{OD} = $400 mV, achieving a normalized power dissipation of 3.42 mW/Gbps. The area of the LVDS driver circuit is 0.067 ${hbox{mm}}^{2}$ and the measured output jitter is $sigma _{rms} = $4.5 ps. Measurements show that the proposed LVDS driver can be used at frequencies as high as 2.5 Gbps where the speed will be limited by the load $RC$ time constant.      

Feedback Biasing in Nanoscale CMOS Technologies

This work rediscovers the attractiveness of feedback biasing when applied to circuits designed in nanoscale CMOS technologies. It is shown that very compact amplifiers can be obtained by utilizing a type of biasing that imposes minimal area overhead. We discuss how the undesired features of the nanoscale CMOS technologies actually help in the revival of this simple biasing method in newer technology generations. The measurement results of prototyped common-source (CS) amplifiers utilizing feedback biasing for application in medical ultrasound imaging systems are presented in this brief. The proposed feedback biasing is also suitable for amplifying signals from high-impedance sources that pose challenges on maintaining high input impedance for the voltage amplifiers while maintaining a very low input capacitance value. Measurements show that the proposed amplifier achieves a voltage gain of 28 dB, an output noise power spectral density of 0.11 $(muhbox{V})^{2}/ hbox{Hz}$ at center-frequency, and a total harmonic distortion of $-$30 dB, with the full-scale output at 30 MHz, while drawing 120 $muhbox{A}$ from a 1-V power supply. The amplifiers were fabricated in 90-nm CMOS technology and measured to be just $20 muhbox{m} times 10 muhbox{m}$.      

A Sub-100 $mu{rm W}$ Ku-Band RTD VCO for Extremely Low Power Applications

This letter presents the microwave performance of a sub-100 $mu{rm W}$ Ku-band differential-mode resonant tunneling diode (RTD)-based voltage controlled oscillator (VCO) with an extremely low power consumption of 87 $mu{rm W}$ using an InP-based RTD/HBT MMIC technology. In order to achieve the extremely low-power Ku-band RTD VCO, the device size of RTD is scaled down to $0.6times 0.6 mu{rm m}^{2}$. The obtained dc power consumption of 87 $mu{rm W}$ is found to be only 1/18 of the conventional-type MMIC VCOs reported in the Ku-band. The fabricated RTD VCO has a phase noise of $-$100.3 dBc/Hz at 1 MHz offset frequency and a tuning range of 140 MHz with the figure-of-merit (FOM) of $-$194.3 dBc/Hz.      

A 47 GHz Cross-Coupled VCO Employing High- Island-Gate Varactor for Phase Noise Reduction

A 47 GHz $LC$ cross-coupled voltage controlled oscillator (VCO) employing the high-$Q$ island-gate varactor (IGV) based on a 0.13 $mu{rm m}$ RFCMOS technology is reported in this work. To verify the improvement in the phase noise, two otherwise identical VCOs, each with an IGV and a conventional multi-finger varactor, were fabricated and the phase noise performance was compared. With $V_{DD}$ of 1.2 V and core power consumption of 3.86 mW, the VCOs with the IGV and the multi-finger varactor have a phase noise of $-$95.4 dBc/Hz and $-$91.4 dBc/Hz respectively, at 1 MHz offset, verifying the phase noise reduction with the introduction of the high-$Q$ IGV. The VCO with IGV exhibited an output power of around $-$15 dBm, leading to a FoM of $-$182.9 dBc/Hz and a tuning range of 3.35% (45.69 to 47.22 GHz).      

A 98/196 GHz Low Phase Noise Voltage Controlled Oscillator With a Mode Selector Using a 90 nm CMOS Process

A 98/196 GHz low phase noise voltage controlled oscillator (VCO) with a fundamental/push-push mode selector using a 90 nm CMOS process is presented in this letter. An innovative concept of the VCO with the mode selector is proposed to switch the fundamental or second harmonic to the RF output. The VCO demonstrates a fundamental frequency of up to 98 GHz with an output power of greater than $-8~{rm dBm}$. The phase noise of the VCO is better than $-100.8~{rm dBc}/{rm Hz}$ at 1 MHz offset frequency, and its figure-of-merit is better than $-186~{rm dBc}/{rm Hz}$. Moreover, the output frequency of the work is up to 196 GHz with a fundamental suppression of greater than $-30~{rm dBc}$ as the VCO is operated in push-push mode.