A high-voltage, high-temperature reverse conducting thyristor

This paper describes the structure and electrical characteristics of a silicon p-n-p-n inverter switch which has been fabricated to demonstrate the feasibility of obtaining both high-voltage and high-temperature capability in the same device while still maintaining reasonable dynamic properties. It was realized that in most inverter systems, feedback rectifiers are required, and thus the reverse blocking capability of a thyristor is not utilized. This was used to advantage in the design of a thyristor by integrating an anti-parallel rectifier into a conventional thyristor structure. Although this approach results in a thyristor having a negligible reverse blocking capability in comparison to commercially available power thyrisitors, the potential advantages of lower conduction losses, high maximum junction temperatures, and integrated antiparallel rectifier may be attractive for use in inverters. Reverse conducting thyristors designed in this fashion have been operated with reasonable turnoff times at a forward blocking voltage of 1000 volts while at case temperatures of up to 230°C.     

A 3 A sink/source current fast transient response low-dropout Gm driven linear regulator

A 3 A sink/source G_m-driven CMOS low-dropout regulator(LDO),specially designed for low input voltage and low cost,is presented by utilizing the structure of a current mirror G_m(transconductance)driving technique,which provides high stability as well as a fast load transient response.The proposed LDO was fabricated by a 0.5μm standard CMOS process,and the die size is as small as 1.0 mm~2.The proposed LDO dissipates 220μA of quiescent current in no-load conditions and is able to deliver up to 3 A of load current.The measured results show that the output voltage can be resumed within 2μs with a less than 1mV overshoot and undershoot in the output current step from-1.8 to 1.8 A with a 0.1μs rising and falling time at three 10μF ceramic capacitors.     

Experimental response of MOS devices to a fast linear voltage ramp

An experimental investigation is undertaken of the response of an MOS device to a linear voltage ramp of such speed as to take the device into non-equilibrium, but to allow sufficient generation to take place during the voltage sweep to provide structure in the C-V curves which can be analysed quantitatively. The main aim has been to investigate the effect of sweep rate per se, but additional data is presented which considers the voltage dependence of the space-charge width, the maximum sweep rate for quasi-equilibrium, and the effect of temperature. It is demonstrated that the technique provides quantitative information on bulk traps and a qualitative measure of the relative role of interface traps in the generation process. Transitions are observed between quasi-equilibrium and non-equilibrium which are a function of sweep rate. This is in contrast to the pulse technique, where the response is of a purely transient nature.     

A linear voltage regulator for an implantable device monitoring system

This paper describes a CMOS implementation of a Linear Voltage Regulator (LVR) used to power an implanted physiological signal system that is used to monitor the blood pressure. The topology is based on a classical structure of a Low Dropout Regulator (LDO) and receives his activation energy from a RF link characterizing a passive RFID tag. The LVR was designed to achieve important features like low power consumption, and a small silicon area without the need for any external discrete components. The low power operation represents an essential condition to avoid a high energy RF link, thus minimizing the power of the transmitter and the thermal effects on the patient tissues. The project was diffused in a 0.35 μm CMOS TSMC technology and a prototype was tested to validate the overall performance. The LVR output is regulated at 1 V and supplies a maximum load current of 0.5 mA @ 37°C. The load regulation is 13 mV/mA and the line regulation is 39 mV/V. The LVR total power consumption is 1.2 mW.     

一款灌入/拉出3A电流跨导驱动快速瞬态响应低漏失稳压器

本文设计了一款可以灌入(sink)和拉出(source)3A电流,低电源、低功耗的CMOS低漏失电压线性稳压器。采用电流镜像结Gm(跨导)驱动的LDO架构可以获得高稳定性和快速负载瞬态响应。基于UMC 0.5um标准CMOS工艺投片验证,芯片面积为1.0mm2。空载时该LDO静态电流为220uA,最大带载3A。测试表明,使用30uF陶瓷电容,在-1.8A到 1.8A 0.1us负载跳变时,该LDO可以在低于2us的时间达到稳态,且过冲小于1mV。     

应用动态偏置和双环反馈技术的CMOS快速瞬态响应低压差线性稳压器设计

This paper presents a low-dropout regulator （LDO） for portable applications with dual-loop feedback and a dynamic bias circuit. The dual-loop feedback structure is adopted to reduce the output voltage spike and the response time of the LDO. The dynamic bias circuit enhances the slew rate at the gate of the power transistor. In addition, an adaptive miller compensation technique is employed, from which a single pole system is realized and over a 59~ phase margin is achieved under the full range of the load current. The proposed LDO has been implemented in a 0.6μm CMOS process. From the experimental results, the regulator can operate with a minimum dropout voltage of 200 mV at a maximum 300 mA load and IQ of 113μA. The line regulation and load regulation are improved to 0. l mV/V and 3.4 μV/mA due to the sufficient loop gain provided by the dual feedback loops. Under a full range load current step, the voltage spikes and the recovery time of the proposed LDO is reduced to 97 mV and 0.142 μs respectively.     

A fast transient response low dropout regulator with current control methodology

A transient performance optimized CCL-LDO regulator is proposed.In the CCL-LDO,the control method of the charge pump phase-locked loop is adopted.A current control loop has the feedback signal and reference current to be compared,and then a loop filter generates the gate voltage of the power MOSFET by integrating the error current.The CCL-LDO has the optimized damping coefficient and natural resonant frequency, while its output voltage can be sub-l-V and is not restricted by the reference voltage.With a 1μF decoupling capacitor,the experimental results based on a 0.13μm CMOS process show that the output voltage is 1.0 V;when the workload changes from 100μA to 100 mA transiently,the stable dropout is 4.25 mV,the settling time is 8.2μs and the undershoot is 5.11 mV;when the workload changes from 100 mA to 100μA transiently,the stable dropout is 4.25 mV,the settling time is 23.3μs and the overshoot is 6.21 mV.The PSRR value is more than -95 dB.Most of the attributes of the CCL-LDO are improved rapidly with a FOM value of 0.0097.     

基于电流环路控制方法的快速响应LDO

LDO电路的瞬态响应能力是评价LDO性能的一个重要指标。本文借鉴电荷泵式锁相环的环路控制方法,提出了一种基于电流控制环路的LDO结构,将典型LDO电路中的电压比较改为电流比较,利用跨导放大器和环路滤波器产生功率管的控制栅压,使得环路具有优化的阻尼因子ζ和固有频率ωn,有效提高了LDO环路的瞬态响应能力,并且输出电压可以低至1V以下,且不受基准电压的限制。基于0.13μm CMOS工艺的实现结果表明,在使用1μF去耦电容,LDO输出1.0V的情况下,负载100μA→100mA瞬态变化时,输出超调5.11mV,稳定输出的压降4.25mV,稳定时间8.2μs,而负载100mA→100μA时,输出超调6.21mV,稳定输出的压降4.25mV,稳定时间23.3μs。结果表明,该电路各项性能指标均有明显的提高,FOM指数达到0.0097。     

A highly efficient inductorless voltage regulator

This versatile and highly efficient voltage regulator, for applications where the conventional series regulator and the inductor type of switching regulator are impractical, uses solid-state switching techniques. Efficiencies greater than 90 percent have been achieved, independent of input voltage amplitudes. Good load regulation is provided, with a ripple increase as the main effect of a load-current increase. High-peak-current capability is another major advantage of the regulator. The circuit described successfully delivers power peaks of 600 watts. Output voltage restoration from the power line is accomplished as quickly as possible. Some applications of the regulator are prereugulation, class-B audio amplifiers, and solenoid driving.     

A monolithic high-power series voltage regulator

A complete series voltage regulator circuit capable of delivering /SUP 1///SUB 2/ ampere of current has been built on a single 63/spl times/66-mil die using the conventional all- diffused processing technology. Improved performance has been achieved by using an internal low-power voltage regulator to supply the desired dc output voltage reference directly to a second main regulator. This permits the dc and ac characteristics of the regulator to be separately optimized with the result that excellent transient characteristics are realized simultaneously with low drift and excellent regulation.     

A novel, linear voltage variable MMIC attenuator

Voltage variable attenuators (VVAs) for microwave applications that are fabricated using present technology and design methods feature a nonlinear relationship between the attenuation measured in decibels and the control signal. A novel VVA that features a linear attenuation-control-voltage relationship without the need for external linearization is described. This is accomplished by connecting a number of FET segments in a unique fashion to form a composite FET. The channel resistance of the composite FET constitutes a prescribed function of its gate-source voltage. By careful design the resistance functions that are necessary for realization of linear attenuators are synthesized. The attenuator was fabricated using GaAs MMIC technology employing MESFETs as voltage variable resistors. It is completely passive and does not require a DC supply. The attenuation ranges from 2 to 15 dB over DC to 8 GHz while port impedance is kept close to 50 Ω. The deviation of the attenuation from a straight line is less than 0.2 dB     

A CMOS fast transient response low-dropout regulator with a compact NMOS output driver

We present a CMOS low-dropout voltage regulator with a high-speed NMOS compact driver suitable for supplying on-chip voltages for the digital core of a SoC. The LDO is part of a power management controller hardblock integrated within a microcontroller. The die area of the circuit implemented in a 90 nm CMOS process is only 0.054 mm². Experimental results show that the developed LDO can supply up to 15 mA and it presents a very fast transient response, with a settling time of approximately 30 ns and a voltage drop of 200 mV when the load current changes from 100 nA to 9 mA.     

低压差线性稳压器中过流保护电路的设计

设计了一种应用于低压差线性稳压器的过流保护电路.该电路结构简单,易于调整,功耗低,可采用0.5μmCMOS工艺实现.仿真结果表明,它可以把稳压器的最大输出电流限定在300mA,输出短路电流限定在40mA,能够实现过流保护的目的.     

一种新型可控硅固态调压装置

本文介绍了一种利用可控硅相控整流技术调节电压的方法及实用装置。对组成调压装置的主要电路的设计思想和工作原理作了简要分析。并结合该装置的实际应用介绍了一些优点并提出了自己的看法。     

A multimodule parallelable series-connected PWM voltage regulator

This paper presents the analysis and design of a single-phase voltage regulator (VR) and its multinodule parallel control. The VR employs the pulsewidth modulation three-arm rectifier-inverter topology. The inverter side adjusts the load voltage with the series regulating structure aiming to minimize converter capacity and attain higher efficiency. The rectifier side regenerates the load power and executes the active power filter function to achieve unity power factor. Based on such high-performance VR, a resistive droop method combined with the P-V droop and Q-δ shift scheme is then proposed to control the current sharing such that multiple VRs can be paralleled directly without any control interconnection. The proposed parallel control technique possesses the features of fast response, precise voltage regulation, equal fundamental and harmonic current sharing, tolerance for parameter mismatch, and so on. Two prototype 1 KVA VRs are implemented, and the effectiveness is demonstrated by some simulation and experimental results     

新型多路输出数字调压电路的设计

研究了一种新型多路输出数字调压电路。以FPGA为核心,利用其丰富的I/O口,实现多路电压同时输出。待转换的数据经USB2.0接口输入FPGA内部FIFO中,减少电压配置时间。采用高压运放芯片,工作于非对称供电模式。实验结果表明,电压调节范围-39V~+49.95V,步进调节灵敏度为0.0244V,最大输出电流50mA,纹波电压小于2mV。     

A novel switching-mode ac buck-boost voltage regulator

This paper presents a novel switching-mode ac/ac voltage regulator using a bidirectional buck-boost converter. Since it operates at high frequency, the proposed system can be designed compactly, and there is a wide range of input voltage from 1/2 to 2 per unit with fast dynamic response and low harmonics. In order to verify the accuracy of the proposed method, a 500 W prototype has been implemented in the laboratory. From the experimental results, the regulation of the output voltage is within less than 1%. Moreover, the total harmonic distortion (THD) of the input current under full load is 2.46% and the output voltage has a THD of 1.77%.     

Critical bandwidth for the load transient response of voltage regulator modules

This paper investigates the relationship between the control bandwidth and the load transient response in voltage regulator modules (VRMs), which are designed with multiphase interleaving synchronous buck converters. Both voltage- and current-mode controls are discussed. A critical bandwidth value is discovered, beyond which pushing the bandwidth can no longer reduce the output voltage spike during the load transient response. Also, the critical bandwidths are different according to different kinds of output capacitors. The critical bandwidth concept highlights the trend of high-frequency VRM design that uses ceramic capacitors to achieve smaller size and faster load transient response. Simulation and experimental results prove the theoretical analysis.     

一种分高低压供电的低压差线性稳压器的设计

针对传统低压供电的低压差线性稳压器线性响应比较慢的情况,提出了一种基于BICMOS 0.5μm工艺分高低压供电的低压差线性稳压器。经过Hspice仿真验证,该稳压器具有高增益、高PSRR（Power Supply Rejection Ratio,电源抑制比）、低功耗、响应速度快的特点,输入电压范围为0.5~28.0 V,输出电压为5 V。此稳定器低频时的开环增益达到86 dB,相位裕度为68o,低频时的电源电压抑制比为–91 dB,高频时也能达到–2 dB,静态电流只有13.5μA。     

辐照诱生的双极性线性稳压器的1/f 噪声退化研究

研究发现辐照能使双极线性稳压器LM117的输出1/f噪声性能退化。本文在研究双极线性稳压器LM117的辐照失效机理基础上,认为LM117的内部带隙基准是其噪声性能退化的关键部件,辐照引起的带隙基准内部的双极性晶体管的基极表面复合电流的退化,导致LM117输出1/f噪声发生退化。通过对比,可以看出1/f噪声比电参数敏感,也可以用来表征LM117辐照损伤。