A slew-rate controlled output driver using PLL as compensation circuit

A slew-rate controlled output driver adopting the delay compensation method has been implemented using 0.18-/spl mu/m CMOS process for storage device interface. A phase-locked loop (PLL) is used to generate compensation current and constant delay time. The compensation current reduces the slew-rate variation over process, voltage, and temperature variation of the output driver. The constant delay time, which is generated by the replica of the voltage-controlled oscillator in the PLL, reduces the slew-rate variation over load capacitance variation. Such an output driver has 25% less variation at slew rate than that of the conventional output driver. The proposed output driver is able to meet UDMA100 interface that specifies load capacitance ranging from 15 to 40 pF and slew rate from 0.4 to 1.0 V/ns.     

An effective BIST scheme for SRAM full speed test

This article presents a novel built-in self-test (BIST) scheme at full speed test where access time test is performed. Based on normal BIST circuits, we harness an all digital phase locked loop to generate a high-frequency clock for static random access memory (SRAM) performance test at full speed. A delay chain is incorporated to achieve the four-phase clock. As inputs to SRAM, clock, address, data are generated in terms of the four-phase clock. Key performance parameters, such as access time, address setup and hold times, are measured. The test chip has been fabricated by United Microelectronics Corporation 55?nm CMOS logic standard process. According to test results, the maximum test frequency is about 1.3?GHz, and the test precision is about 35?ps at the typical process corner with supply voltage 1.0?V and temperature 25°C.     

与工艺、电源电压和温度无关的低功耗振荡环设计

分析了传统片外时钟和片内时钟各自的特点和应用背景,在Chartered 0.35μm CMOS工艺下实现了一个低功耗PVT(工艺、电源电压、温度无关)振荡环,对片内时钟的稳定性和功耗进行改进。该振荡环无需精准的电压源,采用了误差补偿技术,通过偏置电压和延时单元的相互补偿,使得振荡频率对于工艺、温度和电源电压均有较大的容差能力。并且由于针对延时单元补偿的方式,令周期大小易于调整。蒙特卡罗仿真显示,工艺误差引起的偏差要比补偿前的偏差减小了60%。流片测试结果表明,在工作温度变化范围0~100°C时,振荡环输出的频率偏差为±3.22%;在电源电压变化范围为2.8~3.8 V时,振荡环输出的频率偏差为±3.36%;在电源电压3.3 V的情况下,整个芯片消耗的电流为950μA。     

A CMOS voltage buffer with slew-rate enhancement

A high slew-rate CMOS voltage buffer has been presented in this article. The slew-rate enhancement is achieved by an embedded driver stage activated by internal nodes in the voltage buffer through capacitive coupling. The capacitive coupling provides one-shot auto-off feature for the driver stage. Therefore, the drive stage can be turned off automatically after activation. The auto-off feature of the proposed driver stage guarantees a reliable operation. The proposed voltage buffer is implemented in a commercial 0.35-μm CMOS technology. The active chip area is 345 μm × 246 μm. The single supply voltage is 3.3 V, and the quiescent current is about 7 μA. When the proposed buffer drives a capacitive load of 220 pF, the measured positive and negative slew rates are 0.714 and 1.548 V/μs, respectively. The improvement corresponds to about 22 times for the positive slew rate and 48 times for the negative slew rate when comparing with the voltage buffer without the proposed the slew-rate enhancement circuit.     

Frequency multiplier using pulse-width control loop

A frequency multiplier circuit based on a well-known pulse-width control loop is presented. The proposed circuit can be used to enhance the output frequency range of a phase-locked loop (PLL) by using multiple phases of the voltage-controlled oscillator. It can be used for enhancing the output frequency range of new as well as existing PLL designs with minimum impact on PLL loop dynamics. The circuit is generic in nature and can be used with any multi-phase oscillator type. The circuit is designed in 65 nm complimentary metal oxide semiconductor (CMOS) technology and has been simulated across process, voltage and temperature (PVT) corners with temperature variation from ?40°C to 125°C, analogue supply voltage variation from 1.62 V to 1.98 V, and digital supply voltage variation from 1.1 V to 1.3 V.     

Temperature compensated and gated CMOS ring oscillator for time-to-digital converter application

This paper presents a CMOS voltage controlled ring oscillator with temperature compensation for low power time-to-digital converters (TDCs). In order to maintain the oscillation frequency stable, a novel compensation circuit is proposed through adaptively sensing temperature variations. This design has been implemented in TSMC 0.35 μm CMOS standard process with an active area of under 0.039 mm². Experimental results show that the clock frequency is around 159.0 MHz only with a power consumption of 550 μA. As respective to the room temperature the maximum frequency variation is between ?3.46 and +3.08 % under temperature range of ?40 to 85 °C. The bit error time induced by clock jitter is limited within 4.8 % in the whole clock period, and the differential nonlinearity of the TDC is less than 0.408 LSB.     

Integrated AlGaAs/GaAs HBT high slew-rate and wide band operationalamplifier

We report the design, fabrication, and test results of a wide band and high slew-rate voltage-mode operational amplifier using AlGaAs/GaAs HBT's. To select higher carbon doping concentration is more effective in reducing base resistance, and lower emitter doping concentration possess a smaller input capacitance to improve the device speed. The HBT operational amplifier has provided 500 V/μs high slew-rate, only 8 ns setting time and about 2 GHz unity-gain frequency. Common mode rejection ratio (CMRR) values of this operational amplifier are in the order of 70 dB with a small DC input voltage offset 5 mV, and the open-loop gain is about 40 dB     

A low-power circuit block for digital telephone exchanges

An integrated static 128 bit serial memory with logic circuitry at its input and transmission line drivers at its output is described. It works at a supply voltage of ?2 V ± 17%. Its power dissipation is 90 mW, and its maximum clock frequency is 40 MHz. Chip size is 3 × 4 mm².     

A wide supply voltage range and low-power all-digital clock generator

This study presents a low-power all-digital clock generator (ADCG) for a wide supply voltage range system. The proposed ADCG limits the maximum supply current to 100 μA at a supply voltage ranging from 1.6 to 3.6 V. The ADCG also uses a digitally controlled oscillator (DCO) to extend its operational frequency range. The proposed DCO controls the supply current and divider circuits for a wide supply voltage range. The output duty cycle of ADCG falls within 50 ± 1.9 % using a duty cycle corrector. The maximum peak-to-peak jitter is less than 2.7 % at 8.38 MHz for a digital water meter application (DWM). The operational frequencies of 1.45 and 8.38 MHz at 1.8 V are 3.1 and 36.7 μA, respectively. The core area of ADCG is 0.14 mm² for a 0.35 μm CMOS process. The operational frequency of ADCG ranges from 4.5 to 9.2 MHz at a supply voltage ranging from 1.6 to 3.6 V. This clock generator can also be applied to microcontroller applications.     

A Chip for Linearization of RF Power Amplifiers using Predistortion based on a Bit-Parallel Complex Multiplier

This paper presents a custom chip for linearization of RF power amplifiers using digital predistortion. The chip has been implemented in a standard digital 0.8 m CMOS process with standard static cells and single-phase clocking. A systolic complex multiplier based on distributed arithmetic constitutes the core of the chip. The nonlinear function is realized with a look-up table containing complex gain factors applied to the complex multiplier. Maximum clock frequency was found by means of simulation to be 105 MHz corresponding to 21 Msamples/s throughput with 3 W power consumption using 5 V supply voltage. The fabricated chip is fully functional and has been measured up to 60 MHz clock frequency with 825 mW power consumption with 3.3 V supply voltage. Operation at 1.5 V supply voltage allows 10 MHz clock frequency with 35 mW power consumption.     

Dual-bridge LLC-SRC with extended voltage range for deeply depleted PEV battery charging

This paper proposes a dual-bridge LLC series resonant converter with hybrid-rectifier for achieving extended charging voltage range of 50–420 V for on-board battery charger of plug-in electric vehicle for normal and deeply depleted battery charging. Depending upon the configuration of primary switching network and secondary rectifier, the proposed topology has three operating modes as half-bridge with bridge rectifier (HBBR), full-bridge with bridge rectifier (FBBR) and full-bridge with voltage doubler (FBVD). HBBR, FBBR and FBVD operating modes of converter achieve 50–125, 125–250 and 250–420 V voltage ranges, respectively. For voltage above 62 V, the converter operates below resonance frequency zero voltage switching region with narrow switching frequency range for soft commutation of secondary diodes and low turn-off current of MOSFETs to reduce switching losses. The proposed converter is simulated using MATLAB Simulink and a 1.5 kW laboratory prototype is also built to validate the operation of proposed topology. Simulation and experimental results show that the converter meets all the charging requirements for deeply depleted to fully charged battery using constant current-constant voltage charging method with fixed 400 V DC input and achieves 96.22% peak efficiency.     

A miniature high-efficiency fully digital adaptive voltage scaling buck converter

A miniature high-efficiency fully digital adaptive voltage scaling (AVS) buck converter is proposed in this paper. The pulse skip modulation with flexible duty cycle (FD-PSM) is used in the AVS controller, which simplifies the circuit architecture (<170 gates) and greatly saves the die area and the power consumption. The converter is implemented in a 0.13-μm one-poly-eight-metal (1P8 M) complementary metal oxide semiconductor process and the active on-chip area of the controller is only 0.003 mm², which is much smaller. The measurement results show that when the operating frequency of the digital load scales dynamically from 25.6 MHz to 112.6 MHz, the supply voltage of which can be scaled adaptively from 0.84 V to 1.95 V. The controller dissipates only 17.2 μW, while the supply voltage of the load is 1 V and the operating frequency is 40 MHz.     

5?Gb/s 2:1 fully-integrated full-rate multiplexer with on-chip clock generation circuit in 0.18-μm CMOS

A 5?Gb/s 2:1 full-rate multiplexer (MUX) has been designed and fabricated in SMIC 0.18-??m CMOS process. A clock generation circuit (CGC) is also integrated to provide the MUX with both 2.5 and 5-GHz clock signals. The CGC is realized by a clock and data recovery (CDR) loop with a divide-by-2 frequency divider embedded in, where the two required clocks are obtained after and before the divider, respectively. In addition, the phase relation between data and clock is assured automatically by CDR feedback loop and the precise layout. The whole chip area is 812?×?675???m, including pads. At a single supply voltage of 1.8?V, the total power consumption is 162?mW with an input sensitivity of <25?mV and a single-ended output swing of above 300?mV. And due to the full-rate architecture, the pulse width distortion (PWD) with multiplexed data is removed. The measured results also show that the circuit can work reliably at any input data rate between 2.46 and 2.9?Gb/s without need for external components, reference clock, or manual phase alignment between data and clock.     

An ultra-high-speed direct digital synthesizer with nonlinear DAC and wave correction ROM

This paper presents a novel direct digital synthesizer (DDS) architecture combining Nonlinear DAC with a small-sized wave-correction-ROM (WCR), which achieves both high operating speed and accuracy. A 6?GHz 8-bit DDS chip based on the proposed architecture is designed and fabricated in a 60?GHz GaAs HBT technology. The major blocks of the DDS MMIC based on ECL logic includes an 8-bit pipelined accumulator, an 8?×?8?×?3-bit WCR, two combined digital-to-analog converters (DACs) and an analog Gilbert Cell for sine-wave generation, a 3-to-7 thermometer coder, digital logic gates and registers. A method of using a series of RC networks to terminate the clock tree together with a pot-layout simulation scheme is developed to maintain the clock tree signal integrity. The DDS chip is tested using an on-wafer measurement approach. The measured spurious free dynamic range (SFDR) is 33.96 dBc with a 2.367?GHz output using a 6?GHz maximum clock frequency. The measurement also shows an average SFDR of 37.5 dBc and the worst case SFDR of 31.4 dBc (FCW?=?112) within the entire Nyquist band under a 5?GHz clock. The chip occupies 2.4?×?2?mm² of area and consumes a 3.27?W of power from a single ?4.6?V power supply.     

基于薄膜SOI的PDP高压寻址驱动集成电路

基于自主开发的薄膜SOI高低压兼容工艺,研制出一种64位输出的薄膜SOI PDP高压寻址驱动集成电路.测试结果显示,该电路具有80 V驱动电压和20 mA输出电流,电路时钟频率大于40 MHz.     

A 1.2-V, 84-dB \begin{document}$\Sigma\Delta$\end{document} ADM in 0.18-μm digital CMOS technology

A low power and low voltage \begin{document}$\Sigma\Delta$\end{document} analog-to-digital modulator is realized with digital CMOS technology, which is due to full compensated depletion mode capacitors. Compared with mixed signal technology, this type of modulator is more compatible for pure digital applications. A pseudo-two-stage class-AB OTA is used in switched-capacitor integrators for low voltage and low power. The modulator is realized in standard SMIC 0.18 μm 1P6M digital CMOS technology. Measured results show that with 1.2 V supply voltage and a 6 MHz sample clock, the dynamic range of the modulator is 84 dB and the total power dissipation is 2460 μW.     

一种采用共栅频率补偿的轨到轨输入/输出放大器

提出了一种采用共栅频率补偿的轨到轨输入/输出放大器,与传统的Miller补偿相比,该放大器不仅可以消除相平面右边的低频零点,减少频率补偿所需要的电容,还可获得较高的单位增益带宽.所提出的放大器通过CSMC 0.6μm CMOS数模混合工艺进行了仿真设计和流片测试:当供电电压为5V,偏置电流为20μA,负载电容为10pF时,其功耗为1.34mW,单位增益带宽为25MHz;当该放大器作为缓冲器,供电电压为3V,负载电容为150pF,输入2.66 Vpp10kHz正弦信号时,总谐波失真THD为-51.6dB.     

A bipolar output voltage pulse transformer boost converter with charge pump assisted shunt regulator for thermoelectric energy harvesting

This system presents an energy harvesting system that generates bipolar output voltage (±1 V) based on a miniature 1:1 turn-ratio pulse transformer boost converter using sub-threshold level input voltage source. A shunt regulator is designed using six-transistor Schmitt-Trigger core to limit the boost converter output voltage. Another power stage, i.e. a fully integrated on-chip single-stage cross-coupled charge pump, then generates 3 V output from the unused extra output power of boost converter, which is shunted otherwise. The increased voltage headroom generated is instrumental for sensor, analog and RF circuits. Charge pump clock frequency is designed to adaptively tracking the input voltage, which is sensed using power-saving time-domain digital technique. Based on a standard CMOS 0.13-µm technology, chip measurement verified the operations of the boost converter, shunt regulator and bipolar charge pump prototypes, respectively. Simulations confirmed the full system operations. During start-up, the system only requires minimum start-up input voltage of 36 mV at input power of 5.8 µW.     

数字/频率、频率/数字转换电路的应用

介绍了数字／频率转换(D／F)一频率／电压转换(F／V)的数据发送方法和电压／频率转换(v／F)一频率／数字转换(F／D)的数据采集方法,并对D／F、F／D电路以及F／V、V／F电路进行了详细介绍。总结了相对于模拟／数字转换(A／D)、数字／模拟转换(D／A)的数据传送方式,D／F、F／D电路的优缺点。     

一种用于数字麦克风的低功耗低电压LDO

数字麦克风具有抗干扰能力强、集成度高、易于使用等优点,用于对功耗、体积敏感的便携式设备.研究了用于数字麦克风的低压差线性稳压器(LDO),该LDO除了具有稳压功能,为系统提供稳定和确定的电压外,还能在时钟频率低于休眠频率时,使数字麦克风进入休眠状态.流片测试表明,LDO电压调节范围为1.6～3.5 V,休眠频率为40～60 kHz,芯片待机电流为9μA.