Plasma-charging effects on submicron MOS devices

Plasma-charging damage on gate dielectrics of MOS devices is an important issue because of shrinking dimension, plasma nonuniformity, and effects on high-k gate dielectrics. A comprehensive study of plasma-charging effects on the electrical properties of MOS devices was investigated in this work. Shunt diodes were used to estimate the charging polarity distribution. For high-frequency application, the 1/f noise was found to be a promising index for assessing plasma-charging damage. Gate oxynitride formed by two-step nitridation was demonstrated to have better electrical reliability as compared to the conventional one-step nitridation, especially accompanied by amorphous silicon gate electrode. This improvement could be attributed to the relaxation of interface stress by amorphous silicon gate electrode and the suppression of hydrogen effects by gate oxynitride using two-step nitridation. Plasma-charging damage on Si₃N₄ and Ta₂O₅ gate dielectrics with high dielectric constant was also investigated. For MOS devices with Si₃N₄ film, the leakier characteristic and shorter time to breakdown reveal its inferior reliability. For MOS devices with Ta₂O₅ gate dielectric, the trap-assisted current mechanism makes a thicker physical thickness of Ta₂O₅ film more susceptible to plasma-charging-induced damage. Smaller physical thickness of Ta₂O₅ film in MOS devices is favorable due to the better reliability and comparable plasma-induced electrical degradation     

Comparison of effective work function extraction methods using capacitance and current measurement techniques

The effective work function (EWF) extracted on terraced oxide structures by capacitance-voltage-based techniques was compared with the work function calculated from the barrier height extracted by current-voltage measurements. The results show a reasonable correlation-within /spl plusmn/ 0.1 eV-in the EWF values for various metal gate electrodes, validating both techniques for EWF extraction.     

Effects of Al2O3 Dielectric Cap and Nitridation on Device Performance, Scalability, and Reliability for Advanced High- κ/Metal Gate pMOSFET Applications

A pFET threshold-voltage (Vt) reduction of about 200 mV is demonstrated by inserting a thin Al₂O₃ layer between the high-k dielectric and the TiN gate without noticeable degradation of other electrical properties. HfSiO_propcapped with 9 Aring of thin Al₂O₃obtains a low long-channel Vt of -0.37 V (the lowest among those with TiN gate), a high mobility of 59 cm² /V ldr s at 0.8 MV/cm (92% of universal value), a negligible equivalent- oxide-thickness (EOT) increase of 0.1 Aring (compared to the uncapped reference), and a low Vt instability of 4.8 mV at 7 MV/cm. It also passes the ten-year negative-bias-temperature-instability (NBTI) lifetime specification with a gate overdrive of -0.7 V. This indicates that thin Al₂O₃obtains caps are beneficial to the pFET applications. In contrast, nitrogen incorporation in the Al₂O₃-capped HfSiO_prop is not favorable because it increases the Vt by 50-140 mV, degrades the mobility by 10%-22%, increases the EOT by 0.5-0.8 Aring and the Vt instability by 5-13 mV, and reduces the NBTI lifetime by four to five orders of magnitude. Compared to postcap nitridation, high-k nitridation results in more severe degradation of these properties by incorporating nitrogen closer to the Si/SiO₂ interface.     

Yttrium- and Terbium-Based Interlayer on SiO2 and HfO2 Gate Dielectrics for Work Function Modulation of Nickel Fully Silicided Gate in nMOSFET

Novel yttrium- and terbium-based interlayers (Y_IL and Tb_IL, respectively) on SiO₂ and HfO₂ gate dielectrics were employed for NMOS work function Phi_m modulation of undoped nickel fully silicided (Ni-FUSI) gate. Bandedge Ni-FUSI gate Phi_m of ~4.11 and ~4.07 eV was obtained by insertion of ultrathin (~1 nm) Y_IL and Tb_IL, respectively, on the SiO₂ gate dielectric in a gate-first process (with 1000 degC anneal). NiSi Phi_m on SiO₂ could also be tuned between the Si midgap and the conduction bandedge E_C by varying the interlayer thickness. The achievement of NiSi Phi_m around 4.28 eV on the HfO₂ gate dielectric using interlayer insertion makes this an attractive Phi_m modulation technique for Ni-FUSI gates on SiO₂ and high-k dielectrics     

Off-state gate current in n-channel MOSFETs with nitrided oxidegate dielectrics

The authors report on the off-state gate current (I_g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I_g at drain voltages as low as 4 V and an I_g injection efficiency reaching 0.8, as compared to 8.5 V and 10^-7 in SiO₂ devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I_g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure     

An improved two-frequency method of capacitance measurement forSrTiO3 as high-k gate dielectric

An improved two-frequency method of capacitance measurement for the high-k gate dielectrics is proposed. The equivalent circuit model of the MOS capacitor including the four parameters of intrinsic capacitance, loss tangent, parasitic series inductance, and series resistance is developed. These parameters can be extracted by independently measuring the capacitor at two different frequencies. This technique is demonstrated for high-k SrTiO₃ gate dielectrics and the results show that the calibrated capacitances are invariant over a wide range of frequency. In addition, the extracted loss tangent, inductance and resistance are independent on gate voltage and frequency. The effect of series resistance on the frequency dispersion of the capacitance can be also explained by this model. These results indicate that this modified technique can be incorporated in the routine capacitance-voltage (C-V) measurement procedure providing the physically meaningful data for the high-k gate dielectrics     

金属栅/高k基FinFET研究进展

对比传统的平面型晶体管,总结了三维立体结构FinFET器件的结构特性。结合MOS器件栅介质材料研究进展,分别从纯硅基、多晶硅/高k基以及金属栅/高k基三个阶段综述了Fin-FET器件的发展历程,分析了各阶段FinFET器件的材料特性及其在等比缩小时所面临的关键问题,并着重从延迟时间、可靠性和功耗三方面分析了金属栅/高k基FinFET应用于22 nm器件的性能优势。基于短沟道效应以及界面态对器件性能的影响,探讨了FinFET器件尺寸等比缩小可能产生的负面效应及其解决办法。分析了FinFET器件下一步可能的发展方向,主要为高迁移率沟道材料、立体型栅结构以及基于新原理的电子器件。     

Electrical and material property enhancement in HfTaSiON-gated MOS devices by tuning Hf composition

High dielectric constant (high-k) materials, as a replacement for conventional gate dielectrics, have been proposed to overcome the problem of excessive gate leakage current. HfSiON is a potential high-k gate dielectric material, but the value of its dielectric constant is considered a little too low. In this work, we incorporate Ta into HfSiON to form a HfTaSiON gate dielectric. The influences of different Hf contents in HfTaSiON and various post deposition anneal (PDA) treatments were studied in detail. Experimental results show thatimprovements on the material and electrical properties of metal-oxide-semiconductor (MOS) devices such as crystallization temperature, interface quality between high-k dielectric/Si, hysteresis, stress-induced leakage current (SILC) and interface trap density (D_it) are achieved with incorporating a suitable amount of Hf in HfTaSiON high-k gate dielectric     

Effects of nitridation pressure on the characteristics of gatedielectrics annealed in N2O ambient

Effects of N₂O pressure during oxynitridation on the characteristics of ultrathin gate dielectrics have been investigated. Reoxidation in N₂O ambient showed three distinguished oxidation regions as a function of tube pressure; that is, enhancement at 10-40 torr, retardation at 40-100 torr, and enhancement at 100-600 torr. The N₂O-nitridation at 40 torr incorporated much less nitrogen in oxide bulk than that at near-atmospheric pressure. The 40 torr N₂O-nitridation case exhibited about 70% of nitrogen incorporation at the Si/SiO₂ interface compared to that of the 600 torr N₂O-nitridation case. The low-pressure N₂ O-nitridation at 40 torr results in improvement of TDDB of gate dielectrics and the transconductance of nMOSFETs compared to the nitridation at near-atmospheric pressure. These data suggest that low pressure oxynitridation should be more recommendable for device application     

Thermal Nitridation of Si and SiO/sub 2/ for VLSI

This paper presents an extensive review of our work on thermal nitridation of Si and SiO/sub 2/. High-quality ultrathin films of silicon nitride and nitrided-oxide (nitroxide) have been thermally grown in ammonia atmosphere in a cold-wall RF-heated reactor and in a lamp-heated system. The growth kinetics and their dependence on processing time and temperature have been studied from very short to long nitridation times. The kinetics of thermal nitridation of SiO/sub 2/ in ammonia ambient have also been studied. In nitroxide, nitrogen-rich layers are formed at the surface and interface at a very early stage of the nitridation. Then the nitridation reaction mainly goes on in the bulk region with the surface and near interface nitrogen content remaining fairly constant. Our results also indicate the formation of an oxygen-rich layer at the interface underneath the nitrogen-rich layer whose thickness increases slowly with nitridation time. The nitride and nitroxide films were analyzed using Auger electron spectroscopy, grazing angle Rutherford backscattering, and etch rate measurements. MIS devices were fabricated using these films as gate insulators and were electrically characterized using I-V, C-V, time-dependent breakdown, trapping, and dielectric breakdown techniques. Breakdown, conduction, and C -V measurements on metal-insulator semiconductor (MIS) structures fabricated with these films show that very thin thermal silicon nitride and nitroxide films can be used as gate dielectrics for future highly scaled-dowm VLSI devices. The electrical characterization results also indicate extremely low trapping in the nitride films. The reliability of ultrathin nitride was observed to be far superior to SiO/sub 2/ and nitroxide due to its much less trapping. Studies show that the interface transition from nitride to silicon is almost abrupt and the morphology and roughness of the interface are comparable to the SiO/sub 2/-Si interfaces.     

Effective Work-Function Modulation by Aluminum-Ion Implantation for Metal-Gate Technology (Poly-Si/TiN/SiO2)

The impact of aluminum (Al) implantation into TiN/SiO₂ on the effective work function (EWF) of poly-Si/ TiN/SiO₂ is investigated. Al implanted at 5 keV with a dose of 5 times 10¹⁵ cm^-2 reduces the flatband voltage (V_FB) and the EWF of poly-Si/TiN/SiO₂ stack by ~150 mV compared with the unimplanted poly-Si/TiN/SiO₂ stack. This reduction of V_FB is found to be dose-dependent, which is correlated to the Al concentration at the TiN-SiO₂ interface as evidenced by secondary-ion-mass-spectrometry profiles. The interface dipole created due to the Al presence at the metal-dielectric interface is believed to contribute to the observed V_FB (or EWF) reduction (or increase). This technique for EWF modulation is promising for further threshold-voltage (V_t) tuning without any process complexities and is quite significant for planar and multiple gate field-effect transistors on fully depleted silicon on insulator.     

Frequency-dependent capacitance reduction in high-k AlTiOx and Al2O3 gate dielectrics from IF to RFfrequency range

We have characterized the capacitance and loss tangent for high-k Al₂O₃ and AlTiO_x gate dielectrics from IF (100 KHz) to RF (20 GHz) frequency range. Nearly the same rate of capacitance reduction as SiO₂ was demonstrated individually by the proposed Al₂O₃ and AlTiO_x gate dielectrics as frequency was increased. Moreover, both dielectrics preserve the higher k better than SiO₂ from 100 KHz to 20 GHz. These results suggest that both Al₂O₃ and AlTiO_x are suitable for next generation MOSFET application into RF frequency regime     

Characteristics of Self-Aligned Gate-First Ge p- and n-Channel MOSFETs Using CVD HfO2 Gate Dielectric and Si Surface Passivation

The electrical properties of p- and n-MOS devices fabricated on germanium with metal-organic chemical-vapor-deposition HfO₂ as gate dielectric and silicon passivation (SP) as surface treatment are extensively investigated. Surface treatment prior to high-K deposition is critical to achieve small gate leakage currents as well as small equivalent oxide thicknesses. The SP provides improved interface quality compared to the treatment of surface nitridation, particularly for the gate stacks on p-type substrate. Both Ge p- and n-MOSFETs with HfO₂ gate dielectrics are demonstrated with SP. The measured hole mobility is 82% higher than that of the universal SiO₂/Si system at high electric field (~0.6 MV/cm), and about 61% improvement in peak electron mobility of Ge n-channel MOSFET over the CVD HfO₂ /Si system was achieved. Finally, bias temperature-instability (BTI) degradation of Ge MOSFETs is characterized in comparison with the silicon control devices. Less negative BTI degradation is observed in the Ge SP p-MOSFET than the silicon control devices due to the larger valence-band offset, while larger positive BTI degradation in the Ge SP n-MOSFET than the silicon control is characterized probably due to the low-processing temperature during the device fabrication     

堆叠栅介质MOS器件栅极漏电流的计算模型

采用顺序隧穿理论和传输哈密顿方法并考虑沟道表面量子化效应,建立了高介电常数堆叠栅介质MOS器件栅极漏电流的顺序隧穿模型。利用该模型数值,研究了Si3N4/SiO2、Al2O3/SiO2、HfO2/SiO2和La2O3/SiO2四种堆叠栅介质结构MOS器件的栅极漏电流随栅极电压和等效氧化层厚度变化的关系。依据计算结果,讨论了堆叠栅介质MOS器件按比例缩小的前景。     

Electrical properties of MOSFET's with N2O-nitridedLPCVD SiO2 gate dielectrics

Electrical properties of MOSFETs with gate dielectrics of low-pressure chemical-vapor-deposited (LPCVD) SiO₂ nitrided in N₂O ambient are compared to those with control thermal gate oxide. N₂O nitridation of CVD oxide, combines the advantages of interfacial oxynitride growth and the defectless nature of CVD oxide. As a result, devices with N₂O-nitrided CVD oxide show considerably enhanced performance (higher effective electron mobility), improved reliability (reduced charge trapping, interface state generation, and transconductance degradation), and better time-dependent dielectric breakdown (TDDB) properties (t_BD ) compared to devices with control thermal oxide     

Lateral nonuniformity of effective oxide charges in MOS capacitors with Al/sub 2/O/sub 3/ gate dielectrics

The high-frequency Terman's method for interface-trap-density (D/sub it/) extraction is used to examine the lateral nonuniformity (LNU) of effective oxide charges in MOS capacitors. The two-parallel-subcapacitor model is constructed to simulate LNU charges, and it was shown that the value of the found effective D/sub it/ appears negative as the LNU occurs in the gate oxide. This technique was first used to examine the effective oxide charge distribution in Al/sub 2/O/sub 3/ high-k gate dielectrics prepared by anodic oxidation and nitric-acid oxidation. It was found that the LNU effect in Al/sub 2/O/sub 3/ is sensitive to oxidation mechanisms and can be avoided by using an appropriate oxidation process. The proposed technique is useful for the preparation and reliability improvement of high-k gate dielectrics.     

Impact of High-k Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs

The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities k. It is observed that there is a decrease in the parasitic outer fringe capacitance C_of in addition to an increase in the internal fringe capacitance C_if with high-k dielectrics, which degrades the short-channel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-k integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum k for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineering     

Electrical Properties of Low-Temperature-Compatible P-Channel Polycrystalline-Silicon TFTs Using High-$kappa$ Gate Dielectrics

In this paper, we describe a systematic study of the electrical properties of low-temperature-compatible p-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs) using HfO₂ and HfSiO_x, high-k gate dielectrics. Because of their larger gate capacitance density, the TFTs containing the high-k gate dielectrics exhibited superior device performance in terms of higher I_on/I_off current ratios, lower subthreshold swings (SSs), and lower threshold voltages (V_th), relative to conventional deposited-SiO₂, albeit with slightly higher OFF-state currents. The TFTs incorporating HfSiO_x, as the gate dielectric had ca. 1.73 times the mobility (mu_FE) relative to that of the deposited-SiO₂ TFTs; in contrast, the HfO₂ TFTs exhibited inferior mobility. We investigated the mechanism for the mobility degradation in these HfO₂ TFTs. The immunity of the HfSiO_x, TFTs was better than that of the HfO₂ TFTs-in terms of their V_th shift, SS degradation, mu_FE degradation, and drive current deterioration-against negative bias temperature instability stressing. Thus, we believe that HfSiO_x, rather than HfO₂, is a potential candidate for use as a gate-dielectric material in future high-performance poly-Si TFTs.     

Electrical and Reliability Characteristics of 12- Å Oxynitride Gate Dielectrics by Different Processing Treatments

Various ultrathin oxynitride gate dielectrics of similar thickness (~1.2 nm) fabricated by a combination of an in situ steam generated and remote plasma nitridation treatment (RPN), an RPN with rapid thermal NO annealing (RPN-NO), and an RPN with rapid thermal O₂ annealing (RPN-O₂) are reported in this paper. The RPN-NO gate dielectric films show superior interface properties including relatively high nitrogen concentration near the poly-Si/oxide interface and smooth interfaces, excellent electrical characteristics in terms of lower leakage current, better electron and hole channel mobility, higher drive current, and significantly improved reliability such as stress-induced leakage current, hot carrier injection, and negative bias temperature instability, compared to other gate dielectrics fabricated by different processes.     

High-k Al/sub 2/O/sub 3/ gate dielectrics prepared by oxidation of aluminum film in nitric acid followed by high-temperature annealing

A simple, cost-effective, and room temperature process was proposed to prepare high-k gate dielectrics. An aluminum oxide (Al/sub 2/O/sub 3/) gate dielectric was prepared by oxidation of ultrathin Al film in nitric acid (HNO/sub 3/) at room temperature then followed by high-temperature annealing in O/sub 2/ or N/sub 2/. The substrate injection current behavior and interface trap-induced capacitance were introduced to investigate the interfacial property between the gate dielectric and Si substrate. Al/sub 2/O/sub 3/ gate dielectric MOS capacitors with and without initial SiO/sub 2/ layers were characterized. It was shown that the Al/sub 2/O/sub 3/ gate dielectrics with initial oxide exhibit better electrical properties than those without. The 650/spl deg/C N/sub 2/-POA Al/sub 2/O/sub 3/-SiO/sub 2/ sample with an equivalent oxide thickness of 18 /spl Aring/ exhibits three orders of magnitude reduction in gate leakage current in comparison with the conventional thermal SiO/sub 2/ sample.