Design considerations of CMOS active inductor for low power applications

Previous studies have shown that \(g_m/I_D\) (transconductance-to-drain-current) ratio based design is useful for optimizing analog circuits. In this paper, we explore challenges associated with designing a low-power active inductor. We focus in particular on sizing issues that arise as the transistor speed is maximized and the current consumption is minimized. Finally, we apply the results to design an amplifier integrated with an active inductor in \(0.18\,\upmu \hbox{m}\) CMOS process and show that by systematically working through sizing issues, a \(10\,\upmu \hbox{A}\) sub GHz amplifier can be designed.     

A deep submicron CMOS process compatible suspending high-Q inductor

A novel high-Q on-chip inductor structure called suspending inductor is developed to improve the characteristics of the conventional on-chip spiral inductor. The suspending inductor employs the air gap and is supported by a set of novel metal pillars to suppress the capacitance from the metal layer to the substrate. The measured maximum quality factor of the suspending inductor is improved from 4.8 to 6.3 in comparison to the conventional spiral inductor. Furthermore, the frequency at maximum quality factor is raised from 1.5-2 GHz     

RF CMOS active inductor band pass filter with post fabrication calibration

This paper presents an active inductor bandpass filter (BPF) architecture with selectable 50 Ω driving capability and post fabrication calibration for gain, center frequency, and quality factor. The design details, and performance assessment that facilitate selecting an offline calibration mode to measure and tune post fabrication BPF performance are discussed. A specific design example for a L1/L2 channel GPS receiver is included with a BPF that is required to pass the L2 signal centered at 1.227 GHz with a gain of approximately16 dB at the center frequency, have a 3 dB bandwidth of 30 MHz (Q = 41) and rejection of the L1 signal at 1.575 GHz by at least 60 dB relative to the center frequency. A multistage active inductor BPF 90 nm CMOS design is presented that meets these specifications with typical process parameters. It is demonstrated that the post fabrication design based on typical corner analysis can be re-tuned to the desired performance for process variations across the slow and fast corners using the offline measuring and tuning control inputs.     

Compact low voltage four quadrant CMOS current multiplier

A new compact low voltage four quadrant current mode CMOS multiplier is presented. Post layout simulation in a CMOS 0.5 μm technology shows a linearity error lower than 0.9% for signal swings up to ±50 μA. The circuit operates at a supply of ±1.5 V, has a static power dissipation of 0.6 mW and a 1 dB bandwidth of 33 MHz     

De-embedding method for on-wafer RF CMOS inductor measurements

In this work, an accurate de-embedding method for on-wafer RF measurements of CMOS large area devices like the inductors is presented. The method uses distributed and lumped-element models to represent the parasitic elements. The interconnect parasitics are calculated using the transmission line theory. The proposed method is compared to existing de-embedding methods. The validity of the method is checked with the DC resistance value of the interconnects as calculated from the layout and as extracted from measurements, as well as with inductance results of the fabricated inductor, extracted from measurements and from electromagnetic simulations. On-wafer S-parameter measurements have been taken from a test chip up to 20 GHz.     

Low-voltage low-power high-Q CMOS RF bandpass filter

Based on the gyrator-C inductor topology, a second-order bandpass filter can be realised by adding a series capacitor to the input port of the gyrator. high-Q second-, fourth- and sixth-order fully differential RF bandpass filters operating in the 2.4 GHz Industrial, Scientific and Medical (ISM) frequency band under a 2 V single power supply voltage with low-power dissipation are demonstrated     

用于射频集成的高Q硅基电感的优化设计

采用理论分析与电磁仿真结合的方法,对硅上多层金属构成的螺旋电感进行电性能研究,优化并获得一种适用于射频电路集成的硅基射频高Q电感。对于影响电感Q值的多种损耗机制,重点研究了趋肤效应对电感的影响。并通过结构参数及金属层叠优化后,硅上电感的Q值可以达到60以上,自谐振频率可以达到10 GHz以上,可以较好地应用于射频系统中的滤波选频及匹配等网络。     

Wide tunable CMOS active inductor

A tunable CMOS active inductor is presented. The circuit uses a crosscoupled pair of transistors providing positive feedback for enhanced quality factor. The circuit is biased with a controllable current source varying the feedback and tuning the inductor. The proposed inductor is designed and simulated in a 90 nm digital CMOS process. It shows a wide-frequency range inductive impedance and a very high resonance frequency. By cascading two inductors, a wideband filter/ amplifier is designed to characterise the inductor performance.     

Design of low distortion active inductor and its applications

This paper proposes a novel distortion reduction technique for active inductors. A bias current of a MOSFET, which acts as transconductor in an active inductor, is controlled to reduce a distortion of a active inductor. When an input voltage increases, the bias current is decreased by a control circuit. As a result of this control, transconductance of the MOSFET remains constant. An active inductor using this technique is free from distortion caused by a transconductance variation of a MOSFET. The proposed technique is applied to two different conventional active inductors and novel low distortion active inductors are derived. Computer simulations show that distortion of the proposed active inductor is very low. The proposed low distortion active inductors are applied to a second order bandpass filter and a voltage controlled oscillator. Thanks to the proposed technique, distortion of these circuits are reduced and their performance is improved.     

CMOS source degenerated differential active inductor

A new CMOS source degenerated differential active inductor is proposed. The proposed differential active inductor required only six transistors or more for proper operation. It is very compact compared to a conventional differential active inductor that was design using two differential transconductors and which requires at least ten transistors. The proposed active inductor was fabricated using Silterra 0.18 mum CMOS process for demonstration. Measurement results show that the proposed active inductor has a wide tuning range with a maximum resonance frequency of 7.85 GHz.     

Digitally controlled CMOS current follower for low voltage lowpower applications

A novel digitally controlled CMOS current follower is proposed. The circuit is useful for low voltage low power high frequency applications. The DCCF operates from a 3 V supply in class AB mode and provides precise digitally programmable current gain without component spread. Experimental results from a 1.2 μm CMOS chip fabricated through MOSIS are provided     

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver is presented. The problems to implement the low voltage design and the on-chip input/output impedance matching are considered, and some improved circuits are presented to overcome the problems. Especially, a single-end input, differential output double balanced mixer with an on-chip bias loop is analyzed in detail to show its advantages over other mixers. The transceiver RF front-end has been implemented in 0.18 um CMOS process, the measured results show that the Rx front-end achieves 5.23 dB noise figure, 12.7 dB power gain (50 ohm load), −18 dBm input 1 dB compression point (ICP) and −7 dBm IIP3, and the Tx front-end could output +2.1 dBm power into 50 ohm load with 23.8 dB power gain. The transceiver RF front-end draws 13.6 mA current from a supply voltage of 1.8 V in receive mode and 27.6 mA current in transmit mode. The transceiver RF front-end could satisfy the performance requirements of IEEE802.11b WLAN standard. Supported by the National Natural Science Foundation of China, No. 90407006 and No. 60475018.     

A simple CMOS process compatible high performance parallel-stacked spiral inductor for advanced RF analog circuit applications

A high Q on-chip inductor with some unique structures has been fabricated with 0.13 μm CMOS compatible process for the first time. The unique structures including parallel stacked, line via between inter-metal layers, and use the top signal pad as the under path of the inductor instead of conventional bottom signal pad. These structures offer advantages of reducing resistance, high Q value, simple preparing process and small chip area. Experimental results show that the measured peak Q and peak-Q frequency can attain 7.06 and 1.8 GHz, respectively for the structure with four metal layers in parallel, 15 μm in metal width, 5.5 turns in wire number,and an area of 204×240 μm². The results have a better potential for advanced mobile communication applications.     

Compact power-efficient class-AB CMOS exponential voltage to voltage converter

A novel implementation of a rail-to-rail exponential voltage to voltage converter is presented. It is based on a pseudo-exponential approximation that is easily achieved by the nonlinear currents of a class-AB transconductor. Measurement results for a 0.5 /spl mu/m CMOS technology show a 52 dB output voltage range with linearity error less than /spl plusmn/2 dB using a dual supply voltage of /spl plusmn/750 mV. The power dissipation is less than 40 /spl mu/W.     

Integrated CMOS wideband oscillator for RF applications

A fully integrated LC oscillator with a tuning range of 800 MHz is presented. A combination of capacitive and inductive tuning has been used to produce the large tuning range with a low-gain control input. The phase noise at 1.9 GHz is as low as -120 dBc/Hz at 500 kHz offset. Possible applications include integer-N PLLs with a low level of reference spurs     

CMOS RF circuits for data communications applications

The author describes the recent development of two analog CMOS circuits operating at RF frequencies with applications to data communications. One is a four-quadrant analog multiplier which exhibits a 100-MHz bandwidth with a measured linearity error of 0.7% for X and Y inputs of 0.6 and 0.8 V, respectively. The other is a 90/spl deg/ phase shifter which maintains the grain and phase errors of less than 0.5 dB and 3/spl deg/, respectively, for a signal within 40-60-MHz frequency range.     

CMOS four-quadrant analogue multiplier for RF applications

A CMOS four-quadrant multiplier consisting of four MOS transistors operating in the saturation region is introduced. The circuit exploits the quadratic relation between the current and voltage of the MOS transistor in saturation. Simulation results show that, for a supply voltage of 1.2 V multiplication can be performed at a frequency of 1.8 GHz, achieving better performances than a recently proposed similar architecture     

一种应用于6-9GHz UWB系统的低噪声CMOS射频前端设计

本文介绍了一种应用于6-9 GHz超宽带系统的全集成差分CMOS射频前端电路设计。在该前端电路中应用了一种电阻负反馈形式的低噪声放大器和IQ两路合并结构的增益可变的折叠式正交混频器。芯片通过TSMC 0.13µm RF CMOS工艺流片,含ESD保护电路。经测试得该前端电路大电压增益为23~26dB,小电压增益为16~19dB;大增益下前端电路平均噪声系数为3.3-4.6dB,小增益下的带内输入三阶交调量(IIP3)为-12.6dBm。在1.2V电压下,消耗的总电流约为17mA。     

A low noise CMOS RF front-end for UWB 6-9 GHz applications

An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented.A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13μm RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB,an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of-12.6 dBm while in th...