18 Gbit/s monolithically integrated 2:1 multiplexer and laser driving using 0.3 mu m gate length quantum well HEMTs

A monolithically integrated 2:1 multiplexer and laser diode driver was developed, using AlGaAs quantum well HEMTs of 0.3 mu m gate length. The DC and modulation current is 25 and 45 mA, respectively. Open eye diagrams were measured at bit rates up to 18 Gbit/s with pseudorandom data streams.<>     

15 Gbit/s integrated laser diode driver using 0.3 mu m gate length quantum well transistors

An integrated laser diode driver was realised using enhancement/depletion 0.3 mu m recessed-gate AlGaAs/GaAs quantum well transistors. Fully-open eye diagrams were observed at bit rates up to 10 Gbit/s with 50 Omega loads. The maximum DC and modulation current were 25 and 45 mA, respectively. The power consumption is less than 450 mW.<>     

Integrated laser-diode voltage driver for 20-Gb/s optical systemsusing 0.3-μm gate length quantum-well HEMT's

An integrated laser-diode voltage driver (LDVD) making use of enhancement/depletion AlGaAs-GaAs quantum-well high electron mobility transistors (QW HEMTs) with gate lengths of 0.3 μm has been developed. Its large signal bandwidth is 12 GHz. Eye diagrams of the output signal at bit rates up to 8 Gb/s show an opening similar to that of the input signal. Supporting material is given indicating that the LDVD might operate at bit rates up to 20 Gb/s. The maximum output current is over 90 mA; the maximum modulation voltage of 800 mV corresponds to 40-mA modulation current for a laser diode with 20-Ω dynamic resistance. The power consumption is less than 500 mW     

A monolithically integrated 1-Gb/s optical receiver in 1-μm CMOStechnology

Results of a monolithically integrated Si optical receiver for applications in optical data transmission and in optical interconnects with wavelengths of 638 and 850 nm are presented. The optoelectronic integrated circuit (OEIC) implementing a vertical p-type-intrinsic-n-type photodiode achieves a data rate of 1 Gb/s for 638 nm with a sensitivity of -15.4 dBm at a bit-error rate of 10^-9 . The sensitivity of this OEIC in a 1.0-μm CMOS technology is improved by at least a factor of four compared to that of published submicrometer OEICs. A 25-THz.Ω effective transimpedance bandwidth product of the implemented amplifier is achieved     

10Gb/s突发模式时钟数据恢复电路设计

突发模式的时钟数据恢复是10G EPON系统的关键技术之一。本文介绍了一种基于XNOR/XOR门的振荡器,分析了其工作原理与性能,以此为基础设计了半速率突发时钟恢复电路。设计采用SMIC 0.13?m CMOS工艺进行了流片验证,芯片面积为675?m ? 625?m。测试结果表明,该电路可以即时的实现10Gbit/s的突发数据恢复,恢复出的时钟数据符合IEEE 802.3av标准,锁定时间小于5bit。     

0.3-μm gate length p-channel AlGaAs/InGaAs heterostructure fieldeffect transistors with high cut-off frequency

P-channel Heterostructure Field Effect Transistors (HFETs) with a 0.3-μm gate were fabricated by Mg ion implantation. The maximum transconductance was 68 mS/mm and there was no serious drain or gate leakage current, regardless of this short gate length. The gate turn on voltage (@I_gs=-1 μA/μm) was -2.1 V and its absolute value was large enough for use in complementary HFETs. S-parameters measurements showed a very high cut-off frequency of over 10 GHz. Results indicated the superiority of less-diffusive Mg ion implantation for forming p⁺-layer in p-channel HFETs     

A 1.7 Gb/s ASK and a 622 Mb/s incoherent FSK transmissionexperiment using a 1.55-μm multiquantum well distributed feedbacklaser

A multiple-quantum-well distributed-feedback (MQW-DFB) laser with narrow linewidth and low frequency chirp at low output power may experience linewidth rebroadening at high output power. the rebroadening is mostly due to a large carrier-induced change of refractive index, which also causes a large frequency modulation response for the MQW-DFB lasers. Using a 1.55-μm MQW-DFB laser, a 622-Mb/s amplitude-shift-keying (ASK) transmission experiment employing 200-km of fiber and an erbium-doped fiber amplifier has been demonstrated having a dispersion power penalty less than 9.8 dB. The receiver sensitivities at BER=10^-9 of the ASK system are -34.5 dBm and -42.5 dBm for 1.7-Gb/s and 622-Mb/s modulation, respectively. A 622-Mb/s incoherent frequency-shift-keying (FSK) transmission experiment using the same laser has also achieved a receiver sensitivity of -42.5 dBm     

Cavity length and doping dependence of 1.5-μm GaInAs/GaInAsPmultiple quantum well laser characteristics

High-power, 1.5-μm, ridge-waveguide lasers with GaInAs/GaInAsP multiple-quantum-well active layers are discussed. For 1-mm-long devices, a threshold current of 35 mA and an output power of 62 mW per facet were measured. The cavity-length and doping dependence of the threshold current, quantum efficiency, and resonant frequency were investigated experimentally. With heavy Zn doping in the barrier layers, an increase in differential gain by a factor of 1.8 was observed     

基于高精细度F-P滤波器的40Gb/s全光时钟提取

提出了一种基于高精细度Fabry-Perot(F-P)滤波器的全光时钟提取方案,并进行了实验验证。为了实现对信号波长无关的特性,系统利用光纤中交叉相位调制(XPM)效应对输入信号进行正码波长变换,使变换后的波长始终与F-P滤波器的透射峰精确对准。采用精细度为1 012的高精细度F-P滤波器提取时钟,并利用半导体光放大器(SDA)的自增益调制(SGM)效应进一步抑制时钟信号的低频噪声,保证了高质量的时钟输出。实验中,利用这种装置对40 Gb/s归零(RZ)码信号进行了时钟提取,得到了抖动为285 fs的高质量40 GHz时钟信号,验证了方案的可行性。     

A 10 Gb/s high sensitivity, monolithically integrated p-i-n-HEMToptical receiver

A high-sensitivity, monolithically integrated optical receiver, composed of a p-i-n-PD and high electron mobility transistors (p-i-n-HEMTs) is described. The receiver sensitivity is -17.3 dBm at a bit error rate of 1×10^-9 for a 10-Gb/s non-return-to-zero (NRZ) lightwave signal. This value is the best result yet reported for 10-Gb/s monolithically integrated receivers. The sensitivity is -30.6 dBm if an erbium-doped fiber amplifier (EDFA) is placed ahead of the p-i-n-NEMT receiver. A transmission experiment using a 150-km dispersion-shifted fiber (DSF) indicates no degradation in the bit error rate characteristics or the eye pattern. This verifies the practicality of the p-i-n-HEMT optical receiver for high-speed transmission systems     

High-temperature optically pumped 1.55-μm VCSEL operating at 6Gb/s

Vertical cavity lasers operating at a wavelength of 1547 nm were optically pumped by a 980-nm diode laser. Continuous-wave fiber-coupled output powers of 2 mW at room temperature and 140 nW at 105°C were observed. Fiber optic transmission over 25 km at 6 Gbit/s with a power penalty of 0.3 dB was demonstrated     

High-performance 0.1-μm gate enhancement-mode InAlAs/InGaAsHEMT's using two-step recessed gate technology

Novel approach for making high-performance enhancement-mode InAlAs/InGaAs HEMT's (E-HEMT's) is described for the first time. Most important issue for the fabrication of E-HEMT's is the suppression of the parasitic resistance due to side-etching around the gate periphery during gate recess etching. Two-step recessed gate technology is utilized for this purpose. The first step of the gate recess etching removes cap layers wet-chemically down to an InP recess-stopping layer and the second step removes only the recess-stopping layer by Ar plasma etching. The parasitic component for source resistance is successfully reduced to less than 0.35 Ω·mm. Etching selectivities for both steps are sufficient not to degrade uniformity of devices on the wafer. The resulting structure achieves a positive threshold voltage of 49.0 mV with high transconductance. Due to the etching selectivity, the standard deviation of the threshold voltage is as small as 13.3 mV on a 3-in wafer. A cutoff frequency of 208 GHz is obtained for the 0.1-μm gate E-HEMT's. This is therefore one of the promising devices for ultra-high-speed applications     

A 30-MHz hybrid analog/digital clock recovery circuit in 2-μmCMOS

A high-speed hybrid clock recovery circuit composed of an analog phase-locked loop (PLL) and a digital PLL (DPLL) for disk drive applications is described. The chip operates at a maximum data rate of 33 MHz from a single 5-V power supply and achieves fast acquisition, a decode window of 95% of full window width, effective sampling jitter of 100-ps rms, and an effective input sampling rate of 1 GHz. The ring oscillator in the analog PLL shows a 62 p.p.m./°C temperature coefficient (TC) and 4.5%/V supply sensitivity of free-running frequency. The total power dissipation is about 600 mW, and the active area is 30000 mil² in a 2-μm single-poly double-metal n-well CMOS process     

A super-dynamic flip-flop circuit for broad-band applications up to24 Gb/s utilizing production-level 0.2-μm GaAs MESFETs

This paper describes a novel dynamic flip-flop (FF) circuit that can operate 30% faster than conventional clocked inverter-type FFs. A new wideband clock buffer is introduced to cover the FF operation range. An 8- to 24-Gb/s decision circuit and a 9- to 26-GHz 1/2 frequency divider were developed utilizing production-level 0.2-μm GaAs MESFET technology     

基于标准CMOS工艺的1.5Gb/s单片集成光接收机

A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35μm EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10-9. The chip dissipates 60 mW under a single 3.3 V supply.     

A 1.5 Gb/s monolithically integrated optical receiver in the standard CMOS process

A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 μm EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10~(-9). The chip dissipates 60 mW under a single 3.3 V supply.     

A 0.8-μm CMOS 2.5 Gb/s oversampling receiver and transmitter forserial links

A receiver targeting OC-48 (2.488 Gb/s) serial data link has been designed and integrated in a 0.8-μm CMOS process. An experimental receiving front-end circuit demonstrates the viability of using multiple phased clocks to overcome the intrinsic gate-speed limitations in the demultiplexing (receiving) and multiplexing (transmitting) of serial data. To perform clock recovery, data is 3× oversampled so that transitions can be detected to determine bit boundaries. The design of a transmitter for the high-speed serial data is also described. The complete transceiver occupies a die area of ~3×3 mm²     

A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver

An 8-Gb/s 0.3-μm CMOS transceiver uses multilevel signaling (4-PAM) and transmit preshaping in combination with receive equalization to reduce intersymbol interference due to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency acquisition scheme and a linear phase-locked loop that achieves a loop bandwidth of 35 MHz, phase margin of 50°, and capture range of 20 MHz without a frequency acquisition aid. The transmitted 8 Gb/s data are successfully detected by the receiver after a 10-m coaxial cable. The 2×2 mm² chip consumes 1.1 W at 8 Gb/s with a 3-V supply     

A 1.2-μm BiCMOS sample-and-hold circuit with aconstant-impedance, slew-enhanced sampling gate

A new sampling gate circuit, with dual outputs functioning alternately in the track and hold modes, is integrated in an open-loop sample-and-hold circuit architecture achieving greater than 450-MHz small-signal input bandwidth and 100-MHz maximum sample rate. The sampling gate also incorporates slew enhancement techniques to achieve (+430 V/μs, -510 V/μs) slew rate and features a `built-in' buffer to maintain constant input impedance for both the track and hold modes, simplifying design of the front-end input buffer. Special on-chip clock generation circuits are used to minimize sampled pedestal (+4 mV). Power dissipation is less than 300 mW, including output driver. Measured harmonics are 58 dB down for a 2 V_p-p 20-MHz sine wave sampled at 100 MHz     

A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique

A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-/spl mu/m standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2 ps rms and 47 ps pk-pk for 2/sup 31/-1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be -112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10/sup -6/ for 2/sup 31/-1 PRBS. The chip excluding output buffers dissipates 70 mW from a single 2.5-V supply.