Critical Thickness of Exponentially and Linearly Graded HgCdTe/CdZnTe

We have investigated the glide of strain-relaxing dislocations in closely lattice matched, liquid phase epitaxially (LPE) grown, HgCdTe. A generalized LPE heterostructure was modeled based on secondary-ion mass spectroscopy (SIMS) profile measurements. Critical thickness was predicted using a force balanced method which expands upon the work recently developed by Ayers. The behavior of dislocation dynamics is predicted with respect to exponentially and linearly graded metallurgical interfaces intrinsic to the high- temperature LPE growth process. The extended Ayers model is compared against x-ray topography and cross-sectional observations of misfit dislocations by the decoration of etch pits on cleaved HgCdTe/CdZnTe. The model predicts that, for bulk Cd/Zn compositions which are nearly lattice matched, the Zn compositional profile plays an important role in determining both the onset and distribution of misfit dislocations.     

Overshoot Graded Layers for Mismatched Heteroepitaxial Devices

We have studied the use of overshoot graded layers for the control of the dislocation density in mismatched heteroepitaxial layers. Graded ZnS _y Se_1–y structures were grown on GaAs (001) by photoassisted metalorganic vapor-phase epitaxy (MOVPE) and characterized by high-resolution x-ray diffraction (HRXRD). All samples had a uniform top layer of ZnS_0.014Se_0.986, and various graded layers were incorporated between the substrate and the uniform top layer; these included forward-graded (FG) and reverse-graded (RG) buffers. Some structures incorporated overshoot at the interface with the uniform top layer (FGO and RGO buffers). Among the FG samples, those with overshoot exhibited better crystal quality and lower dislocation densities than those without. This is expected because the mismatched interface between the graded layer and the top ZnS_0.014Se_0.986 can affect the bending over of threading dislocations for the production of misfit dislocations, indirectly promoting annihilation and coalescence reactions. An overshoot interface with 0.1% mismatch was found to remove 2 × 10⁸ cm⁻² dislocations from the top device layer. Overshoot did not reduce the dislocation density in RG structures, but this may be because the sign of the overshoot caused the generation of new dislocations rather than interactions between existing ones. For growing a high-quality device layer with minimal defect density, it appears that steep forward-graded layers with overshoot may be best in this material system.     

Exact Analytical Solution for the Critical Layer Thickness of a Lattice-Mismatched Heteroepitaxial Layer

Based on the Lambert W-function, an exact analytical solution for the critical thickness of a lattice-mismatched heteroepitaxial layer is presented. The new expression in exact and algebraic closed form eliminates the need for complex iterative computation. Its high accuracy is proved by comparison of the calculated critical thickness versus fractional atomic content of an alloy epilayer with the respective numerical solution.     

S-Graded Buffer Layers for Lattice-Mismatched Heteroepitaxial Devices

We have conducted a theoretical study of the equilibrium strain and misfit dislocation density profiles for ??S-graded?? buffer layers of In _x Ga_1?x As on GaAs (001) substrates in which the compositional profile follows a normal cumulative distribution function. On the basis of this modeling work we show that the S-graded layer exhibits misfit dislocation-free regions near the substrate interface and the free surface (or device interface). The equilibrium peak misfit dislocation density as well as the thicknesses of the dislocation-free regions may be tailored by design of the compositional profile; this in turn should enable minimization of the density of electronically active threading dislocations at the top surface. S-graded buffer layers may therefore facilitate the achievement of metamorphic device structures with improved performance compared with similar structures having uniform or linearly graded buffers.     

GexSi1—xSi应变层和超晶格及其临界厚度

异质外延层的性能和质量,往往取决于异质结构的特性。文章讨论了Ge_xSi-(1-x)/Si 应变层和应变层超晶格中的应变、位错和临界厚度,并比较了实验结果。     

Energy Conversion Efficiency of an Exponentially Graded Thermoelectric Material

This work describes an analytical model that predicts the effects of property gradients on the energy conversion efficiency of a functionally graded thermoelectric material (FGTEM) with an exponentially varying Seebeck coefficient S, electrical resistivity ρ, and thermal conductivity k. The figure-of-merit parameter, Z = S ²/(ρk), thus also varies exponentially. A closed-form solution for the temperature distribution in the FGTEM and the efficiency as a function of current density are obtained. The peak efficiency and the optimal current density are determined from the efficiency solution. It is found that the efficiency may be increased by about 30% using appropriate property gradients.     

Characterization of Dislocations in HgCdTe Heteroepitaxial Layers Using a New Substrate Removal Technique

Dislocations are known to influence the electrical and optical properties of long-wavelength infrared (LWIR) HgCdTe detectors and have been shown to limit the performance of arrays fabricated on heteroepitaxial substrates. To help better understand dislocations in HgCdTe, a new method for preparing HgCdTe diagnostic epitaxial single-crystal samples by chemically removing the supporting CdZnTe substrate has been developed. Using this new sample preparation technique, the behavior of misfit and threading dislocations in HgCdTe epitaxial layers has been investigated by using a defect etch to reveal the dislocations present in the thin HgCdTe films. In most cases etch pits on the surface of the film are spatially correlated with etch pits on the bottom of the HgCdTe film. The small displacements of the related etch pits were used to obtain crystallographic information concerning the paths followed by threading dislocations on allowed slip planes in the HgCdTe crystal. In addition, transmission electron microscopy (TEM) is used to obtain more specific information regarding the Burgers vector of the dislocation. While this new sample preparation technique is useful for studying dislocations in HgCdTe epitaxial layers, it can also be used to study stress from ohmic contacts and passivation layers. The technique can be used for both liquid-phase epitaxy (LPE)- and molecular-beam epitaxy (MBE)-grown HgCdTe on CdZnTe substrates.     

异质外延GaN中穿透位错对材料发光效率的影响

用阴极射线致发光(CL)法、透射电子显微镜(TEM)和X射线衍射(XRD)法研究了异质外延GaN材料的发光性质与结构特性的关系.结果表明,GaN外延层中的穿透位错是材料有效的非辐射复合中心,但GaN的CL带边峰强度并不随位错密度的增加而减少.两步法生长GaN形成的马赛克结构的亚晶粒尺寸和晶粒间合并产生的位错的弯曲程度是影响材料发光效率的关键.     

异质外延GaN中穿透位错对材料发光效率的影响

用阴极射线致发光(CL)法、透射电子显微镜(TEM)和X射线衍射(XRD)法研究了异质外延GaN材料的发光性质与结构特性的关系.结果表明,GaN外延层中的穿透位错是材料有效的非辐射复合中心,但GaN的CL带边峰强度并不随位错密度的增加而减少.两步法生长GaN形成的马赛克结构的亚晶粒尺寸和晶粒间合并产生的位错的弯曲程度是影响材料发光效率的关键.     

GaAs/InGaAs应变异质结构临界厚度的Raman散射和PL谱分析

采用室温Raman散射和低温光致发光(PL)谱,对以TMG,固体As和固体In作为分子束源的MOMBE法生长的GaAs/In_xGa_(1-x)As(x=0.3)单层异质结构和多量子阱结构中InGaAs应变层的临界厚度进行了实验研究。由应变引起的Raman散射峰位移,以及PL谱峰位置与应变和无应变状态下一维有限深势阱跃迁能量计算结果的比较可见,在In组分含量x=0.3的情况下,临界厚度H_c≤5nm,小于能量平衡理论的结果,而与力学平衡模型的理论值相近。     

薄膜SOI结构中反型层厚度与薄膜厚度的关系

本文从理论上分析了薄膜SOI结构中反型层厚度与薄膜厚度的关系。为设计薄膜MOS/SOI器件引进了一个新的参数──薄膜整体反型临界厚度。分析认为,为使超薄膜MOS/SOI器件高速和高功率工作,有必要使薄膜厚度接近整体强反型临界厚度。     

硅外延双层结构的厚度测量

硅外延是一种性能优良的半导体材料,在IGBT、大功率器件等领域中有着广泛的应用。FTIR（Fourier—Transform Infrared Spectrophotometry）技术是目前普遍采用的测量硅外延层厚度的先进方法,具有准确、快速、稳定、无损伤等其他方法无可比拟的优势。FTIR方法对于常规的低掺杂双层外延结构,只能测出两层外延的总厚度,而不能测出两个外延层分别的厚度。文章通过试验数据,证明了FTIR测试方法能够同时测量双层外延层结构的硅外延片的两层厚度,并提出了对中间层外延的电阻率的要求,同时对ASTM—F95标准中提出的FTIR法测量硅外延层厚度时对外延层和衬底层电阻率的要求,提出了新的范围。     

制备超薄多层膜的自动转速控厚法

在转速控厚法的基础上 ,排除了射频溅射的电磁干扰 ,实现了自动转速控厚法。用这种方法镀制超薄多层膜时 ,可以实时记录下镀制每层膜的沉积时间、自动切换转速、完成设定周期后自动停止转动。自动转速控厚法与转速控厚法相比 ,明显降低了多层膜制备的劳动强度 ,提高了多层膜制备的成品率和监控精度。而且将在镀制复杂膜系多层膜时 ,具有更加明显的优势     

p型4H-SiC同质外延有效层厚度

通过化学气相沉积法,采用不同生长工艺在4°偏角4H-SiC衬底上制备p型4H-SiC同质外延片。提出了p型4H-SiC同质外延中有效层厚度的概念,研究发现导致外延有效层厚度减少的直接原因是自掺杂效应的存在。采用傅里叶红外光谱仪(FT-IR)、汞探针电容电压(Hg-CV)和表面缺陷测试仪对p型4H-SiC同质外延片进行表征,讨论了不同工艺对外延有效层厚度的影响。结果表明,采用隔离法和阻挡层法均能提高外延有效层厚度,且掺杂浓度随距表面深度变化斜率值由1.323减小到0.073。然而,阻挡层法斜率值能进一步优化至0.050,是由于有效抑制了外延中固相和气相自掺杂。对比于优化前工艺,采用阻挡层法制备的p型4H-SiC同质外延片厚度不均匀性和表面总缺陷数量处于同一水平,掺杂浓度不均匀性由2.95%改善到2.67%。综上,采用阻挡层法能够制备出高有效层厚度、高一致性和高质量的p型4H-SiC同质外延片。     

双层有机电致发光器件AlQ厚度优化的研究

采用真空蒸发法制备了双层结构（ITO／NPB（15nm）／AlQ（x）／Mg：Ag）有机电致发光器件（OLED）。测试分析了8-羟基喹啉铝（AlQ）厚度对OLED的B-V、J-V，和η-V特性的影响，结果表明AlQ厚度对OLED器件的性能有显著的影响；当AlQ厚度在40nm时器件的发光亮度、发光效率以及稳定性都是最佳，但是当厚度变化时对光谱影响不大。     

双层有机电致发光器件AlQ厚度优化的研究

采用真空蒸发法制备了双层结构(ITO/NPB(15nm)/AlQ(x)/Mg:Ag)有机电致发光器件(OLED)。测试分析了8-羟基喹啉铝(AlQ)厚度对OLED的B-V、J-V和η-V特性的影响,结果表明AlQ厚度对OLED器件的性能有显著的影响;当AlQ厚度在40nm时器件的发光亮度、发光效率以及稳定性都是最佳,但是当厚度变化时对光谱影响不大。     

Critical Dimension Uniformity Via Real-Time Photoresist Thickness Control

In this paper, we present the experimental results on wafer-to-wafer and within-wafer critical dimension (CD) control. It is known that photoresist thickness affects CD. In this paper, we control photoresist thickness to control CD. As opposed to run-to-run control where information from the previous wafer or batch is used for control of the current wafer or batch, the approach here is real time and makes use of the current wafer information for control of the current wafer CD. The experiments demonstrate that such an approach can reduce CD nonuniformity wafer to wafer and within wafer.     

Cross-Interaction between Ni and Cu across Sn Layers with Different Thickness

The Ni/solder/Cu material sequence is one of the most common material sequences in the solder joints of electronic packages. In this study, the Ni/Sn/Cu ternary diffusion couples were used to investigate the solder volume effect on the cross-interaction between Ni and Cu. Experimentally, a pure Sn layer with the thickness of 100–400 μm was electroplated over Cu foils. A pure Ni layer (20 μm) was then deposited over the as-deposited Sn surface. The diffusion couples were aged at 160°C for different periods of time. With this technique, the diffusion couples were assembled without experiencing any high temperature process, such as reflow, which would have accelerated the interaction and caused difficulties in analysis. This study revealed that the cross-interaction could occur in as short as 30 min. A detailed atomic flux analysis showed that the Cu flux through the Sn layer was about 25–40 times higher than the Ni flux. Moreover, it was found that (Cu_1−x Ni _x )₆Sn₅ on the Ni side reduced the consumption rate of the Ni layer, and the cross-interaction also reduced the Cu₃Sn thickness on the Cu side.     

SIMOX薄膜材料的红外光谱特性和薄膜厚度的非破坏性测量方法

报道了 SOI材料薄膜厚度的非破坏性快速测量方法 ,详细地研究了 SIMOX材料的红外吸收光谱特性 ,求出了特征峰对应的吸收系数 .提出利用红外吸收光谱测量 SIMOX绝缘埋层厚度的非破坏性方法 ,并根据离子注入原理计算出表面硅层的厚度 .SIMOX薄膜的表层硅和绝缘埋层的厚度是 SOI电路设计时最重要的两个参数 ,提供的非破坏性测量方法 ,测量误差小于5% .在 SIMOX材料开发利用、批量生产中 ,用此方法可及时方便地检测 SIMOX薄膜的表层硅和绝缘埋层的厚度 ,随时调整注入能量和剂量     

SIMOX薄膜材料的红外光谱特性和薄膜厚度的非破坏性测量方法

报道了SOI材料薄膜厚度的非破坏性快速测量方法,详细地研究了SIMOx材料的红外吸收光谱特性,求出了特征峰对应的吸收系数.提出利用红外吸收光谱测量SIMOX绝缘埋层厚度的非破坏性方法,并根据离子注入原理计算出表面硅层的厚度.SIMOX薄膜的表层硅和绝缘埋层的厚度是SOI电路设计时最重要的两个参数,提供的非破坏性测量方法,测量误差小于5％.在SIMOX材料开发利用、批量生产中,用此方法可及时方便地检测SIMOX薄膜的表层硅和绝缘埋层的厚度,随时调整注入能量和剂量.