A VSWR-protected silicon bipolar RF power amplifier with soft-slope power control

This paper presents the design and measured performance of a 1.8-GHz power amplifier featuring load mismatch protection and soft-slope power control. Load-mismatch-induced breakdown can be avoided by attenuating the RF power to the final stage during overvoltage conditions. This was accomplished by means of a feedback control system, which detects the peak voltage at the output collector node and clamps its value to a given threshold by varying the circuit gain. The issue of output power control has been addressed as well. To this end, a temperature-compensated bias network is proposed, which allows a moderate power control slope (dB/V) to be achieved by varying the circuit quiescent current according to an exponential law. The nonlinear power amplifier was fabricated using a low-cost silicon bipolar process with a 6.4-V breakdown voltage. It delivers a 33.5-dBm saturated output power with 46% maximum power-added efficiency and 36-dB gain at a nominal 3.5-V supply voltage. The device is able to tolerate a 10:1 load standing-wave ratio up to a 5.1-V supply voltage. Power control slope is lower than 80 dB/V between -15 dBm and the saturated output power level.     

Improved circuit-device interface for microwave bipolar power transistors

Several improvements in the mounting and interconnection of bipolar microwave power transistors are described. A plated heat sink applied to thinned transistor pellets decreases the junction temperature for a given dissipation level by approximately a factor of 2. A new, low-parasitic-BeO carrier provides improved power sharing between cells and better high-frequency performance as illustrated by a CW power output of 4 W at 5 GHz with 6-dB gain. Finally, a new etched-line interconnection system is discussed that promises to become a highly reproducible, low-cost replacement for the widely used, but troublesome, multiple wire bonds.     

Lateral high-speed bipolar transistors on SOI for RF SoC applications

This paper introduces a novel silicon-on-insulator (SOI) lateral radio-frequency (RF) bipolar transistor. The fabrication process relies on polysilicon side-wall-spacer (PSWS) to self-align the base contact to the intrinsic base. The self-aligned base and emitter regions greatly reduce the parasitic components. In this unique design, the critical dimensions are not limited by lithography resolution. With the control of the SOI film thickness or SWS width, the device can be optimized for higher speed, gain, breakdown, or current drive capability. Furthermore, with no additional mask, both common-emitter and common-collector layout configurations can be realized, providing more flexibility to the circuit design and more compact layout. The experimental f/sub T//f/sub max/ of the high-speed device are 17/28 GHz, the second fastest reported f/sub T/ for lateral bipolar junction transistors (LBJT) so far. As for the high-voltage device, the measured f/sub T//f/sub max/ of 12/30 GHz and BV/sub CEO/ of over 25 V produces a Johnsons product well above 300 GHz /spl middot/V. This figure is currently the closest reported data to the Johnsons limit for lateral BJTs. This technology can easily be integrated with CMOS on SOI. Therefore, it is feasible to build fully complimentary bipolar and MOS transistors on a single SOI substrate to form a true complementary-BiCMOS process. This silicon-based lateral SOI-BJT technology is a promising candidate for realizing future RF SoC applications.     

Heterojunction tunnelling model for pnp and npn polysilicon emitter bipolar transistors

A new tunnelling model is described which treats the interfacial layer in a polysilicon emitter transistor as a wide bandgap semiconductor. Potential barriers are formed in the valence and conduction bands, the sizes of which vary with the dopant type and concentration in the interfacial layer.<>     

Horizontal current bipolar transistor (HCBT) process variations for future RF BiCMOS applications

Two different process designs of horizontal current bipolar transistor (HCBT) technology suitable for future RF BiCMOS circuits are presented. The active transistor region is built in the defect-free sidewall of 900-nm-wide n-hills on a [110] wafer. The collector n-hill region is partially etched at the extrinsic base-collector periphery, whereas the extrinsic base is self-protected, resulting in reduced collector-base capacitance (C/sub BC/) and minimized volume of the extrinsic regions. The effect of doping levels at different regions on the transistor performance is examined in the two process designs. The fabricated HCBTs exhibit cutoff frequencies (f/sub T/) from 19.2 to 25.6 GHz, maximum frequencies of oscillations (f/sub max/) from 32.2 to 39.6 GHz, and collector-emitter breakdown voltages (BV/sub CEO/) between 4 and 5.2 V, which are the highest f/sub T/ and the highest f/sub T//spl middot/BV/sub CEO/ product compared to existing silicon-on-insulator (SOI) lateral bipolar transistors (LBTs). The compact nature of the HCBT structure and low-cost technology make it suitable for integration with advanced pillar-like CMOS and SOI CMOS devices.     

Double-interdigitated (TIL) bipolar power transistors with lightlydoped collectors

The results of an investigation concerning the implementation of the two-interdigitation-level (TIL) concept in TO-3-packaged, triple-diffused bipolar power n-p-n transistors with lightly doped collector are discussed. It is demonstrated that the TIL concept, which offers a fair balance between manufacturability ease/cost effectiveness and overall electrical performances, allows for an increase of both the DC and small-signal current gains and the voltage ratings of bipolar transistors. The peculiarities of the ON-state current carrying mechanism in TIL-type transistors was investigated and its impact on device behavior was also assessed     

A low power dual-band multi-mode RF front-end for GNSS applications

A CMOS dual-band multi-mode RF front-end for the global navigation satellite system receivers of all GPS,Bei-Dou,Galileo and Glonass systems is presented.It consists of a reconfigurable low noise amplifier(LNA),a broadband active balun,a high linearity mixer and a bandgap reference(BGR) circuit.The effect of the input parasitic capacitance on the input impedance of the inductively degenerated common source LNA is analyzed in detail.By using two different LC networks at the input port and the switched cap...     

一个应用于卫星导航接收机的低功耗可配置双频多模射频前端

本文给出了一个应用于GPS、北斗、伽利略和Glonass四种卫星导航接收机的高性能双频多模射频前端。该射频前端主要包括有可配置的低噪声放大器、宽带有源单转双电路、高线性度的混频器和带隙基准电路。详细分析了寄生电容对源极电感负反馈低噪声放大器输入匹配的影响,通过在输入端使用两个不同的LC匹配网络和输出端使用开关电容的方法使低噪声放大器可以工作在1.2GHz和1.5GHz频带。同时使用混联的有源单转双电路在较大的带宽下仍能获得较好的平衡度。另外,混频器采用MGTR技术在低功耗的条件下来获得较高的线性度,并不恶化电路的其他性能。测试结果表明：在1227.6MHz和1557.42MHz频率下,噪声系数分别为2.1dB和2.0dB,增益分别为33.9dB和33.8dB,输入1dB压缩点分别0dBm和1dBm,在1.8V电源电压下功耗为16mW。     

Simulator-independent compact modeling of vertical npn transistors for ESD and RF circuit simulation

We present an easy-to-use, simulator-independent compact model of a vertical npn transistor suitable for ESD circuit simulation. In addition to including high-current and breakdown effects, we also model accurately the small-signal off-state impedance of the device using s-parameter measurements, for inclusion in RF circuit simulations. Experimental results are provided for silicon and SiGe npn transistors.     

Optimization of silicon bipolar transistors for high current gainat low temperatures

Bipolar transistors designed specifically for operation at liquid-nitrogen (LN₂) temperature are discussed. It is found that for high-gain LN₂ bipolar transistors, the emitter concentration should be around 5×10¹⁸ cm^-3. Compensating impurities in the base should be kept to minimum. Test bipolar transistors with polysilicon emitter contacts were fabricated using these criteria. The devices show very little current degradation between room temperature and 77 k. Polysilicon emitter contacts are also shown to be somewhat more effective at lower temperatures     

Heterogeneous InSb quantum well transistors on silicon for ultra-high speed, low power logic applications

The heterogeneous integration of InSb quantum well transistors onto silicon substrates is investigated for the first time. 85 nm gate length FETs with f_T = 305 GHz at V_ds = 0.5 V and DC performance suitable for digital logic are demonstrated on material with a buffer just 1.8 mum thick. An initial step towards integrating InSb FETs with mainstream Si CMOS for high-speed energy-efficient logic applications has been achieved.     

A novel self-aligned fabrication process for microwave static induction transistors in silicon carbide

A novel multiple-self-aligned fabrication process is developed for recessed gate microwave static induction transistors (SITs) in silicon carbide (SiC). This process is demonstrated by fabricating 4H-SiC SITs having record f/sub T/ of 7 GHz.     

III-V field-effect transistors for low power digital logic applications

Sustaining Moore’s Law of doubling CMOS transistor density every twenty four months will require not only shrinking the transistor dimensions, but also introduction of new materials and new device architectures to achieve the highest performance per watt of power dissipation. Compound semiconductor-based quantum-well field effect transistors have recently emerged as a promising transistor option for future ultra low-power logic applications. This paper reviews the opportunities and challenges in this exciting field of research.     

A new trench bipolar transistor for RF applications

A new vertical trench SiGe heterojunction bipolar transistor (HBT) is proposed that improves the tradeoff between the cutoff frequency (f/sub T/) and the off-state collector-base breakdown voltage (BV/sub cbo/). Extensive device simulations show that a record f/sub T//spl middot/BV/sub cbo/ product of about 2375 GHz/spl middot/V can be obtained for an HBT having a trench field plate connected to the emitter and a linearly graded doping profile in the collector drift region, while about 700 GHz/spl middot/V can be obtained for a standard optimized HBT. This large improvement is explained mainly by the suppression of the base-widening effect.     

A self-aligned short process for insulated-gate bipolar transistors

An n-channel vertical insulated-gate bipolar transistor (IGBT) process which implements a self-aligned p⁺ short inside the DMOS diffusion windows is proposed and demonstrated experimentally. The salient feature of the new process is the placement of a poly-Si plug to define the diffusion window of the p⁺ short. Similar forward conduction characteristics and tradeoffs with turn-off time were obtained for these self-aligned short IGBTs when compared to conventional IGBTs with non-self-aligned shorts. With a resistive load and no external gate resistor, dynamic latching current was seen to increase with increasing p⁺ diffusion depth and electron irradiation dosage, as well as with larger p⁺ diffusion windows     

New approach to the manufacturing of power microwave bipolar transistors: A computer simulation

A new manufacturing technology for power microwave silicon npn transistors is evaluated by 2D computer simulation in Silvaco’s SSUPREM4. It enables one to increase the effective emitter area, which makes for better power-handling and frequency capabilities, radiation hardness, and common-emitter output characteristics. Advantages of the new technology over the standard one are demonstrated.     

SiC and GaN transistors - is there one winner for microwave power applications?

Wide bandgap semiconductors show promise for high-power microwave electronic devices. Primarily due to low breakdown voltage, it has not been possible to design and fabricate solid-state transistors that can yield radio-frequency (RF) output power on the order of hundreds to thousands of watts. This has severely limited their use in power applications. Recent improvements in the growth of wide bandgap semiconductor materials, such as SiC and the GaN-based alloys, provide the opportunity to now design and fabricate microwave transistors that demonstrate performance previously available only from microwave tubes. The most promising electronic devices for fabrication in wide bandgap semiconductors for these applications are metal-semiconductor field-effect transistors (MESFETs) fabricated from the 4H-SiC polytype and heterojunction field-effect transistors (HFETs) fabricated using the AlGaN/GaN heterojunction. These devices can provide RF output power on the order of 5-6 W/mm and 10-12 W/mm of gate periphery, respectively. 4H-SiC MESFETs should produce useful performance at least through X band and AlGaN/GaN HFETs should produce useful performance well into the millimeter-wave region, and potentially as high as 100 GHz.     

A comparative study on the various monolithic low noise amplifiercircuit topologies for RF and microwave applications

This paper critically compares the various monolithic low noise amplifier (LNA) circuit topologies using BiCMOS or MESFET technologies for RF and microwave applications, in addition to the conventional techniques, five newly proposed schemes for the simultaneous noise and input power matching are extensively compared with each other at microwave frequencies. At L-band, the best scheme is found to be the proposed cascode inductive series feedback (CCSF) or common-source inductive series feedback (CSSL)+common-gate inductive parallel feedback (CGPF) when 0.5 μm GaAs MESFET is used, while it is cascode resistive parallel feedback (CCPF) when n-p-n BJT is used. At C- and X-bands, the proposed CGPF exhibits the best performance. Other than CGPF, the CSSL+CGPF seems to he the best at 6 GHz, and both CCPF+CGPF and CSSL+CGPF are recommended at 12 GHz. Finally, to verify the feasibility of this approach, a CCPF has been fabricated with 0.5 μm GaAs MMIC technology, of which measured results agree well with the simulated ones     

A self-alignment process for amorphous silicon thin film transistors

A new method of fabricating amorphous Si thin film transistors (a-Si TFT's) has been developed. This method uses the self-alignment process, which also includes the successive deposition of gate insulator and active amorphous Si layers in one-pumpdown time in an RF glow discharge apparatus. This method greatly simplifies the fabrication process and results in stable device performance. The practicability of this method was confirmed by experimentally fabricated devices.     

A transient model for insulated gate bipolar transistors (IGBTs)

In this paper, we present a physics-based model for the non punch-through (NPT) insulated gate bipolar transistor (IGBT) during transient turn off period. The steady state part of the model is derived from the solution of the ambipolar diffusion equation in the drift region of the NPT IGBT. The transient component of the model is based on the availability of a newly developed expression for the excess carrier concentration in the base. The transient voltage and current are obtained both numerically and analytically from this model. The theoretical predictions of both approaches are compared with experimental data and found to be in good agreement.