芯片级封装技术研究

对刚性基板倒装式和晶圆再分布式两种结构的CSP进行了研究，并描述了工艺流程。详细阐述了CSP的几项主要的关键技术：即结构设计技术，凸点制作技术，包封技术和测试技术。阐述了采用电镀和丝网漏印制备焊料凸点的方法。     

电镀技术在凸点制备工艺中的应用

简要回顾了微电子封装的发展历程;描述了FC、BGA、CSP以及WLP的基本概念;归纳了凸点类型以及各种凸点的不同用途;着重介绍了电镀金、金锡、锡铅、锡银和化学镀镍凸点的工艺过程,最后简单介绍了制备凸点的电镀设备。     

未来微处理器的封装技术—8新型无凸点叠层封装

无凸点叠层（BBUL）封装技术是Intel公司研制出的1种新型封装技术，用以满足未来微处理器封装技术的要求，这种BBUL封装技术具有巨大的优越性，它免除了大多数高性能的倒装芯片所用的大量焊料凸点互连，使环路电感量小，热机械应力小，不但减小芯片连接的寄生效应，而且提高了微处理器芯片的效率，此外，该封装的体积比传统封装更小，更轻，使多芯片之间的互连更为紧密，特别适合于高引出端的电子类及光电子产品，如逻辑单元，存储器，射频器件以及微型机电一体化系统。本主要从其发展背景，工艺及特性方面阐述这种新型BBUL封装技术，最后提出一些建议。     

一种新型的BBUL封装技术

无凸点叠层封装（BBUL）技术是Intel公司研制出的一种新型封装技术，用以满足未来微处理器封装技术的要求。这种BBUL封装技术具有巨大的优越性，它免除了大多数高性能的倒装芯片所用的大量焊料凸点和互连，使环路电感量小、热机械应力小，不但减小芯片连接的寄生效应，而且提高了微处理器芯片的效率。此外，该封装比传统封装更小、更轻，使多芯片之间的互连更为紧密，特别适合于高引出端的电子类及光电子产品，如逻辑单元、存储器、射频器件以及微型机电一体化系统。本文主要从其发展背景、工艺及特性方面来阐述这种新型的BBUL封装技术，最后提出一些建议。     

圆片级封装的无铅焊料凸点制作技术研究

对圆片级封装（WLP）的结构设计和关键工艺技术进行了研究；描述了凸点UBM层的选择，凸点回流技术以及凸点的质量控制技术；重点阐述了采用电镀来制作无铅焊料凸点的方法。     

圆片级封装的无铅焊料凸点制作技术研究

对圆片级封装(WLP)的结构设计和关键工艺技术进行了研究;描述了凸点下金属(UBM)层的选择,凸点回流技术,以及凸点的质量控制技术;重点阐述了采用电镀制作无铅焊料凸点的方法.     

芯片凸点植球技术

介绍了目前芯片封装过程中凸点的几种制造方法,重点介绍了凸点植球技术的发展现状．以及相关制造设备的情况。     

先进的芯片尺寸封装(CSP)技术

随着手机、掌上电脑、薄形笔记本等消费类电子产品的迅速发展,芯片尺寸封装技术(CSP)在我国从无到有,并在短短几年时间内取得了突飞猛进的发展。论述了芯片尺寸封装(CSP)的7大特点,总结了6大类别,归纳了主要生产制作工艺,并对我国芯片尺寸封装技术(CSP)的发展提出了几点建议。     

激光重熔在钎料凸点成形中的应用

激光由于具有高能量输入密度以及可局部加热的优点而在面阵列电子封装钎料凸点成形中具有潜在的优势，介绍了激光重熔在面阵列封装钎料凸点成形中的研究进展，并且对PBGA共晶钎料球激光重熔进行了工艺研究，研究结果表明；采用合适的激光输入能量可以在非常短的时间内获得表面质量光滑的钎料凸点。     

封装装配技术所用材料的无铅化

本文简要叙述了无铅化立法确定的最后期限、凸点成形工艺、晶圆片凸点成形电镀技术、凸点下金属化及可靠性问题和无铅化材料的发展方向。从而说明，通过漏印板印刷和电镀的晶圆片凸点形成技术事例，证明可靠的无铅化技术是适合的。     

Bump formation for flip chip and CSP by solder paste printing

Area array packages (flip chip, CSP and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment or are limited by the throughput, minimal pitch and yield the industry is currently searching for new and lower cost bumping approaches. In this paper the experimental work of stencil printing to create solder bumps for flip chip and wafer level CSP (CSP-WL) is described in detail.This paper is divided into two parts. In the first part of the paper a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless Nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented and the limits concerning pitch, reproducibility and bump height will be discussed in detail. The second part of the paper is focused on solder paste printing for wafer-level CSPs. In order to achieve large bumps an optimized printing method will be presented. Additionally advanced stencil design will be shown and the achieved results will be compared with conventional methods.     

Low cost bumping by stencil printing: process qualification for 200 μm pitch

Area array packages (flip chip, CSP (Chip scale packages) and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment and/or are limited by the throughput, minimal pitch and yield, the industry is currently searching for new and lower cost bumping approaches. The experimental work of stencil printing to create solder bumps for flip chip devices is described in detail in this article. In the first part of this article, a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented, and the limits concerning pitch, stencil design, reproducibility and bump height will be discussed in detail. In the second part, a comparison of measured standard deviations of bump heights as well as the quality demands for ultrafine pitch flip chip assembly are shown.     

C4NP-无铅倒装晶片焊凸形成生产工艺与可靠性数据

受控倒塌芯片连接新工艺是一种由IBM公司开发、由Suss Micro Tec公司推向商品化的新型焊凸形成技术。受控倒塌芯片连接新工艺采用各种无铅焊料合金致力于解决现有的凸台。形成技术限定,使低成本小节距焊凸形成成为可能。受控倒塌芯片连接新工艺是一种焊球转移技术,熔焊料被注入预先制成并可重复使用的玻璃模板(模具)。这种注满焊料的模具在焊料转入圆片之前先经过检查以确保高成品率。注满焊料的模具与圆片达到精确的接近后以与液态熔剂复杂性无关的简单工序转移在整个300mm(或300mm以下)圆片上。受控倒塌芯片连接新工艺技术能够在焊膏印刷中实现小节距凸台形成的同时提供相同合金选择的适应性。这种简单的受控倒塌芯片连接新工艺使低成本、高成品率以及快速封装周期的解决方法对于细节距FCiP以及WLCSP凸台形成均能适用。     

Single chip bumping and reliability for flip chip processes

Processes of bump deposition based on mechanical procedures together with their reliability data are summarized in this paper. The stud bumping of gold, palladium, and solder is described and also a novel bumping approach for fine pitch solder deposition down to 100 μm pitches using thermosonic bonding on a modified wedge–wedge bonding machine. This wedge bumping doesn’t require a wire flame-off process step. Because of this, no active atmosphere is necessary. The minimum pad diameter which can be bumped using the solder wedge bumping is 50 μm, up to now. This bumping process is highly reproducible and therefore well-suited for different flip chip soldering applications. Palladium stud bumps provide a solderable under bump metallization. Results from aging of lead/tin solder bumps on palladium are shown. The growth of intermetallics and its impact on the mechanical reliability are investigated.     

Squeegee bump technology

An innovative solder bumping technology, termed squeegee bumping, has been developed at Motorola's Interconnect Systems Laboratory that uses baked photoresist as a mask for solder printing to deposit fine pitch solder bumps on wafers. This process provides much better alignment accuracy and is capable of bumping finer pitch devices than stencil printing technology. Solder paste printing uses a screen printer similar to that used for stencil printing. Greater versatility of solder materials can be obtained through solder paste than the electroplating. Cost modeling shows that the squeegee bump technology has a significant cost benefit over controlled collapse chip connection (C4) technology. This is because the C4 process has very low efficiency in labor and materials usage. Statistical process control data show an average bump height of 118 ± 3.5 μm, and a maximum-to-minimum bump height range of 17 μm over a 150 mm-diameter wafer and have been produced repeatedly on test wafers with 210 μm peripheral pitch. A 109.6 ± 1.3 μm bump height on orthogonal array with 250 μm pitch has been successfully demonstrated with greater than 90% die yield. Bump reliability has been studied using both multiple reflows and extended thermal/humidity storage procedures. No degradation of shear strength was observed after up to 10 × reflows and 1008 h of a thermal/humidity stress environment. Bump reliability was also evaluated by assembling squeegee bumped dice on a plastic chip scale package (CSP). Liquid-to-liquid thermal shock cycling at a temperature range of -55°C to +125°C had a characteristic life of 2764 cycles with a 1st failure at 1050 cycles. No failures were observed after 432 h of autoclave stress at 121°C, 100% RH, 15 psig test condition     

Novel Bumping Material for Solder‐on‐Pad Technology

A novel bumping material, which is composed of a resin and Sn3Ag0.5Cu (SAC305) solder power, has been developed for the maskless solder‐on‐pad technology of the fine‐pitch flip‐chip bonding. The functions of the resin are carrying solder powder and deoxidizing the oxide layer on the solder power for the bumping on the pad on the substrate. At the same time, it was designed to have minimal chemical reactions within the resin so that the cleaning process after the bumping on the pad can be achieved. With this material, the solder bump array was successfully formed with pitch of 150 µm in one direction.     

Novel Bumping and Underfill Technologies for 3D IC Integration

In previous work, novel maskless bumping and no‐flow underfill technologies for three‐dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low‐volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no‐flow underfill material named “fluxing underfill” is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two‐tier stacked TSV chips are sucessfully stacked.     

CBGA植球工艺成熟度提升方法的研究

随着陶瓷球栅阵列(CBGA)封装形式产品被广泛应用,对其植球工艺质量的可靠性和一致性要求也越来越严格,焊球的位置度是检验CBGA产品质量的重要参数之一,其直接影响该产品表面贴装的质量和可靠性。以CBGA256产品为例,针对CBGA产品在批生产过程中出现的局部助焊剂聚集而引起焊球位置偏移的问题,通过对陶瓷外壳质量、焊膏印刷工艺和回流焊工艺的研究,优化CBGA产品的植球工艺,解决局部焊球位置度较差的问题,进而提高产品的一致性和可靠性,提升CBGA植球工艺的成熟度。     

Prediction of Solder Bump Formation in Solder Jet Packaging Process

Precise solder bump shape prediction is crucial for the application of the solder jet bumping process to microelectronic component packaging. In the present study, numerical simulation of both the dynamics and phase change responses during a metal droplet impingement is conducted by introducing a nonconstant interfacial heat transfer coefficient, which varies with time and position. Comparison between the numerical and experimental results for a large metal droplet demonstrates the validity of the numerical method. The results of many simulation cases are presented corresponding to typical solder jet bumping conditions. Variations in the impact velocity, initial droplet size, and droplet temperature and substrate temperature are investigated to understand their impact on the formation of solder bumps.