深亚微米MOSFET衬底电流的模拟与分析

利用器件模拟手段对深亚微米ＭＯＳＦＥＴ的衬底电流进行了研究和分析，给出了有效的道长度，栅氧厚度，源漏结深，衬底掺杂浓度以及电源电压对深亚微米ＭＯＳＦＥＴ衬底电流的影响，发现电源电压对深亚微米ＭＯＳＦＥＴ的衬底电流有着强烈的影响，热载流子效应随电源电压的降低而迅速减小，当电源电压降低到一定程度时，热载流子效应不再成为影响深亚微米ＭＯＳ电路可靠性的主要问题。     

衬底正偏的MOSFET的近似模型

本文针对衬底正偏的ＭＯＳＦＥＴ的解析模型进行了讨论．在已有ＭＯＳＦＥＴ理论基础上，仅引入一个参数ξ，便得到了全偏压范围的ＭＯＳＦＥＴ的解析表达式的通式．当ξ＝１时，该表达式与已知的衬底负偏的ＭＯＳＦＥＴ的表达式相同；当ξ＝０．８时，可得到衬底正偏的ＭＯＳＦＥＴ的近似解析式．实验结果验证了该模型的正确性．     

NMOS低温热载流子晶体管的解析研究

利用低温（７７－２９５Ｋ）短沟ＮＭＯＳＦＥＴ准二维解析模型，研究了７７－２９５Ｋ温区ＮＭＯＳＦＥＴ衬底电流相关的物理机制。发现沟道电子平均自由程不随温度而改变，其值约为７．６ｎｍ；低温下虽然沟道电子在漏端获得较高的能量，但由于碰撞电离减弱，使ＮＭＯＳＦＥＴ的衬底电流不随温度降低而显著增长。实验结果证明，提出的衬底电流机制和模型适用于７７－２９５Ｋ宽温区范围。     

MOSFET衬底电流模型及参数提取

在短沟道ＭＯＳＦＥＴ器件物理的基础上,导出了其衬底电流解析模型,并通过实验进行了模型参数提取。模型输出与短沟ＭＯＳＦＥＴ实测结果比较接近,可应用于ＶＬＳＩ／ＵＬＳＩ可靠性模拟与监测研究和亚微米ＣＭＯＳ电路设计。     

适合于PSPICE的一种精确的功率MOSFET等效电路

建立了一种新的功率ＭＯＳＦＥＴ等效电路，以便利用先进的电路模拟软件ＰＳＰＩＣＥ对功率ＭＯＳＦＥＴ所有特性进行模拟和分析．对ＩＲ公司的各类ＨＥＸＦＥＴ进行的模拟结果与其数据手册中的实验曲线十分吻合，表明该模型具有较高的精确性．     

MOSFET栅电流分布的理论建模

小尺寸ＭＯＳＦＥＴ的强场性,场畸变性和漏区尺度比例的增大,使它的分布效应增强,更准确地描述小尺寸器件的栅电流需要分布模型。本文依据“幸运电子”概念,基于我们已创建的沟道和衬底电流的二维分布模型,建立了ＮＭＯＳＦＥＴ的电子和空穴栅电流的分布模型,空穴栅电流的分布模型是基于负纵向场加速的新的发射物理过程建立的,所建分布模型包含了更祥尽的热载流子向栅发射的物理过程,这将有利于ＭＯＳＦＥＴ热载流子的损伤的     

低通滤波器结构的改进分析及模拟

在高频域，ＭＯＳＦＥＴ的分布参数对全集成ＭＯＳＦＥＴ－Ｃ滤波器的特性有很大影响，本文应用ＳＰＩＣＥ（Ⅱ）通用模拟电路程序，采用非理想运算放大器单极点电路模型，考虑到ＭＯＳＦＥＴ的寄生电容，对一个六阶切比雪夫低通滤波器全ＭＯＳＦＥＴ－Ｃ平衡结构应用传输线模型进行了仿真分析。     

MOSFET－C滤波电路TT平衡结构的CCⅡ±实现及仿真

本文提出了全集成ＭＯＳＦＥＴ电流传输器ＣＣⅡ±为基础的平衡结构积分器，并对其消除非线性因素进行了理论分析。同时提出了以全集成ＭＯＳＦＥＴ电流传输器ＣＣⅡ±为基本电路元件的有源ＲＣＴＴ滤波器平衡模式，并利用ＳＰＩＣＥ（Ⅱ）通用模拟电路程序，对全集成ＭＯＳＦＥＴ－Ｃ平衡结构精确连续时间二阶滤波器输出电压幅频特性进行了仿真分析。     

0．1μm NMOSFET沟道δ－掺杂与结构特性

沟道δ－形掺杂对于改善极小尺寸ＭＯＳＦＥＴ性能、提高可靠性极其重要。利用能量输运模型（ＥＴＭ），报道了沟道δ－形掺杂分布对０．１μｍ沟长ＮＭＯＳＦＥＴ结构特性的影响，根据漏源电流ＩＤＳ、截止态电流Ｉｏｆｆ、阈值电压ＶＴＨ和Ｓ因子的要求，提出了使性能和可靠性得到优化的δ－形掺杂分布。     

深亚微米PESD MOSFET特性研究及优化设计

本文对多晶抬高源漏（ＰＥＳＤ）ＭＯＳＦＥＴ的结构作了描述，并对深亚微米ＰＥＳＤＭＯＳ－ＦＥＴ的特性进行了模拟和研究，看到ＰＥＳＤＭＯＳＦＥＴ具有比较好的短沟道特性和亚阈值特性，其输出电流和跨导较大，且对热载流子效应的抑制能力较强，因此具有比较好的性能．给出了ＰＥＳＤＭＯＳＦＥＴ的优化设计方法．当ＭＯＳＦＥＴ尺寸缩小到深亚微米范围时，ＰＥＳＤＭＯＳ－ＦＥＴ将成为一种较为理想的器件结构     

MOSFET substrate current model including energy transport

A new MOSFET substrate current model, incorporating energy transport, is proposed. It was found that a non-steady-state electron transport effect and two effects attributed to electron pressure are essential to calculate the substrate current characteristics accurately. The predictions from the present model compare favorably with the experimental data for MOSFET's with effective channel length down to 0.45 µm.     

A model for the relation between substrate and gate currents in n-channel MOSFET's

The gate current in n-channel MOSFET's normalized to the source current is expressed as a function of the substrate current normalized to the source current by means of an impact ionization model. The ratio of the electron mean free path for impact ionization to that for optical phonon scattering, which is the most important among the various related device parameters, is determined by indirect measurement of the gate current using stacked-gate MOSFET's. The present model has been applied to interpret the experimental results obtained from samples with a variety of device dimensions. Limitation by the hot-electron emission, which is an important design constraint for submicrometer-gate MOS devices, is studied for single-gate and stacked-gate MOSFET's in comparison with other limiting factors.     

Lucky-electron model of channel hot-electron injection in MOSFET'S

The lucky-electron concept is successfully applied to the modeling of channel hot-electron injection in n-channel MOSFET's, although the result can be interpreted in terms of electron temperature as well. This results in a relatively simple expression that can quantitatively predict channel hot-electron injection current in MOSFET's. The model is compared with measurements on a series of n-channel MOSFET's and good agreement is achieved. In the process, new values for many physical parameters such as hot-electron scattering mean-free-path, impact-ionization energy are determined. Of perhaps even greater practical significance is the quantitative correlation between the gate current and the substrate current that this model suggests.     

An analytical breakdown model for short-channel MOSFET's

Avalanche-induced breakdown mechanisms for short-channel MOSFET's are discussed. A simple analytical model that combines the effects due to the ohmic drop caused by the substrate current and the positive feedback effect of the substrate lateral bipolar transistor is proposed. It is shown that two conditions must be satisfied before breakdown will occur. One is the emission of minority carriers into the substrate from the source junction, the other is sufficient avalanche multiplication to cause significant positive feedback. Analytical theory has been developed with the use of a published model for short-channel MOSFET's. The calculated breakdown characteristics agree well with experiments for a wide range of processing parameters and geometries.     

Correlation between substrate and gate currents in MOSFET's

A correlation between substrate and gate currents in MOSFET's is described and analyzed. Both of these currents are the result of hot-electron mechanisms. Theory for these mechanisms has been applied to derive an expression for gate current in terms of substrate current and parameters that can be calculated from processing data and bias conditions. The theory is successfully applied to a series of n-channel MOSFET's with a range of geometries and bias values.     

A new approach to modeling the substrate current of pre-stressedand post-stressed MOSFET's

In this paper, we propose a closed form expression of a new and accurate analytical substrate current model for both pre-stressed and post-stressed MOSFET's. It was derived based on the concept of effective electric field, which gives a more reasonable impact ionization rate in the lucky-electron model. This effective electric field, composed by two experimentally determined parameters, can be regarded as a result of nonlocal heating effects within devices. This model shows a significant improvement to the conventional local field model. One salient feature of the present model is that it allows us to characterize the time evolution of the substrate current of stressed MOSFET's for the first time. Experimental verification for a wide variety of MOSFET's with effective channel lengths down to 0.3 μm shows that the new model is very accurate and is feasible for any kind of MOS device with different drain structures. The present model can be applied to explore the hot carrier effect in designing submicrometer MOS devices with emphasis on the design optimization of a device drain engineering issue. In addition, the present model is well suited for device reliability analysis and circuit level simulations     

Verification of saturation velocity lowering in MOSFET's inversionlayer

With reduction of the MOSFET's channel length L, the drain saturation current of MOSFET's is determined by the saturation velocity v_sat in the inversion layer. Hence, the modeling of v_sat becomes very important. In this paper, v_sat in the inversion layer has been examined by using simulation experiment. New parameter values for v_sat model in the inversion layer are proposed. In order to verify the v_sat model, the impurity profiles of MOSFET's are calibrated to fit the threshold voltage V_th-L characteristics. Then, we validate new v_sat model by comparing the experiments of I_D-V_D characteristics of 0.35-μm CMOS with the simulations using the energy transport model (ETM)     

Design of ion-implanted MOSFET's with very small physical dimensions

This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation, to provide shallow source and drain regions and a nonuniform substrate doping profile. One-dimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFET's with channel lengths as short as 0.5 /spl mu/ were fabricated, and the device characteristics measured and compared with predicted values. The performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected.     

A numerical model of avalanche breakdown in MOSFET's

An accurate numerical model of avalanche breakdown in MOSFET's is presented. Features of this model are a) use of an accurate electric-field distribution calculated by a two-dimensional numerical analysis, b) introduction of multiplication factors for a high-field path and the channel current path, and c) incorporation of the feedback effect of the excess substrate current induced by impact ionization into the two-dimensional calculation. This model is applied to normal breakdown observed in p-MOSFET's and to negative-resistance breakdown (snap-back or switchback breakdown) observed in short-channel n-MOSFET's. Excess substrate current generated from channel current by impact ionization causes a significant voltage drop across the substrate resistance in short-channel n-MOSFET's. This voltage forward-biases the source-substrate junction and increases channel current causing a positive feedback effect. This results in a decrease of the breakdown voltage and leads to negative-resistance characteristics. Current-voltage characteristics calculated by the present model agree very well with experimental results. Another model, highly simplified and convenient for device design, is also presented. It predicts some advantages of p-MOSFET's over n-MOSFET's from the standpoint of avalanche breakdown voltage, particularly in the submicrometer channel-length range.     

New experimental findings on hot carrier effects in sub-0.1 μmMOSFET's

The behaviors of the substrate current and the impact ionization rate are investigated for deep submicron devices in a wide temperature range. New important features are shown for the variations of the maximum substrate current as a function of applied biases and temperature. It is found that the gate voltage V_gmax, corresponding to the maximum impact ionization current conditions, is quasi-constant as a Function of the drain bias for sub-0.1 μm MOSFET's in the room temperature range. At low temperature, a substantial increase of V_gmax is observed when the drain voltage is reduced. It is also shown that, although a significant enhancement of hot carrier effects is observed by scaling down the devices, a strong reduction of the impact ionization rate is obtained for sub-0.1 μm MOSFET's operated at liquid nitrogen temperature in the low drain voltage range