A methodology for measuring the gate-drain capacitance of CMOSdevices

In this paper, the author presents a new methodology for measuring the gate drain capacitance of CMOS devices using an accelerated dc measurement scheme. The gate-drain capacitance was measured using a floating gate MOS transistor, i.e., an MOS transistor with an additional capacitor placed in series with the gate oxide capacitance. This was implemented within a standard p-well CMOS process using two matched transistors. The top capacitance couples charge onto the gate oxide capacitor and the gate-drain capacitor. The amount of coupling is determined by the ratio of these two capacitors     

Characterization of polysilicon-gate depletion in MOS structures

This paper presents a new technique to characterize the depletion capacitance and (active) impurity concentration of gate polysilicon in MOS transistors. The method has been validated by means of 2-D simulation; experimental results obtained with state-of-the-art n-channel 0.5 micrometer transistors are presented     

Parasitic resistance in an MOS transistor used as on-chipdecoupling capacitance

Adding on-chip decoupling capacitance has become a popular method to reduce dI/dt noise in integrated circuits. The most area-efficient realization of on-chip capacitance in a standard CMOS process is to use the gate capacitance of MOS transistors. In this paper, the inevitable parasitic resistance of an MOS transistor is estimated, which is important for two reasons. The resistive noise caused by this parasitic must be kept low, and, if properly sized, this resistance can be used to dampen potential resonance oscillations     

New method for threshold voltage extraction of high-voltage MOSFETs based on gate-to-drain capacitance measurement

This letter reports on the extraction of the threshold voltage of laterally diffused MOS transistors. A clear analysis of the device physics is performed, highlighting the correlation between the change of the electron charge distribution along the channel and the device capacitance variations when the gate voltage is swept. Using numerical simulations, it is shown that the peak of the gate-to-drain capacitance is related to the transition of the surface from weak to moderate inversion in the intrinsic MOS transistor at the location of the maximum doping concentration, which corresponds to the threshold voltage of the device according to the MOS theory. Comparison between conventional I/sub D///spl radic/g/sub m/ extraction and the new proposed capacitance peak method is performed on both technology computer-aided design simulations and measurements in order to confirm the new experimental technique and related theory.     

Wafer-chip assembly for large-scale integration

A technique has been developed for achieving a very high density interconnection of active silicon devices to permit the fabrication of large electronic subsystems in essentially monolithic form. The technique has been used to assemble a MOS 2000-bit shift register containing 12 000 MOS transistors on a 300 by 600 mils silicon substrate. The register utilizes ten 200-bit shift-register chips, each containing 1200 transistors. Four-phase MOS logic techniques are used to obtain very low power (0.1 mW/bit) and/or high frequency (10 MHZ) operation. In the technique used to assemble the 2000-bit shift register, silicon large-scale array chips are face-down bonded in adjoining positions on a larger silicon wafer section which may contain additional layers of interconnections and/or active devices as required to form a complete system subassembly. Since the same photoengraving technology is used in the substrate as on the chips, very high packing densities can be achieved, with minimum chip area required for interconnections. This approach also minimizes the parasitic capacitance associated with more conventional techniques for encapsulating and interconnecting large-scale arrays. In the case of MOS circuits, large area-buffer devices are not needed due to the small capacitance in the wafer-chip interconnections. Various techniques have been evolved for processing the chips and substrates produce contact regions which permit the required high fabrication yields. The bonding conditions and metallurgical systems used to date in fabricating large shift-register assemblies will be described and compared with other approaches.     

Transistor design for low distortion at high frequencies

The design of high-frequency bipolar transistors with very low distortion is described. Simple expressions for distortion are used to select device parameters for the optimization of distortion performance. The effect of epitaxial-layer characteristics on device performance is considered in detail, and the importance of collector depletion in achieving low distortion is shown. The influence of device geometry on distortion is considered, and the degradation caused by MOS capacitance is illustrated.     

Very low-voltage analog signal processing based on quasi-floating gate transistors

A novel design principle for very low-voltage analog signal processing in CMOS technologies is presented. It is based on the use of quasi-floating gate (QFG) MOS transistors. Similar to multiple input floating gate (MIFG) MOS transistors, a weighted averaging of the inputs accurately controlled by capacitance ratios can be obtained, which is the basic operating principle. Nevertheless, issues often encountered in MIFG structures, such as the initial charge trapped in the floating gates or the gain-bandwidth product degradation, are not present in QFG configurations. Several CMOS circuit realizations using open- and closed-loop topologies, have been designed. They include analog switches, mixers, programmable-gain amplifiers, track and hold circuits, and digital-to-analog converters. All these circuits have been experimentally verified, confirming the usefulness of the proposed technique for very low-voltage applications.     

Study of the input and reverse transfer capacitance of vertical MOS transistors

The input capacitance of vertical MOS transistors shows, when it is measured in the current flow state, much higher values than in the currentless state (V_{GS} = 0). This can partly be attributed to the Miller-effect with the internal drain series resistance of the epitaxial layer working as a load resistance. Moreover there is an additional increase of the reverse transfer capacitance by more than an order of magnitude because of accumulation beneath the gate. This effect more or less depends on the current according to the epi-doping, and it occurs especially on transition from the linear to the pentode region. Measurements of the input and computed values of the reverse tranfer capacitance and its dependence on current will be presented for transistors with different dopings and heights of the epitaxial layer.     

Modeling and optimization of fringe capacitance of nanoscale DGMOS devices

We analyze the impact of gate electrode thickness and gate underlap on the fringe capacitance of nanoscale double-gate MOS (DGMOS) transistors. We propose an analytical fringe capacitance model considering gate underlap and finite source/drain length. A comparison with the simulation results show that the model can accurately estimate the fringe capacitance of the device. We show that an optimum gate underlap can significantly reduce the fringe capacitance resulting in higher performance and lower power consumption. Also, the effects of process variation in gate underlap devices are discussed. Simulation results on a three-stage ring oscillator show that with optimum gate underlap 32% improvement in delay can be achieved.     

Electrical characterization of feature sizes and parasitic capacitances using a single test structure

Commonly, transistor characteristics, feature sizes, and interfaces as well as oxide quality of MOS transistors are measured on different test patterns. For short-channel devices this can lead to wrong interpretations because the various parameters strongly depend on each other. The present paper describes capacitance measurements which allow the determination of relevant parameters by using only a single multitransistor test structure. The method is very accurate and simple and can be used for device and process characterization.     

Impact of tunnel currents and channel resistance on thecharacterization of channel inversion layer charge and polysilicon-gatedepletion of sub-20-Å gate oxide MOSFETs

This paper discusses the limitations on MOSFET test structures used in extracting the polysilicon gate doping from capacitance-voltage (C-V) analysis in strong inversion, especially for ultrathin gate oxides. It is shown that for sub-20-Å oxide MOS devices, transistors with channel lengths less than about 10 μm will be needed to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length has been estimated using a new simple transmission-line-model of the terminal capacitance, which accounts for the nonnegligible gate tunneling current and finite channel resistance     

Analysis of quantum effects in nonuniformly doped MOS structures

This paper presents results from the self-consistent solution of Schrodinger and Poisson equations obtained in one-dimensional (1-D) nonuniformly doped MOS structures suitable for the fabrication of very short transistors. Different issues are considered and investigated, including quantum-induced threshold voltage shifts, low-field electron effective mobility and gate-to-channel capacitance. The reported results give indications for the optimization of n-MOS channel doping profiles suitable for the fabrication of ultrashort MOSFETs     

A new AC technique for accurate determination of channel charge and mobility in very thin gate MOSFET's

A new method is described for determining the channel charge and mobility of a MOS transistor as a function of gate bias from the ac admittance measurements. The admittance of the conduction channel of the MOSFET is derived from a transmission line model. The peaks of theG/omegaversus ω curves are used to deduce gate-channel capacitance and mobility. The mobile carrier density and mobility in very thin-oxide MOSFET's can be measured more accurately using this ac method, since a zero lateral field and a uniform mobile charge distribution along the channel is maintained with zero drain-source voltage and interface trap effects are reduced by using high test frequencies. Measured data on the electron mobility versus gate voltage are presented for 90-A gate dielectric MOS transistors.     

A self-scanned image sensor employing MOS structure

Studies were carried out on a self-scanned image sensor comprising a linear integrated-circuit array of photodiodes and metal-oxide-semiconductor (MOS) transistors. It was found that the maximum scanning rate is about 2.5×10⁵bits/s, and that the value is mainly restricted by the photo-induced current and the junction capacitance of the photodiode.     

On the temperature dependence of subthreshold currents in MOS electron inversion layers

It has been observed that the “n” factor which enters into the exponential dependence of drain current on gate voltage for MOS transistors operating in the weak inversion region, exhibits a significant temperature dependence. This effect is correlated with the increase of interface state density towards the band edges and the variation of the space-charge capacitance.     

Capacitorless digitally programmable fractional-order filters

Novel topologies of fractional-order filters, implemented using the internal gate-source capacitance of MOS transistors, are introduced in this paper. This has been achieved using current-mirrors as active elements, resulting into resistorless realizations due to the employment of the small-signal transconductance parameter of the MOS transistor. This also offers the capability for electronic tuning of the frequency characteristics of the derived filter structures. The evaluation of the proposed technique has been performed through the design of a generalized fractional-order filter, which is also digitally programmed in such way that the four standard filter functions are offered. The behavior of the filter has been evaluated using the Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35 μm CMOS process.     

Inversion charge modeling

A simple, implicit, relation for the inversion charge density in the channel of metal oxide semiconductor (MOS) transistors is presented. The relation is continuous and covers the whole operating range, from subthreshold to strong inversion. The derivative of the local inversion charge density with respect to the channel voltage is a simple expression in the charge density, leading to analytic integrals as required for obtaining the drain current and the capacitance coefficients     

Study of the influence of design-technological factors on the conductivity and breakdown voltage of lateral double-diffused MOS transistors using numerical simulation

The influence of design-technological factors on lateral double-diffused MOS transistors is studied. The results of numerical simulation of lateral double-diffused MOS transistors are presented.     

Concepts of gain at an oxide-semiconductor interface and their application to the TETRAN—A tunnel emitter transistor—And to the MIS switching device

The idea of current gain at an insulator interface is discussed using the tunnel-oxide as an example upon which to base calculations. A novel approach to the calculation of tunnel components is introduced which accurately describes the electron tunnel component when the metal Fermi level is both above and below the semiconductor conduction band edge. A new form of bipolar amplifier (the TETRAN) is proposed and its performance is compared from a logic and memory point of view with existing transistors. As a logic element the device does not perform well when compared with MOS transistors because the current densities that one can obtain are too low to charge the relatively large tunnel-oxide capacitance. For the memory comparison, the concepts of gain necessary for TETRAN operation are applied to the MIS switching device. Preliminary experimental verification of the concept is reported.