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A/D转换器在航空航天系统中的重要元器件,随着器件转换时钟频率不断提高而其工作环境不断恶化,如何准确测试其时间参数对于全面评价A/D转换器性能特别重要。目前对于高速A/D转换器时间参数测试,主流方法是通过示波器直接测试其输出,该方法对于示波器采样速度要求比较高。文章提出一种高速A/D转换器时域重构技术,可以通过计算机数字信号处理方法来实现高速A/D转换器时间参数测试,同时避免对示波器采样速度的依赖。同时,在研究高速A/D转换器时域重构技术方法及其应用的基础上,通过了相关试验验证。 相似文献
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介绍了一种使用调制器回路的前反馈补偿技术,以提高转换器的分辨率,从而大大降低了高位A/D转换器电路结构的复杂程度,为开发高精度A/D转换器提供了一条新的途径。. 相似文献
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以SAD08328位串行输出A.D转换器为例,验证了一种串行输出A/D转换器的特殊测试方法。详细介绍了诸如转换精度,三态特性等主要参数的测试方法和测试线路。测试结果表明,该测试方法完全满足串行输出A/D转换器的测试精度要求。 相似文献
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A/D转换器是数字电路教学中的重要内容,本文阐述了如何利用Multisim12软件实现对并行比较型和逐次比较型的分立元件转换器的仿真,并对其传输时间,精确度等电气特性进行测试和进行比较.学生通过这样的仿真测量,能够方便地理解A/D转换器的原理和特点,对数字电路的学习大有帮助. 相似文献
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高速A/D转换器是数字化接收机系统的重要组成部分。本文从系统的角度分析了A/D数字模块对接收机灵敏度、动态范围的影响,结合实际宽带数字接收系统进行了设计实现并给出了指标测试方法。 相似文献
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本文从D/A与A/D转换器的基本概念和制造技术着手概述,特别对D/A和A/D转换器的应用之主要选择因素,进行了着重说明。随后,提出了D/A和A/D转换器优化品种的原则意见。 相似文献
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A/D转换器(ADC)的校准技术是提高高性能ADC转换精度的必要手段,它分为模拟校准技术和数字校准技术。数字校准技术较之模拟校准技术更为有效和更具灵活性。数字校准技术是在数字域进行错误代码计算,减轻了对模拟电路的精度要求。在主流制造工艺小尺寸化的趋势之下,许多创新的校准技术得到发展,并广泛应用于包括射频直接采样ADC在内的高速高精度ADC中。本文在分析最新的高速高精度ADC中采用的主要校准技术的基础上,重点研究了几种高采样率高精度ADC所采用的校准技术,侧重分析了数字校准技术。 相似文献
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微小井眼钻井技术是国外近年来发展起来一种前沿技术,具有成本低、安全环保和勘探开发效率高等特点.通过A/D、D/A转换器将井下模拟信号转换为数字信号,经处理后,将数字信号在转换成模拟信号去控制设备,实现井下的采集、通讯、控制任务.本文通过提出A/D转换器的选型原则,综合考虑性能参数、数字接口、原理结构、工作温度等各个方面,选择出适合随钻测量短节设计的A/D转换器,保证井下系统数据采集过程的稳定,对整个微小井眼钻井设备具有重要的作用. 相似文献
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Teck Seng Low Chao Bi 《Industrial Electronics, IEEE Transactions on》1996,43(1):184-191
A methodology for designing analog to digital (A/D) converters based on a hierarchic network is explored. The principle of this methodology and design procedure are presented. The characteristics and performances of the converter are compared with the converter based on the Hopfield network. Two circuit models for the A/D converters are described in this paper. As a hierarchic network is used, the A/D converters designed have no local minima in their operation, With the method proposed in the paper, high bit number A/D converters can be easily designed, and the converters designed are fast in signal conversion and stable in operation 相似文献
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高速A/D转换器的研究进展及发展趋势 总被引:1,自引:0,他引:1
介绍了高速高精度A/D转换器技术的发展情况、A/D转换器的关键指标和关键技术考虑;阐述了高速高精度A/D转换器的结构和工艺特点;讨论了高速高精度A/D转换器的发展趋势. 相似文献
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首先分别介绍了当前六大模数转换技术的工作原理、电路结构、性能特点及应用领域,通过从转换速率、转换精度、分辨率、功耗、价格、面积等指标进行分析,将物理结构的设计与实际性能结合比较,总结出各自适合的应用领域.然后,根据对现有模数转换技术特点的分析及实际应用中对模数转换器性能的要求,对当前A/D转换技术向着高性能、低功耗、结构简单方向发展的趋势进行了预测. 相似文献
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A fully digital built-in self-test (BIST) for analog-to-digital converters is presented in this paper. This test circuit is capable of measuring the DNL, INL, offset error and gain error, and mainly consists of several registers and some digital subtracters. The main advantage of this BIST is the ability to test DNL and INL for all codes in the digital domain, which in turn eliminates the necessity of calibration. On the other hand, some parts of the analog-to-digital converter with minor modifications are used in the BIST simultaneously. This also reduces the area overhead and the cost of the test. The proposed BIST structure presents a compromise between test accuracy, area overhead and test cost. The BIST circuitry has been designed using Mitel CMOS 1.5 μm technology. The simulation results of the test show that it can be applied to medium resolution analog-to-digital converters or high resolution pipelined analog-to-digital converters. The presented BIST shows satisfactory results for a nine-bit pipe-lined analog-to-digital converter. 相似文献
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Digital decimation filters are used in delta-sigma analogue-to-digital converters to reduce the oversampled data rate to the final Nyquist rate. This paper presents the design and implementation of a fully synthesised digital decimation filter that provides a time-to-market advantage. The filter consists of a cascaded integrator-comb filter and two cascaded half-band FIR filters. A canonical signed-digit representation of the filter coefficients is used to minimise the area and to reduce the hardware complexity of the multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated by using 0.25-μm CMOS technology with an active area of 1.36 mm2 and shows 4.4 mW power consumption at a clock rate of 2.8224 MHz. Experimental results show that this digital decimation filter is suitable for use in oversampled data converters and can be applied to new processes requiring a fast redesign time. This is possible because the filter does not have process-dependent ROM or RAM circuits. 相似文献
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分析了流水线A/D转换器采样电容与反馈电容之间的增益失配,探究了运放有限增益与流水线残差输出及A/D转换器输出的关系,建立了精确的系统模型。通过建立14位流水线A/D转换器Verilog-A的行为级模型,在数字域对流水线A/D转换器输出数字码进行分段平移。在第一级级间增益误差达到±0.012 5时,校正前信噪比仅为62 dB,校正后信噪比提升到85 dB。提出的校正方法可有效补偿由流水线级间增益导致的数字输出不连续和线性度下降。 相似文献
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Lee G.S. Peterson D.A. 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》1989,77(8):1264-1273
A number of superconductive A/D (analog/digital) converter designs that show promise for superiority in high-bandwidth or high-resolution applications are known. On the high-resolution side, counting-type converters appear quite attractive. Voltage-to-frequency and tracking A/D converters are reviewed in this category. On the ultra-high-bandwidth side (greater than about 1 GHz) the parallel-type A/D converters seem to be advantageous. A number of parallel periodic-threshold A/D converters that have been attempted over the years as well as a fully parallel (2N-1 comparators) A/D converter are reviewed 相似文献