A pre-silicon logic level security verification flow for higher-order masking schemes against glitches on FPGAs

Higher-order masking schemes have been proven in theory to be secure countermeasures against side-channel attacks in the algorithm level. The ISW framework is one of the most acceptable secure models of the existing higher-order masking schemes. However, a gap may exist between scheme and implementation. Several analyses have exhibited the weakness of masking in hardware designs on FPGAs. Firstly, we give the definition of leakage point and introduce three implementation logical flaws: glitch, EDA optimization and intermediate variable of scheme flaw. Secondly, we propose a leakage verification flow for implementing and verifying circuits realized higher-order masking schemes to avoid these leakage points. The flow provides an efficient evaluation method to locate and identify leakage points in masking hardware implementations. With the knowledge of the weaknesses of implementation, the implementation should be modified by corresponding methods to fix flaws, especially for glitch, which has been regarded as the main challenge of masking in hardware designs, we provide a method to remove the leakage point using Dijkstra algorithm with no extra time and area overheads. Finally, the design flow is evaluated on the implementation of Rivain&Prouff masking. Our experiments demonstrate how it automatically locates and protects the implementation. In addition, the experiments are also performed on flawed implementations due to EDA optimization and intermediate variables.     

Universal sequential logic elements

Feedback is applied to combinationally universal elements and the universal nature of the resulting sequential circuits is examined. For a certain balance of internal states to input symbols, the system may be made to behave as any sequential machine of such states. Also, the variable-structure nature of autonomous versions of the scheme may be used in list-processing storage.     

Modular single-stage universal logic gate

First and second generation universal logic gate (ULG):IC's are described. The ULG comprises one-stage arrays of two identical cascade circuits. These ULG's are shown to realize all logic functions of four (and fewer) input variables in approximately the same propagation delay as a single ECL current switch emitter follower (CSEF) gate fabricated with the same processing technology. Substantial power and power-delay product advantages relative to CSEF arrays are demonstrated at comparable silicon area for realization of all four-input functions. The ULG was developed for implementing logic arrays with a minimum number of gating stages.     

All-optical integrated micro logic gate

In this paper we present a novel approach for realizing an integrated all-optical logic gate. The basic principle is based upon stimulated emission process generated in an active gain medium while special interferometric photonic wave-guiding structure allows the realization of an integrated micro scale device. The operation rate of the proposed device structure can theoretically reach tens of Tera-Hertz.     

可编程光学二值双轨逻辑门

基于双轨逻辑,本文提出一种可级联的并行二值逻辑门。所有十六种二值逻辑运算可以采用偏振半波相延编程来实现。也提出了用电光晶体实现实时编程的方法。本文中给出了实验结果。     

GaAs capacitively coupled domino logic gate

A novel GaAs capacitively coupled domino logic (CCDL) gate is proposed. Derived from capacitor-coupled logic, this domino gate offers complex gate design capability with relatively low power dissipation and high speed, making it suitable for VLSI implementations.<>     

Design of CNTFET-based reconfigurable logic gate

Described is a dynamically reconfigurable 8-function logic gate with seven double-gate carbon nanotube field-effect transistors which demonstrates p-type or n-type behaviour depending on the back-gate voltage. Through simulations, the gate is shown to operate at 20 GHz and has been used to build a 1-bit pipelined full adder using physically identical reconfigurable cells     

三值钟控传输门绝热逻辑电路研究

通过分析开关一信号理论和绝热电路工作原理及结构,提出三值钟控传输门绝热逻辑(Ternary Clocked Transmission Gate Adiabatic Logic,TCTGAL)电路设计方案.该方案利用NMOS管自举效应和CMOS-1atch结构对输出负载进行充放电,并通过NMOS管栅漏并接对输出降压限幅;...     

A voltage tunable threshold logic gate based on multiquantum-wellheterojunction bipolar transistor for multifunction logic

The properties of a heterojunction bipolar transistor with a multiquantum-well collector region for its application as a voltage tunable logic element are examined. The quantum confined Stark effect gives rise to a strong negative differential resistance in the photocurrent-voltage characteristic of the device, which allows the device to be switched optically and/or electronically. This permits the realization of a circuit where the NAND, INVERSE CARRY, and NOR logic functions can be implemented by simply changing the biasing     

FinFET domino logic with independent gate keepers

Scaling of single-gate MOSFET faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the sub-threshold and gate-oxide leakage currents. Double-gate FinFET technology mitigates these limitations by the excellent control over a thin silicon body by two electrically coupled gates. In this paper a variable threshold voltage keeper circuit technique using independent-gate FinFET technology is proposed for simultaneous power reduction and speed enhancement in domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The optimum independent-gate keeper gate bias conditions are identified for achieving maximum savings in delay and power while maintaining identical noise immunity as compared to the standard tied-gate FinFET domino circuits. With the variable threshold voltage double-gate keeper circuit technique the evaluation speed is enhanced by up to 49% and the power consumption is reduced by up to 46% as compared to the standard domino logic circuits designed for similar noise margin in a 32 nm FinFET technology.     

基于SOA-XGM效应的双逻辑门叠加结构研究

为了提高光传输系统数据信息的机密性与安全性,开展了光传输系统物理层全光加/解密技术的理论分析,设计了全光AB逻辑实验方案,通过结构相同的两全光AB逻辑门输出信号的耦合,实验实现了对速率为10Gb/s的明文光信号的全光加密。     

Mixed static and domino logic on the CMOS gate forest

In a semicustom design environment with unified transistor geometries, logic circuit optimization is achieved using an efficient physical circuit implementation. In particular, the semicustom realization of domino logic is demonstrated with a standard-cell and a multiplier design which are used to support the implementation of such a dynamic logic design style on a gate forest, which has a higher n count than p count. The mixture of complementary and dynamic logic allows the designer to improve the critical-path delay and to reduce the size of the layout. The domino standard-cell architecture supports multiple-output configurations and additional internal precharge. The operation time for a mixed static/dynamic multiplier is approximately 30% higher than that of the static version based on a carry select adder. This difference mainly affects the critical delay of the sign-extension path of the parallel adder array     

基于半导体光放大器的新型全光逻辑与门

为了实现基于半导体光放大器的全光逻辑与门,采用了在半导体光放大器构成的马赫-曾德尔干涉仪的基础上,注入外部连续光的方法.以半导体光放大器速率方程为基础,对设计方案进行了理论分析和仿真验证,取得了不同重复周期、不同脉冲宽度的光脉冲序列经过全光逻辑与门操作后的输出数据.结果表明,该方案能对传输速率为10Gbit/s或以下的信号进行正确与运算,同时,外光注入可以有效提高半导体光放大器信号处理速度.这一结果对基于半导体光放大器的全光逻辑的设计是有帮助的.     

Universal delay test sets for logic networks

It has been shown earlier that, if we are restricted to unate gate network (UGN) realizations, there exist universal test sets for Boolean functions. Such a test set only depends on the function f, and checks any UGN realization of f for all multiple stuck-at faults and all robustly testable stuck-open faults. In this paper, we prove that these universal test sets are much more powerful than implied by the above results. They also constitute complete delay fault test sets for arbitrary UGN implementations of a given function. This is even true for UGN networks which are not completely testable with respect to the gate or path delay fault model. Our ability to prove the temporal correctness of such circuit realizations comes from the fact that we do not argue the correctness of individual paths, but rather complete path systems     

A 0.5-V MTCMOS/SIMOX logic gate

This paper proposes a multithreshold CMOS (MTCMOS) circuit that uses SIMOX process technology. This MTCMOS/SIMOX circuit combines fully depleted low-threshold CMOS logic gates and partially depleted high-threshold power-switch transistors. The low-threshold CMOS gates have a large noise margin for fluctuations in operating temperature in addition to high-speed operation at the low supply voltage of 0.5 V. The high-threshold power-switch transistor in which the body is connected to the gate through the reverse-diode makes it possible to obtain large channel conductance in the active mode without any increase of the leakage current in the sleep mode. The effectiveness of the MTCMOS/SIMOX circuit is confirmed by an evaluation of a gate-chain test element group (TEG) and an experimental 0.5-V, 40-MHz, 16-b ALU, which were designed and fabricated with 0.25-μm MTCMOS/SIMOX technology     

Subnanosecond emitter-coupled logic gate circuit using Isoplanar II

Describes a 650-ps propagation delay voltage and temperature compensated emitter-coupled logic dual-gate circuit using a new and significantly improved transistor structure. The transistor structure is an improvement over standard Isoplanar and is called Isoplanar II. Isoplanar II transistors eliminate the need for base region diffusion beyond the emitter ends, and for a given emitter size the collector-base junction area is less than 40 percent of the area otherwise needed for the conventional Planar transistor. The total silicon area per transistor is reduced by more than a factor of 2 over conventional IC techniques. These features reduce the collector-base and collector-isolation capacitances significantly. The result is significant improvement in switching performance without any sacrifice in voltage levels and voltage supply tolerances.     

A Josephson adder employing high-gain direct-coupled logic gate

A wide-margin adder with a simple configuration employing high-gain direct-coupled logic gates (HDCL's) was studied. A wide-margin half-adder circuit, consisting of a single junction and three HDCL buffer gates, is proposed. In order to obtain a wide-margin circuit, gates were designed to be protective against a noise signal. The experimental circuit fabricated by a conventional Pb alloy Josephson technology with 5-µm minimum line width has shown wide-margin (more than a ± 30-percent bias signal margin) characteristics, as predicted by a computer simulation. This paper also demonstrates that the adder can be simply modified into a wide-margin full adder with a simple configuration by connecting an additional single junction and a buffer gate for a carry signal.     

Direct-coupled logic operation of GaAs column gate FET

A ring oscillator operation is demonstrated employing normally-off 2 µm diameter column gate FET with 145 ps/gate delay time and with 64 fJ power-delay product. Delay time is discussed in terms of CR time constant comparison between MES and column structure. The column gate FET can realize much smaller "on" resistance comparing with MESFET.     

Modified super pass gate for multiple-valued logic circuits

A model of a super pass gate (SPG) is adapted to allow multiple-valued logic circuit connections and designs that are normally prohibited by the formal synthesis and minimisation technique for the device. The modification of the SPG allows more efficient circuit minimisation to be achieved for functions that do not readily reduce under the formal synthesis technique