Three-dimensional flip-chip on flex packaging for power electronicsapplications

We have extended the concept of flip-chip technology, which is widely used in IC packaging, to the packaging of three-dimensional (3-D) integrated power electronics modules (IPEMs). We call this new approach flip-chip on flex IPEM (FCOF-IPEM), because the power devices are flip-chip bonded to a flexible substrate with control circuits. We have developed a novel triple-stacked solder bump metallurgy for improved and reliable device interconnections. In this multilayer structure, we have carefully selected packaging materials that distribute the thermo-mechanical stresses caused by mismatching coefficients of thermal expansion (CTEs) among silicon chips and substrates. We have demonstrated the feasibility of this packaging approach by constructing modules with two insulated gate bipolar transistors (IGBTs), two diodes, and a simple gate driver circuit. Fabricated FCOF-IPEMs have been successfully tested at power levels up to 10 kW. This paper presents the materials and reliability issues in the package design along with electrical, mechanical, and thermal test results for a packaged IPEM     

Chip-scale packaging of power devices and its application inintegrated power electronics modules

A power electronics packaging technology utilizing chip-scale packaged (CSP) power devices to build three-dimensional (3-D) integrated power electronics modules (IPEMs) is presented in this paper. The chip-scale packaging structure, termed die dimensional ball grid array (D²BGA), eliminates wire bonds by using stacked solder joints to interconnect power chips. D²BGA package consists of a power chip, inner solder caps, high-lead solder balls, and molding resin. It has the same lateral dimensions as the starting power chip, which makes high-density packaging and module miniaturization possible. This package enables the power chip to combine excellent thermal transfer, high current handling capability, improved electrical characteristics, and ultralow profile packaging. Electrical tests show that the V_CE(sat) and on-resistance of the D²BGA high speed insulated-gate-bipolar transistors (IGBTs) are improved by 20% and 30% respectively by eliminating the device wirebonds and other external interconnections, such as the leadframe. In this paper, we present the design, reliability, and processing issues of D²BGA package, and the implementation of these chip-scale packaged power devices in building 30 kW half-bridge power converter modules. The electrical and reliability test results of the packaged devices and the power modules are reported     

Fatigue analysis of high-speed photodiode submodule by using FEM

Higher frequencies, super high-speed, and low-cost demands in wireless communication devices have lead to high density packaging technologies such as flip chip interconnections and multichip modules, as substitutes for wire bonding interconnection. Solder is widely used to connect chips to their packaging substrates in flip chip technology and surface mount technology. We constructed global full 3-D FE models for one photodiode on a submount to predict the fatigue life of solder interconnects during an accelerated thermal cycling testing. The 3-D FE models applied is based on the Darveaux approach does this approach have a non-linear viscoplastic analysis. In the bump structural photodiode submodule, the shortest fatigue life of 233 cycles was obtained at the thermal cycling testing condition from −65 to 150 °C. The bump material, rather than submount material, affected and varied the fatigue life. Also, The fatigue life is decreased with increase in creep strain energy density.     

Connection of VLSI chips to printed circuit board using stacked solder bumps

A new type of flip-chip interconnection technology usingstacked solder bumps is proposed, where the diameter of theupper solder bump is less than that of the lower ones. This isto reduce the capacitance between the stacked solder bumps and the ground plane and to prolong the lifetime ofthe solder joints.     

Flip-chip on flex integrated power electronics modules for high-density power integration

Three-dimensional flip-chip on flex (FCOF) integrated power electronics modules (IPEMs) have been fabricated for high-density power applications. In this FCOF-IPEM structure, solder-bumped devices were flip-soldered to a flexible substrate with electrical circuits etched on both sides. One side of the flex provides interconnection to power devices while the other is used to construct a simple gate-drive circuit; via holes through the flex integrate the power stage and gate-drive together. Solder-bumped MOSFET devices were obtained by a metallization processing and were used in the FCOF power module construction to improve thermal performance, power density, and integration. With this packaging approach, the multiple solder bumps, instead of the thin, long bonding wires were utilized to connect the power devices to the flex substrate and to improve heat dissipation, lower parasitic oscillations, and reduce package size. Reliability of solder joints has been dealt with through selection of materials, such as use of flexible substrates and underfill encapsulation, and design of joint shape for lower thermomechanical stresses. A comparative study of continuous switching test results have shown that the FCOF-IPEMs have better electrical performance than commercial wire bonded power modules.     

A novel flip-chip interconnection technique using solder bumps forhigh-speed photoreceivers

A flip-chip interconnection technique using small solder bumps instead of conventional wire bonding for high-speed broadband photoreceivers is described. The technique achieves interconnection with low parasitic elements, no damage to devices, and easy assembly. A photoreceiver composed of a broadband p-i-n photodiode and a laser-speed GaAS metal-semiconductor field-effect transistor (MESFET) preamplifier connected using solder bumps that are about 26 μm in diameter, with a frequency response of over 22 GHz at 1.55 μm, is demonstrated. This confirms the effectiveness of the solder bump interconnection technique for future high-speed broadband optical modules     

Solder joint reliability of indium-alloy interconnection

Recent high-density very large scale integrated (VLSI) interconnections in multichip modules require high-reliability solder interconnection to enable us to achieve small interconnect size andlarge number of input/output terminals, and to minimize soft errors in VLSIs induced by α-particle emission from solder. Lead-free solders such as indium (In)-alloy solders are a possible alternative to conventional lead-tin (Pb-Sn) solders. To realize reliable interconnections using In-alloy solders, fatigue behavior, finite element method (FEM) simulations, and dissolution and reaction between solder and metallization were studied with flip-chip interconnection models. We measured the fatigue life of solder joints and the mechanical properties of solders, and compared the results with a computer simulation based on the FEM. Indium-alloy solders have better mechanical properties for solder joints, and their flip-chip interconnection models showed a longer fatigue life than that of Pb-Sn solder in thermal shock tests between liquid nitrogen and room temperatures. The fatigue characteristics obtained by experiment agree with that given by FEM analysis. Dissolution tests show that Pt film is resistant to dissolution into In solder, indicating that Pt is an adequate barrier layer material for In solder. This test also shows that Au dissolution into the In-Sn solder raises its melting point; however, Ag addition to In-Sn solder prevents melting point rise. Experimental results show that In-alloy solders are suitable for fabricating reliable interconnections.     

Three-Dimensional System-in-Package Using Stacked Silicon Platform Technology

In this paper, a novel method of fabricating three–dimensional (3-D) system-in-package (SiP) using a silicon carrier that can integrate known good dice with an integrated cooling solution is presented. The backbone of this stacked module is the fabrication of a silicon carrier with through-hole conductive interconnects. The design, process, and assembly to fabricate silicon through-hole interconnect using a wet silicon etching method is discussed in this paper. The process optimization to fabricate silicon carriers with solder through-hole interconnect within the design tolerance has been achieved. The design and modeling methodology to optimize the package in terms of electrical aspects of the stacked module is carried out to achieve less interconnect parasitics. An integrated cooling solution for 3-D stacked modules using single-phase and two-phase cooling solutions is also demonstrated for high-power applications. Known good thin flip-chip devices with daisy chain are fabricated and attached to the silicon carrier by flip-chip processes making it a known good carrier after electrical testing. Individual known good carriers are vertically integrated to form 3-D SiP.     

Ultra-high-density interconnection technology of three-dimensional packaging

The study of 20-μm-pitch interconnection technology of three-dimensional (3D) packaging focused on reliability, ultrasonic flip–chip bonding and Cu bump bonding is described. The interconnection life under a temperature cycling test (TCT) was at an acceptable level for semiconductor packages. Failure analysis and finite element analysis revealed the effect of material properties. Basic studies on ultrasonic flip–chip bonding and very small Cu bump formation were investigated for low-stress bonding methods. The accuracy of ultrasonic flip–chip bonding was almost the same level as that of thermocompression bonding and the electrical connection was also confirmed. Atomic-level bonding was established at the interface of Au bumps. For Cu bump bonding, a dry process was applied for under bump metallurgy (UBM) removal. Electroless Sn diffusion in Cu was investigated and the results clarified that the intermetallic layer was formed just after plating. Finally, we succeeded in building a stacked chip sample with 20-μm-pitch interconnections.     

Under bump metallurgy study for Pb-free bumping

The demand for Pb-free and high-density interconnection technology is rapidly growing. The electroplating-bumping method is a good approach to meet finepitch requirements, especially for high-volume production, because to volume change of patterned-solder bumps during reflow is not so large compared with the stencil-printing method. This paper proposes a Sn/3.5 Ag Pb-free electroplating-bumping process for high-density Pb-free interconnects. It was found that a plated Sn/Ag bump becomes Sn/Ag/Cu by reflowing when Cu containing under bump metallurgy (UBM) is used. Another important issue for future flip-chip interconnects is to optimize the UBM system for high-density and Pb-free solder bumps. In this work, four UBM systems, sputtered TiW 0.2 μm/Cu 0.3 μm/electroplated Cu 5 μm, sputtered Cr 0.15 μm/Cr-Cu 0.3 μm/Cu 0.8 μm, sputtered NiV 0.2 μm/Cu 0.8 μm, and sputtered TiW 0.2 μm/NiV 0.8 μm, were investigated for interfacial reaction with electroplated Pb/63Sn and Sn/3.5Ag solder bumps. Both Cu-Sn and Ni-Sn intermetallic compound (IMC) growth were observed to spall-off from the UBM/solder interface when the solder-wettable layer is consumed during a liquid-state “reflow” process. This IMC-spalling mechanism differed depending on the barrier layer material.     

Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer

A 3-D packaging technology is developed for stacked dynamic random access memory (DRAM) with through-silicon vias (TSVs). Eight different dry etchers were evaluated for deep Si etching. Highly doped poly-Si TSVs were used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM-compatible process. Through optimization of process conditions and layout design, a fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using smart chip connection with feedthrough interposer (FTI) technology. A new bump and wiring structure for the FTI has also been developed for fine-pitch and low-cost bonding. Normal operation during DRAM read/write was confirmed on a 512-Mb DRAM with TSVs, with an I/F chip as a memory controller. Simulation and measurement of the transfer function of the FTI wiring showed a 3-Gb/s/pin data transfer capability.     

Recent advances in modeling the underfill process in flip-chip packaging

Flip-chip underfill process is a very important step in the flip-chip packaging technology because of its great impact on the reliability of the electronic devices. In this technology, underfill is used to redistribute the thermo-mechanical stress generated from the mismatch of the coefficient of thermal expansion between silicon die and organic substrate for increasing the reliability of flip-chip packaging. In this article, the models which have been used to describe the properties of underfill flow driven by capillary action are discussed. The models included apply to Newtonian and non-Newtonian behavior with and without the solder bump resistance for the purpose of understanding the behavior of underfill flow in flip-chip packaging.     

Using scanning acoustic microscopy and LM-BP algorithm for defect inspection of micro solder bumps

Micro solder bump has been widely used in electronic packaging. Currently a number of flip-chip products are developing towards miniaturization with more I/Os at finer pitch, and defect inspection of the high density package is increasingly challenging. In this paper, the Levenberg-Marquardt back-propagation network (LM-BP) combined with the scanning acoustic microscopy technology was investigated for intelligent diagnosis of solder defect. The flip chips were detected by using a 230 MHz ultrasonic transducer. Solder bumps were segmented from the SAM image. The statistical features were extracted and fed into the LM-BP networks for bump classification. The results demonstrate that LM-BP algorithm reached a high recognition accuracy, and is effective for defect inspection of the micro solder bump.     

The use of Mahalanobis-Taguchi System to improve flip-chip bumping height inspection efficiency

With the electronics industry advancing rapidly toward faster, smaller, lighter, and cheaper products, flip-chip packaging has been extensively used in microelectronics. The interconnection of the flip-chip offers several advantages over the widely used wire bonding technique. To obtain a reliable interconnection of the flip-chip, it is important to maintain adequate height of bumps that are plated on the chips. The bump height inspection process is time-consuming in practice and often becomes a constraint during production. The present study aims at solving the bump height inspection efficiency problem. Mahalanobis-Taguchi System (MTS) method is used to reduce the number of bump height measurement points whilst maintaining a high-accuracy inspection level. The results indicate that the numbers of bump height inspection features are significantly reduced from 10 to 6 without losing classification accuracy; and inspection time can be reduced by 40%. By reduction of inspection features, the operation time of the bump height inspection process is reduced. Moreover, the inspection staff can select the inspection position in sequence, according to the significance of features selected by the MTS method. Moreover, they can reduce the number of inspection positions to achieve an acceptable height of bumps.     

Application of laser deprocessing technique in PFA on chemical over-etched on bond-pad issue

With technology scaling of semiconductor devices and further growth of the integrated circuit (IC)¹ design and function complexity, the package size has shrank down proportionally too. Hence, flip-chip solder bump mounting is the current semiconductor devices trend to replace the wire bonding technology.When come to PFA² on the flip-chip devices with solder bump, wet etch for solder bump removal is an essential method. Upon using wet etch methodology; it is very dependent on etching timing and the chemical aggressiveness to get a good removal result for the solder bump. If there is an excessive period in etching or chemical reacts too aggressively, chemical over-etched on bond pad will occur. It is very unfavorable for FA³ engineer to perform subsequent reverse engineering on the bond pad over-etched device.In this paper, the application of laser deprocessing technique is proposed to solve the bond pad over-etched issue. This proposed technique is a quick and reversal way in deprocessing technique for defect identification in PFA.     

Optimization of Material and Process for Fine Pitch LVSoP Technology

For the formation of solder bumps with a fine pitch of 130 μm on a printed circuit board substrate, low‐volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of 220°C. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 μm, 18.3 μm, and 12.0 μm, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine‐pitch interconnection of a Cu pillar in the semiconductor packaging field.     

Influence of transient flow and solder bump resistance on underfill process

The underfill flow process is one of the important steps in Microsystems technology. One of the best known examples of such a process is with the flip-chip packaging technology which has great impact on the reliability of electronic devices. For optimization of the design and process parameters or real-time feedback control, it is necessary to have a dynamic model of the process that is computationally efficient yet reasonably accurate. The development of such a model involves identifying any factors that can be neglected with negligible loss of accuracy. In this paper, we present a study of flow transient behavior and flow resistance due to the presence of an array of solder bumps in the gap. We conclude (1) that the assumption of steady flow in the modeling of the flow behavior of fluids in the flip-chip packaging technology is reasonable, and (2) the solder bump resistance to the flow can not be neglected when the clearance between any two solder bumps is less than 60-70 μm. We subsequently present a new model, which extends the one proposed by Han and Wang in 1997 by considering the solder bump resistance to the flow.     

SiGe HBT Microprocessor Core Test Vehicle

A major impediment to the continuation of Moore's Law in the years to come is the performance of interconnections in ICs at high frequencies. Microprocessors are using a greater portion of their clock cycle charging and discharging interconnections. Silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) provide a fast track technology for the exploration of the effect of interconnections on high-speed computer design. Industry has pursued low-k dielectrics to decrease wire capacitance. Cu metallization has been used to reduce wire resistance which becomes important as the wire dimensions are scaled down. These are not the only issues for high-frequency interconnections. Some other high-frequency issues include coupling, transmission line propagation, skin effects, and dielectric and substrate loss. These phenomena cause signal attenuation, noise, and dispersion in addition to delay. In the limit of zero device delay, interconnection delay will remain in addition to these problems. Wire shortening has been possible using more layers of interconnections, but this approach may be reaching its limit. An unconventional approach, three-dimensional (3-D) integration, attempts to shorten wiring through increased circuit component placement flexibility. The approach considered here for 3-D integration uses wafer-to-wafer aligning and bonding, wafer thinning and deep, high-aspect-ratio Cu via formation. This provides an intimate interconnection between CPU components and an extremely wide path to memory that would be infeasible in conventional or multichip module packaging. This combination of SiGe HBT BiCMOS and 3-D chip stack technologies enables small computing engines in the 16-32-GHz range.     

High-performance FCBGA based on multi-layer thin-substrate packaging technology

We developed a new concept flip-chip ball grid array (FCBGA) based on multi-layer thin-substrate (MLTS) packaging technology in order to meet the strong demand for high-density, high-performance, and low-cost LSI packages. The most important feature of MLTS packaging is that, only a high-density and high-performance MLTS remains by removing the metal plate after mounting an LSI chip. The MLTS packaging offers the advantages of (1) good registration accuracy, which makes higher-density and finer-pitch pattering possible; (2) an ideal multi-layer structure that is highly suitable for high-speed and high-frequency applications; (3) excellent flip-chip mounting reliability, which makes higher-pin-count and finer-pitch area array flip-chip interconnection possible; (4) excellent reliability, supported by use of high T_g (glass transition temperature) resin; and (5) a cost-effective design achieved as a result of fewer layers fabricated with fine-pitch patterning.We successfully produced a high-performance FCBGA prototype based on our MLTS packaging technology. The prototype comprises an LSI chip connected to approximately 2500 bonding pads arranged in 240 μm pitch area array, and 1296 I/O pads for BGA. The prototype FCBGA’s excellent long-term reliability was demonstrated through a series of tests conducted on it.     

SnAg Microbumps for MEMS-Based 3-D Stacks

Fine pitch 100-$mu{rm m}$ electroplated SnAg microbump interconnection technology is presented and discussed for use in microelectromechanical systems (MEMS) based 3-D stacks. Electrochemical deposition (ECD) of copper top side metallization (TSM) is compared to performance of nickel–copper TSM on substrate chips. Nickel–copper was selected for under bump metallization (UBM) of die chips. Lead free Sn3.5%Ag was deposited on the die chip UBM and chip-to-wafer bonded by a standard SnAg reflow process in inert atmosphere. An automotive application module was selected as target application for investigating reliability and failure mechanism of the interconnection technology. Bonded units have been investigated by mechanical and physical analysis, visual inspection and electrical resistance measurements after assembly and subsequent environmental stress test including thermal cycling, elevated temperature, humidity, and high current. The fine pitch lead free microbumps displayed promising capability for 3-D stacking of silicon devices. Excellent performance under thermal cycling with no global thermal mismatch was demonstrated. The microbump interconnection technology proved to be tolerant to high temperature and extensive current exposure. TSM consumption and intermetallic compound (IMC) formation were less evident for the nickel–copper TSMs compared to those entirely made of copper. Only minor Kirkendall porosity was observed at the solder alloy interfaces in the present study.