基于信道估计的限幅OFDM信号检测性能分析

大峰均比是正交频分复用(OFDM)系统的主要缺陷之一，对时域OFDM信号限幅是通常采用的一种抑制发送信号峰值功率的方法，但是限幅产生的非线性干扰，使系统的信道估计和信号检测性能降低。本文分析了限幅干扰对信道估计以及基于估计信道信息的OFDM数据信号检测性能的影响，推导出了基于信道估计信号检测的信噪比与限幅参数之间的关系。利用信噪比和高斯信道的误符号率及误比特率公式，本文对频率选择性瑞利衰落信道环境限幅OFDM系统中信号的误符号率和误比特率进行估算。计算机仿真和估算的结果相吻合。     

A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators

A 0.6-V 2-2 cascaded audio delta-sigma ADC is described. It uses a resistor-based sampling technique which achieves high linearity and low-voltage operation without subjecting the devices to large terminal voltages. A low-distortion feed-forward topology combined with nonlinear local feedback results in enhanced linearity by reducing the sensitivity to opamp distortion, and allows increased input amplitude, resulting in higher SNDR. The modulator achieves 82-dB dynamic range and 81-dB peak SNDR in the A-weighted audio signal bandwidth with an OSR of 64. The total power consumption of the modulator is 1 mW from a 0.6-V supply. The prototype occupies 2.9 mm/sup 2/ using a 0.35-/spl mu/m CMOS technology.     

功放非线性对QAM解调误码率的影响

QAM调制由于高频谱效率得到了广泛应用,但由于QAM信号的功率峰均比较高,功率放大器的非线性会导致解调性能的下降。针对功放非线性对QAM解调性能的影响,传统方法采用仿真实验的方法来获得,而文中推导了高斯信道下功率放大器的非线性对QAM解调误码率影响的闭合表达式,可求出非线性功放在不同静态工作点对应的误码率。仿真结果验证了理论分析的正确性。     

一个压力传感器应用的∑-Δ模数转换调制器

文章介绍了一个用于压力传感器的∑-ΔAD转换器的调制器设计。它能在低于200mV输入信号伴随100μV低频噪声的条件下提供高达87dB的信噪比,有效精度达到14位,并且具有可编程的过采样率以适应不同应用需求。采用0.5μmCMOS双多晶三铝工艺设计,3.4V电源,总功耗小于200μW。全文分析了AD转换器在系统中应用时,系统对AD的性能指标要求以及如何设计具体的参数来达到所要求的精度。     

A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration

Digital calibration using adaptive signal processing corrects for offset mismatch, gain mismatch, and sample-time error between time-interleaved channels in a 10-b 120-Msample/s pipelined analog-to-digital converter (ADC). Offset mismatch between channels is overcome with a random chopper-based offset calibration. Gain mismatch and sample-time error are overcome with correlation-based algorithms, which drive the correlation between a signal and its chopped image or its chopped and delayed image to zero. Test results show that, with a 0.99-MHz sinusoidal input, the ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 56.8 dB, a peak integral nonlinearity of 0.88 least significant bit (LSB), and a peak differential nonlinearity of 0.44 LSB. For a 39.9-MHz sinusoidal input, the ADC achieves a peak SNDR of 50.2 dB. The active area is 5.2 mm/sup 2/, and the power dissipation is 234 mW from a 3.3-V supply.     

A Multi-Mode Sigma-Delta ADC for GSM/WCDMA/WLAN Applications

The demand for new telecommunication services requiring higher capacities, data rates and different operating modes have motivated the development of new generation multi-standard wireless transceivers. In multi-standard design, sigma-delta based ADC is one of the most popular choices. To this end, in this paper we present cascaded 2-2-2 reconfigurable sigma-delta modulator that can handle GSM, WCDMA and WLAN standards. The modulator makes use of a low-distortion swing suppression topology which is highly suitable for wide band applications. In GSM mode, only the first stage (2nd order ∑-Δ ADC) is used to achieve a peak SNDR of 88dB with over-sampling ratio of 160 for a bandwidth of 200KHz and for WCDMA mode a 2-2 cascaded structure (4th order) is turned on with 1-bit in the first stage and 2-bit in the second stage to achieve 74 dB peak SNDR with over-sampling ratio of 16 for a bandwidth of 2MHz. Finally, a 2-2-2 cascaded MASH architecture with 4-bit in the last stage is proposed to achieve a peak SNDR of 58dB for WLAN for a bandwidth of 20MHz. The novelty lies in the fact that unused blocks of second and third stages can be made inactive to achieve low power consumption. The modulator is designed in TSMC 0.18um CMOS technology and operates at 1.8 supply voltage.     

一种基于电阻型数模转换器每级输出3位的6-bit 410-MS/s单通道异步逐次逼近模数转换器

该设计采用SMIC 65-nm CMOS工艺,实现了一款可应用于超宽带通信领域的单通道低功耗6位410-MS/s异步逐次逼近模数转换器(SAR ADC)。通过采用电阻型数模转换器、每级输出3位数字码字结构,以及改进的异步控制逻辑,该ADC在370-MS/s采样率时,无杂散动态范围(SFDR)达到41.95-dB,信号噪声失真比(SNDR)达到28.52-dB。在采样率为410MS/s时,该设计仍能达到40.71-dB的SFDR和30.02-dB的SNDR。通过动态比较器的使用,实现了低功耗设计。测试结果表明,在410-MS/s采样率下,电路总功耗为2.03mW,对应的品质因子(FOM)为189.17fJ/step。     

A 2.1 μW 80 dB SNR DT ΔΣ modulator for medical implant devices in 65 nm CMOS

This paper presents a simple and robust low-power ΔΣ modulator for accurate ADCs in implantable cardiac rhythm management devices such as pacemakers. Taking advantage of the very low signal bandwidth of 500 Hz which enables high oversampling ratio, the objective is to obtain high SNDR and low power consumption, while limiting the complexity of the modulator to a second-order architecture. Significant power reduction is achieved by utilizing a two-stage load-compensated OTA as well as the low-V_T devices in analog circuits and switches, allowing the modulator to operate at 0.9 V supply. Fabricated in a 65 nm CMOS technology, the modulator achieves 80 dB peak SNR and 76 dB peak SNDR over a 500 Hz signal bandwidth. With a power consumption of 2.1 μW, the modulator obtains 0.4 pJ/step FOM. To the authors’ knowledge, this is the lowest reported FOM, compared to the previously reported second-order modulators for such low-speed applications. The achieved FOM is also comparable to the best reported results from the higher-order ΔΣ modulators.     

Design of Semi-Uniform Quantizers and Their Application in Sigma Delta A/D Converters

In this paper a new type of non-uniform quantizer, semi-uniform quantizer, is introduced. A k-bit semi-uniform quantizer uses the thresholds defined by a (k + 1)-bit uniform quantizer and arranges them in such a way that small-amplitude inputs will be quantized by small quantization steps and large-amplitude inputs by large quantization steps. Therefore the total quantization error power could be reduced and the modulator's dynamic range could be increased by 1-bit. The condition for a semi-uniform quantizer to achieve a better performance than a uniform quantizer is analyzed and verified using a second order 3-bit sigma delta modulator prototype chip, fabricated in 0.35 μm CMOS process. At 32× oversampling ratio the modulator achieves 81 dB dynamic range and 63.8 dB peak SNDR with 3-bit semi-uniform quantizer. With 3-bit uniform quantizer the dynamic range is 70 dB and the peak SNDR is 54.1 dB.     

A 65-nm low-noise low-costΣ△modulator for audio applications

正This paper introduces a low-noise low-costΣA modulator for digital audio analog-to-digital conversion. By adopting a low-noise large-output swing operation amplifier,not only is the flicker noise greatly inhibited,but also the power consumption is reduced.Also the area cost is relatively small.The modulator was implemented in a SMIC standard 65-nm CMOS process.Measurement results show it can achieve 96 dB peak signal-to-noise plus distortion ratio(SNDR) and 105 dB dynamic range(DR) over the 22.05-kHz audio band and occupies 0.16 mm~2. The power consumption of the proposed modulator is 4.9 mW from a 2.5 V power supply,which is suitable for high-performance,low-cost audio codec applications.     

On the design of signals for sequential and nonsequential detection systems with feedback

The design of signals for binary communication systems employing feedback has previously been considered by Turin. A delayless, infinite-bandwidth forward channel disturbed by additive, white, Gaussian noise is assumed. At each instant of time, the log likelihood ratio of the two possible signals is fed back to the transmitter via a noiseless and delayless feedback channel. The forward-channel signals are said to be optimally designed when the feedback information is so utilized that the average (for sequential detection) or fixed (for nonsequential detection) transmission time is minimized, subject to a specified probability of error. Average and peak power constraints are also placed on the signals. Turin has solved the signal design problem for extreme values (i.e., very large or equal to one) of the peak-to-average power constraint ratio. These results are extended in this paper to arbitrary values of the power constraint ratio, for both sequential and nonsequential detection.     

Transmit patterns for active linear arrays with peak amplitude andradiated voltage distribution constraints

Distribution functions used in array antenna design typically synthesize specified pattern characteristics without consideration for either the peak amplitude of the radiating elements or the aperture radiated power. There do exist applications, however, in which the pattern synthesis must employ such constraints. In the transmit mode of active array antennas, for example, it is desirable to radiate as much power as possible subject to a per-element peak amplitude constraint while simultaneously suppressing the outer sidelobes. This paper discusses the design considerations of the constrained least squares (CLS) distribution function. In the CLS distribution, most of the radiating elements near the array center are set to their maximum value while only a few of the outer elements are tapered. A method for generating CLS distributions given constraints on both the peak element amplitude and the total effective radiated voltage (ERV) is discussed. The design involves specifying the desired ERV and a weighting function that allows selectively suppressing sidelobes in specified regions. The effects of these design parameters on the far-field patterns are explored     

Effect of third-order intermodulation on radio-over-fiber systems by a dual-electrode Mach-Zehnder modulator with ODSB and OSSB signals

Third-order intermodulation (IM3) is a very important issue as a degradation factor of system performance in the range of high input signal power. In this paper, the effect of IM3 from a dual-electrode Mach-Zehnder modulator (DEMZM) and a photodetector (PD) is analyzed for optical single-sideband (OSSB) and optical double-sideband (ODSB) signals incorporating fiber dispersion. In addition, the optimum input signal power and the signal-to-noise-and-distortion ratio (SNDR) for the two cases are also investigated to optimize the performance of the entire system. In the case of OSSB signals, the fundamental components are robust against fiber dispersion, whereas their IM3 components are still sensitive to fiber dispersion. Subsequently, the SNDR for OSSB signals fluctuated to within 6 dB in the relatively high input power range due to fiber dispersion. In the case of ODSB signals, both powers of the fundamental and IM3 components are attenuated. However, the power attenuation of IM3 due to fiber dispersion is significantly faster than that of the fundamental. Thus, the SNDR for ODSB signals is improved as fiber dispersion increases until the power of IM3 is greater than that of the additive noise level.     

一种高性能CMOS采样/保持电路

提出了一种高性能CMOS采样/保持电路,它采用全差分电容翻转型的主体结构有效减小了噪声和功耗。在电路设计中提出了新型栅源电压恒定的自举开关来极大减小非线性失真,并同时有效抑止输入信号的直流偏移。该采样/保持电路采用0.18μm1P-6M CMOS双阱工艺来实现,在1.8V电源电压、32MHz采样速率下,输入信号直到奈奎斯特频率时仍能达到86.88dB的无杂散动态范围(SFDR),电路的信号噪声失真比(SNDR)为73.50dB。最后进行了电路的版图编辑,并对样片进行了初步测试,测试波形表明,电路实现了采样保持的功能。     

A 12-bit 3.125 MHz Bandwidth 0–3 MASH Delta-Sigma Modulator

We demonstrate a 12-bit 0–3 MASH delta-sigma modulator with a 3.125 MHz bandwidth in a 0.18 $muhbox{m}$ CMOS technology. The modulator has an oversampling ratio of 8 (clock frequency of 50 MHz) and achieves a peak SNDR of 73.9 dB (77.2 $~$dB peak SNR) and consumes 24 mW from a 1.8 V supply. For comparison purposes, the modulator can be re-configured as a single-loop topology where a peak SNDR of 64.5 dB (66.3 dB peak SNR) is obtained with 22 mW power consumption. The energy required per conversion step for the 0–3 MASH architecture (0.95 pJ/step) is less than half of that required by the feedback topology (2.57 pJ/step).      

A convex projections approach to spectral analysis

The projection onto convex sets (POCS) method is applied to the classical problem of estimating a power spectrum given values of the autocorrelation function (ACF). This new method can use any number of linear and/or nonlinear constraints on the spectrum to be estimated. The measured ACF constraint, the amplitude limit constraint, and the reference spectrum constraint are introduced, and the corresponding projection operators are established. Computer simulation results indicate that the POCS spectral analysis performs well     

Performance optimization of radio-on-fiber systems employing erbium doped fiber amplifier for optical single sideband signals considering intermodulation distortion

The performances of radio on fiber (RoF) systems with a dual-electrode Mach-Zehnder modulator and an erbium-doped fiber amplifier (EDFA) are optimized by numerical equations including the third order intermodulation (IM3) as well as amplified spontaneous emission (ASE) noise. We investigate a signal-to-noise-and-distortion ratio (SNDR) considering fiber dispersion with respect to an input signal power and an EDFA gain in both noise-dominant and third order intermodulation (IM3)-dominant cases. We also verify that the numerical analysis results are well matched with those of a commercial simulator, VPItransmissionMaker. In the analysis results, the optimum input signal power for the maximum SNDR of a RoF system with EDFA was reduced over 8 dB compared with that without EDFA. The dramatic reduction of IM3 power at a receiver was resulted from this decrement of input signal power. Thus, the maximum SNDR of the system with EDFA was obtained over 17 dB at 40 km fiber compared with that of the system without EDFA. In addition, the results showed that the SNDR was efficiently improved by EDFA in the noise-dominant case, while the SNDR improvement was negligible by EDFA in the IM3 dominant case.     

84dB动态范围13b/400kHz/3V/5.88mW∑△模数转换器

介绍了一个200kHz信号带宽、用于低中频结构GSM射频接收机的高精度∑△调制器.为了达到高线性和稳定性,调制器采用2-1级联单比特的结构实现.电路在0.18μm CMOS工艺下流片验证,核心面积为0.5mm×1.1mm.调制器工作在19.2MHz的采样频率,在3V电源电压下功耗为5.88mW.测试结果表明,在200kHz信号带宽,过采样率为64的条件下,调制器达到84.4dB动态范围,峰值SNDR达到73.8dB,峰值SNR达到80dB.     

Bandpass Sigma–Delta Modulator Employing SAW Resonator as Loop Filter

Continuous-time bandpass (BP) sigma-delta modulators (SigmaDeltaMs) employing surface acoustic wave (SAW) resonators as loop filters are presented. Compared with the loop filters realized with G_m-C and LC resonators, the SAW resonator has the advantage of high-Q factor, wide resonant frequency range and accurate resonant frequency without the need for automatic tuning. With the proposed anti-resonance cancellation and loop filter phase compensation techniques, a second- and a fourth-order BP SigmaDeltaMs are demonstrated in a 0.35-mum CMOS technology. Both modulators are tested with 47.3-MHz off-chip SAW resonators. The second-order modulator attains a dynamic range of 57 dB and peak signal-to-noise distortion ratio (SNDR) of 54 dB and the fourth-order one achieves a dynamic range of 69 dB and peak SNDR of 66 dB, both in a 200-kHz signal bandwidth. The fourth-order modulator is also measured in a 3.84-MHz signal bandwidth and achieves a dynamic range of 52.5 dB and peak SNDR of 50 dB, an effective 8-bit resolution     

55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers

A new power reduction technique for analog-to-digital converters (ADCs) is proposed in this paper. The power reduction technique is a kind of amplifier sharing technique and it is suitable for ADCs in a wireless receiver. A test chip, which contains two ADCs, is fabricated in 90-nm 1-poly 7-metal CMOS technology. The 10-bit ADC dissipates 55 mW from 1.2-V supply, when the ADC operates at 200 mega-samples per second (MSPS). The 10-bit, 200-MSPS ADCs achieve maximum differential nonlinearity (DNL) of 0.66 least significant bit (LSB), maximum integral nonlinearity (INL) of 1.00 LSB, a spurious-free dynamic range (SFDR) of 66.5 dB and a peak signal-to-noise plus distortion ratio (SNDR) of 54.4 dB that corresponds to 8.7 effective number of bits (ENOB). The active area is 1.8 mm /spl times/ 1.4 mm.