125-GHz Diode Frequency Doubler in 0.13-$mu{hbox {m}}$ CMOS

The first mm-wave Schottky diode frequency doubler fabricated in CMOS is demonstrated. The doubler built in 130-nm CMOS uses a balanced topology with two shunt Schottky barrier diodes, and exhibits $sim$10-dB conversion loss as well as $-$1.5-dBm output power at 125 GHz. The input matching is better than $-$10$~$dB from 61 to 66 GHz. The rejection of fundamental signal at output is greater than 12 dB for input frequency from 61 to 66$~$GHz. The doubler can generate signals up to 140 GHz.      

A 60-GHz Phased Array Receiver Front-End in 0.13-$mu {hbox{m}}$ CMOS Technology

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, ag_m-boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g_m-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm². The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.     

A 40-GHz Low-Noise Amplifier With a Positive-Feedback Network in 0.18-$mu{hbox{m}}$ CMOS

A novel circuit topology for a CMOS millimeter-wave low-noise amplifier (LNA) is presented in this paper. By adopting a positive-feedback network at the common-gate transistor of the input cascode stage, the small-signal gain can be effectively boosted, facilitating circuit operations at the higher frequency bands. In addition, $LC$ ladders are utilized as the inter-stage matching for the cascaded amplifiers such that an enhanced bandwidth can be achieved. Using a standard 0.18-$mu{hbox{m}}$ CMOS process, the proposed LNA is implemented for demonstration. At the center frequency of 40 GHz, the fabricated circuit exhibits a gain of 15 dB and a noise figure of 7.5 dB, while the return losses are better than 10 dB within the 3-dB bandwidth of 4 GHz. Operated at a 1.8-V supply, the LNA consumes a dc power of 36 mW.      

A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-$mu{hbox{m}}$ CMOS for $V$ -Band Applications

In this paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the $V$-band output signal is proposed. Since the proposed ILFM can generate the fifth-order harmonic frequency of the voltage-controlled oscillator (VCO) output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. With the loop gain smaller than unity in the ILFM, the output frequency range of the proposed PLL is from 53.04 to 58.0 GHz. The PLL is designed and fabricated in 0.18-$mu{hbox{m}}$ CMOS technology. The measured phase noises at 1- and 10-MHz offset from the carrier are $-$ 85.2 and $-{hbox{90.9 dBc}}/{hbox{Hz}}$, respectively. The reference spur level of $-{hbox{40.16 dBc}}$ is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. It can be seen that the advantages of lower power dissipation and similar phase noise can be achieved in the proposed PLL structure. It is suitable for low-power and high-performance $V$-band applications.      

A 750-MHz 6-b Adaptive Floating-Gate Quantizer in 0.35-$mu{hbox {m}}$ CMOS

A 6-b 750-MS/s flash analog-to-digital converter (ADC) uses nonvolatile analog storage for reference levels and achieves a signal-to-noise-plus-distortion ratio (SNDR) and a spurious-free dynamic range of 37.2 and 48.6 dB, respectively. The architecture comprises an array of adaptive floating-gate comparators that enables storage and programming of reference levels, eliminating the need for resistive ladders. Reference levels may be programmed either manually by the user or autonomously during normal analog-to-digital conversion. Autonomous programming achieves histogram equalization by adjusting reference levels for finer resolution and greater sensitivity at frequently visited signal values. When programmed manually, the ADC achieves 34.3-dB SNDR at 750 MS/s for input frequencies up to 2.07$times$ Nyquist rate, with a differential full-scale input range of 1 V. We observe integral nonlinearity and differential nonlinearity of less than 0.27 least significant bit at the Nyquist rate. One-month continuous operation shows no signs of reference-level drift due to charge leakage and maintains a constant bit error rate of $2.93times 10^{-9}/hbox{sample}$.      

A $Q$ -Band Four-Element Phased-Array Front-End Receiver With Integrated Wilkinson Power Combiners in 0.18-$mu{{hbox{m}}}$ SiGe BiCMOS Technology

A four-element phased-array front-end receiver based on 4-bit RF phase shifters is demonstrated in a standard 0.18- $mu{{hbox{m}}}$ SiGe BiCMOS technology for $Q$-band (30–50 GHz) satellite communications and radar applications. The phased-array receiver uses a corporate-feed approach with on-chip Wilkinson power combiners, and shows a power gain of 10.4 dB with an ${rm IIP}_{3}$ of $-$13.8 dBm per element at 38.5 GHz and a 3-dB gain bandwidth of 32.8–44 GHz. The rms gain and phase errors are $leq$1.2 dB and $leq {hbox{8.7}}^{circ}$ for all 4-bit phase states at 30–50 GHz. The beamformer also results in $leq$ 0.4 dB of rms gain mismatch and $leq {hbox{2}}^{circ}$ of rms phase mismatch between the four channels. The channel-to-channel isolation is better than $-$35 dB at 30–50 GHz. The chip consumes 118 mA from a 5-V supply voltage and overall chip size is ${hbox{1.4}}times {hbox{1.7}} {{hbox{mm}}}^{2}$ including all pads and CMOS control electronics.      

Blue-Enhanced PIN Finger Photodiodes in a 0.35-$mu{hbox {m}}$ SiGe BiCMOS Technology

Finger photodiodes in PIN technology are introduced to enhance the responsivity for blue and ultraviolet light. A thick low doped epitaxial layer results in high responsivity and high bandwidth also for red and near-infrared light. Results of PIN finger photodiodes are compared to that of PIN photodiodes for 10- and 15-mum epitaxial intrinsic layer thickness. The cathode finger structure results in a high responsivity of 0.20 A/W (quantum efficiency 61%) for 410-nm light and a bandwidth of 1.25 GHz for 10- mum epi thickness at a reverse bias voltage of 3 V. The rise and fall times with an epitaxial layer thickness of 15 mum are below 1 ns for the wavelength range from 410 to 785 nm.     

Numerical Modeling of Pulsed Raman Fiber Converters at 2 $mu{hbox {m}}$

Theoretical modeling of stimulated Raman scattering (SRS) in fibers is presented for the near-infrared band around 2 mum, where pump and Stokes wave have different absorption. This model takes into account amplified spontaneous emission (ASE), SRS towards Stokes and anti-Stokes waves, absorption of the Raman medium and Rayleigh backscattering in fibers. Depending on the fiber configuration, this model includes the cavity parameters of either external or internal mirrors at the fiber ends. Input parameters are, among others, temporal profiles of the pump radiation, absorption, and gain curve of the Raman medium. The model agrees well with experimental results obtained with a GeO₂ doped core fiber pumped by a pulsed and tunable Tm:silica fiber laser emitting around 2 mum.     

InGaAs/GaAs 0.98- $mu{hbox {m}}$ Low-Divergence Central-Lobe Semiconductor Lasers With $delta$ -Doped Resonant Tunneling Quantum Wells

In this paper, we describe a new structure design for producing low-threshold, high-efficiency, and high-brightness 0.98-$mu{hbox {m}}$ lasers. In this structure, we incorporated a self-discriminating weak optical confinement asymmetrical waveguide coupled to passive waveguides, and an active region based on three InGaAs quantum wells (QWs) coupled to Te n-type $delta$-doping. Optimized coupling between the $delta$-doping and the three QWs, together with waveguide optimization and doping profile optimization, yields $J_{rm th}=98 {hbox {A/cm}}^{2}$ per QW, ${T}_{0}=80;^{circ}hbox{C}$, and a far-field central lobe angle of $sim 10^{circ}$.      

22.7-dB Gain $-$19.7-dBm $ICP_{1{rm dB}}$ UWB CMOS LNA

A fully differential CMOS ultrawideband low-noise amplifier (LNA) is presented. The LNA has been realized in a standard 90-nm CMOS technology and consists of a common-gate stage and two subsequent common-source stages. The common-gate input stage realizes a wideband input impedance matching to the source impedance of the receiver (i.e., the antenna), whereas the two subsequent common-source stages provide a wideband gain by exploiting RLC tanks. The measurements have exhibited a transducer gain of 22.7 dB at 5.2 GHz, a 4.9-GHz-wide B _3dB, an input reflection coefficient lower than -10.5 dB, and an input-referred 1-dB compression point of -19.7 dBm, which are in excellent agreement with the postlayout simulation results, confirming the approach validity and the design robustness.     

A Current-Feedback Instrumentation Amplifier With 5 $mu{hbox{V}}$ Offset for Bidirectional High-Side Current-Sensing

This paper describes an instrumentation amplifier for bidirectional high-side current-sensing applications. It uses a multipath indirect current-feedback topology. To achieve low offset, the amplifier employs a combination of chopping and auto-zeroing in a low frequency path to cancel the offset of a wide-band amplifier in a high frequency path. With a 60 kHz chopper clock and a 30 kHz auto-zero clock, this offset-stabilization scheme results in an offset voltage of less than 5 $mu{hbox{V}}$ , a CMRR of 143 dB and a common-mode input voltage range from 1.9 to 30 V. The input voltage-to-current (V-I) converters required by the current-feedback topology are implemented with composite transistors, whose transconductance is determined by laser-trimmed resistors. This results in a less than 0.1% gain inaccuracy. The instrumentation amplifier was realized in a 0.8 $mu{hbox{m}}$ BiCMOS process with high voltage transistors, and has an effective chip area of 2.5 ${hbox{mm}}^{2}$ .      

A 27 GHz, 14 dBm CMOS Power Amplifier Using 0.18 $mu {rm m}$ Common-Source MOSFETs

A Ka-band three-stage CMOS power amplifier was designed and fabricated using 0.18 $mu {rm m}$ gate-length common-source transistors. For low loss and accurate matching networks for the amplifier, a substrate-shielded microstrip-line was used with good modeling accuracy up to 40 GHz. The measured insertion loss was 0.5 dB/mm at 25 GHz. The three-stage amplifier achieved a 14.5 dB small-signal gain, 14 dBm output power, and 13.2% power-added-efficiency at 27 GHz in a compact chip area of 0.84 ${rm mm}^{2}$. The measured gain was the highest for Ka-band power amplifiers using common-source transistors. These results were achieved at a voltage compatible with deep sub-micrometer CMOS technology.      

A Differential Clapp-VCO in 0.13 $mu{rm m}$ CMOS Technology

A new differential voltage-controlled oscillator (VCO) is designed and implemented in a 0.13 $mu{rm m}$ CMOS 1P8M process. The designed circuit topology is an all nMOS LC-tank Clapp-VCO using a series-tuned resonator. At the supply voltage of 0.9 V, the output phase noise of the VCO is $-$110.5 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 18.78 GHz, and the figure of merit is $-$188.67 dBc/Hz. The core power consumption is 5.4 mW. Tuning range is about 3.43 GHz, from 18.79 to 22.22 GHz, while the control voltage was tuned from 0 to 1.3 V.      

A 1.5–9.6 GHz Monolithic Active Quasi-Circulator in 0.18 $mu{rm m}$ CMOS Technology

An active quasi-circulator MMIC was designed and fabricated in a standard 0.18-$mu{rm m}$ CMOS technology. The quasi-circulator combines common-source, common-gate, and common-drain configurations to improve the isolation between ports, and has an insertion loss less than 6 dB and an isolation better than 18 dB over 1.5–9.6 GHz.      

Experimental Demonstration of Multi-Bit Optical Buffer Memory Using 1.55-$mu{hbox {m}}$ Polarization Bistable Vertical-Cavity Surface-Emitting Lasers

We demonstrate a novel all-optical buffer memory using 1.55-$mu{hbox {m}}$ polarization bistable vertical-cavity surface-emitting lasers (VCSELs). A one-bit data is stored as one of two orthogonal polarization states of a VCSEL in this memory. The polarization state is transferred from the VCSEL to another VCSEL which is optically connected in cascade as a shift register. A 4-bit optical buffer memory is constructed using two sets of the shift-register memory connected in parallel. These results show the technical feasibility of multi-bit optical buffer memory.      

A 40 GHz Differential Push-Push VCO in 0.18 $mu{rm m}$ CMOS for Serial Communication

A 40 GHz differential CMOS push-push VCO is proposed for high-frequency applications. It is shown analytically that the phase noise of the VCO output at the full-rate frequency is close to 6 dB higher than that of the half-rate frequency. The result of the phase noise analysis is verified by simulations and measurements. A phase noise of $-$ 101 dBc/Hz was achieved at 1 MHz offset frequency. The proposed push-push VCO design enables higher VCO frequency operation with differential output, which is suitable for millimeter wave frequency synthesizers.      

A 3$,times,$5-Gb/s Multilane Low-Power 0.18-$mu{hbox {m}}$ CMOS Pseudorandom Bit Sequence Generator

A low-power, three-lane, pseudorandom bit sequence (PRBS) generator has been fabricated in a 0.18-mum CMOS process to test a multilane multi-Gb/s transmitter that cancels far-end crosstalk. Although the proposed PRBS generator was designed to produce three uncorrelated 12-Gb/s PRBS sequences, measurement results included in this paper have been obtained at only 5 Gb/s due to test setup limitations. The prototype employs a CMOS latch optimized to operate at frequencies close to the of the process and a current-mode logic (CML) MUX with modified active inductor loads for better high-speed large-signal behavior. In order to reduce the power consumption, a quarter-clock rate linear feedback shift register (LFSR) core in a power-efficient parallel architecture has been implemented to minimize the use of power-hungry, high-speed circuitry. Further power reduction has been achieved through the clever partitioning of the system into static logic and CML. In addition, the prototype design produces three uncorrelated 12-Gb/s data streams from a single quarter-rate LFSR core, thereby amortizing the power across multiple channels which lowers the power per channel by 3 times. The total measured power consumption at 5 Gb/s is 131 mW per lane and the calculated figure of merit per lane is 0.84 pJ/bit, which is significantly better than previously published designs.     

Analysis and Design of a Chip Filter With Low Insertion Loss and Two Adjustable Transmission Zeros Using 0.18- $mu{hbox{m}}$ CMOS Technology

This paper presents the structure of a high-selectivity bandpass filter that is fabricated on low-resistivity silicon substrate with a commercial CMOS technology. The filter is constructed using crossed coplanar waveguide (CPW) lines and metal–insulator–metal capacitors to ensure that it has the desired passband characteristics. An adjustable capacitor between the input and output ports is employed to form a capacitive cross-coupled path, yielding two transmission zeros in the lower and upper stopbands, respectively. Additionally, the coupling mechanism can be modified by turning on or off the gate of an nMOS transistor to adjust the positions of the transmission zeros by applying an externally controlled voltage. To obtain a low passband loss and to minimize the chip size, high-impedance CPW transmission lines are adopted. Our analysis indicates that the CPW line possesses more advantages than the preferred stacked-ground CPW line for constructing the proposed filter. A very compact $X$ -band experimental prototype with a size of ${hbox{0.88}}times {hbox{0.54}} {hbox{mm}}^{2}$ was designed and fabricated. The measurements reveal an insertion loss of less than 3.2 dB in the passband, which is from 10.6 to 12.7 GHz, and rejection levels greater than 35 dB at the designed frequencies of transmission zeros. Moreover, the lower and upper transmission zeros can be shifted from 5 to 6.5 GHz and from 18 to 21.4 GHz, respectively, by changing the controlled voltage.      

A 0.18-$muhbox{m}$ CMOS GFSK Analog Front End Using a Bessel-Based Quadrature Discriminator With On-Chip Automatic Tuning

A fully integrated 2-MHz Gaussian frequency-shift keying (GFSK) analog front end for low-IF receivers is presented. The analog GFSK demodulation uses a Bessel-based quadrature discriminator and a differentiator-based data decision circuit, eliminating the need for analog–digital converters while enabling high sensitivity and large frequency offset tolerance. The analog front end consists of a fifth-order Butterworth low-pass prefilter, a seven-stage limiter, a quadrature discriminator with a fourth-order Bessel phase-shift network, a fourth-order Butterworth low-pass postfilter, and a differentiator-based data decision circuit. The prefilter, Bessel phase shifter, postfilter, and differentiator are built using identical $Gm{-}C$ cells and tuned across process variations with a single master–slave phase-locked loop. The GFSK analog front end is implemented in a 1.8-V 0.18-${rm mu}hbox{m}$ CMOS process, recovering 1-Mb/s input data from a 2-MHz GFSK signal with maximum frequency deviation of $pm$160-kHz, frequency offset tolerance from $-$ 38% to $+$ 47%, and input sensitivity of $-$53 dBm and consuming 7 mA of current.      

A Low-Noise and Low-Power Frequency Synthesizer Using Offset Phase-Locked Loop in 0.13-$mu{rm m}$ CMOS

In this letter, a fractional-N frequency synthesizer based on an offset phase-locked loop (OPLL) architecture is presented. The proposed synthesizer achieves low-noise as the two low-pass filters that are inherent in the OPLL highly suppresses the quantization noise from the delta-sigma modulator. In addition, it consumes low power by employing charge-recycling technique in the sub-PLL. A prototype synthesizer implemented in 0.13 $mu{rm m}$ CMOS process achieves 9 dB of noise reduction compared to a conventional PLL while consuming 3.2 mW of power.