SiC MOSFET单粒子漏电退化的影响因素

高压功率器件是未来航天器进一步发展的关键,对SiC金属-氧化物-半导体场效应晶体管(MOSFET)等高压大功率器件的抗辐射研究亟待突破。在不同偏置条件下对器件的单粒子效应(SEE)进行实验,结果表明,SiC MOSFET单粒子漏电退化效应与漏源电压、离子注量以及反向栅源电压呈正相关。为进一步研究SiC MOSFET单粒子效应机理,结合实验数据进行TCAD仿真,发现器件发生单粒子效应时存在两种失效模式,第一种失效模式与Si基MOSFET类似,而第二种失效模式与SiC器件的特有结构密切相关,容易形成更高的分布电压,导致栅氧化层烧毁失效。该结果为抗辐照加固器件的研究提供了理论支撑。     

埋栅型SIT和VDMOS的单粒子烧毁效应对比研究

对埋栅型静电感应晶体管(SIT)和垂直双扩散MOSFET(VDMOS)的抗单粒子烧毁(SEB)能力进行了仿真对比研究。利用Medici软件,仿真得到两种器件发生SEB效应前后的漏极电流响应和发生单粒子烧毁效应的临界漏极偏压。仿真结果表明,SIT与VDMOS两种器件常态击穿分别为580 V和660 V,在栅极关断电压为-10 V下,SIT的单粒子烧毁效应临界漏极电压为440 V,远高于VDMOS关断时230 V的临界漏极电压;SIT发生SEB效应时的漏极电流数量级为10-3 A/μm,而VDMOS发生SEB效应时的漏极电流数量级为10-4 A/μm,SIT在抗SEB效应方面比VDMOS具有更大的优势。同类研究少见文献报道。对埋栅SIT样品进行了试制,样品击穿电压为530 V。     

SiC JBS二极管和SiC MOSFET的空间辐照效应及机理

基于第六代650 V 碳化硅结型肖特基二极管(SiC JBS Diode)和第三代900 V 碳化硅场效应晶体管(SiC MOSFET),开展SiC功率器件的单粒子效应、总剂量效应和位移损伤效应研究。20~80 MeV质子单粒子效应实验中,SiC功率器件发生单粒子烧毁(SEB)时伴随着波浪形脉冲电流的产生,辐照后SEB器件的击穿特性完全丧失。SiC功率器件发生SEB时的累积质子注量随偏置电压的增大而减小。利用计算机辅助设计工具(TCAD)开展SiC MOSFET的单粒子效应仿真,结果表明,重离子从源极入射器件时,具有更短的SEB发生时间和更低的SEB阈值电压。栅-源拐角和衬底-外延层交界处为SiC MOSFET的SEB敏感区域,强电场强度和高电流密度的同时存在导致敏感区域产生过高的晶格温度。SiC MOSFET在栅压偏置(U_GS=3 V,U_DS=0 V)下开展钴源总剂量效应实验,相比于漏压偏置(U_GS=0 V,U_DS=300 V)和零压偏置(U_GS=U_DS=0 V),出现更严重的电学性能退化。利用中带电压法分析发现,栅极偏置下氧化层内的垂直电场提升了陷阱电荷的生成率,加剧了阈值电压的退化。中子位移损伤会导致SiC JBS二极管的正向电流和反向电流减小。在漏极偏置下进行中子位移损伤效应实验,SiC MOSFET的电学性能退化最严重。该研究为空间用SiC器件的辐射效应机理及抗辐射加固研究提供了一定的参考和支撑。     

功率VDMOSFET单粒子效应研究

阐述了空间辐射环境下n沟功率VDMOSFET发生单粒子栅穿(SEGR)和单粒子烧毁(SEB)的物理机理。研究了多层缓冲局部屏蔽抗单粒子辐射的功率VDMOSFET新结构及相应硅栅制作新工艺。通过对所研制的漏源击穿电压分别为65V和112V两种n沟功率VDMOS-FET器件样品进行锎源252Cf单粒子模拟辐射实验,研究了新技术VDMOSFET的单粒子辐射敏感性。实验结果表明,两种器件样品在锎源单粒子模拟辐射实验中的漏源安全电压分别达到61V和110V,验证了新结构和新工艺在提高功率VDMOSFET抗单粒子效应方面的有效性。     

高耐压Si基GaN功率电子器件

基于Si基GaN HEMT材料制作了击穿电压530V、无场板的功率电子器件。器件制作工艺与现有GaN微波功率器件工艺兼容。研究了器件栅漏间距与击穿电压的关系。器件栅宽为100μm,栅漏间距为15μm时,得到的GaN HEMT器件击穿电压530V,最大电流密度536mA/mm。器件的特征通态电阻为1.54mΩ·cm2,是相同击穿电压Si MOSFET器件特征通态电阻的二十五分之一。所制作的6mm栅宽器件击穿电压400V,输出电流2A。该器件的研制为制作低成本GaN HEMT功率器件奠定了基础。     

无结器件的单粒子辐射效应

介绍了一种新型沟道非均匀掺杂的双栅无结金属氧化物半导体场效应晶体管(MOSFET)。采用Sentaurus TCAD仿真软件对不同沟道掺杂浓度(NSC)的沟道非均匀掺杂双栅无结MOSFET和传统双栅无结MOSFET进行了电特性与单粒子辐射效应对比研究,并分析了不同源端沟道掺杂与源端沟道长度(LSC)下新型双栅无结MOSFET的单粒子辐射特性。仿真结果表明,新型双栅无结MOSFET的电学特性与传统双栅无结MOSFET相差不大,但在抗单粒子辐射方面具有优良的性能,在受到单粒子辐射时,可有效降低沟道内电子-空穴对的产生概率,漏极电流与收集电荷都低于传统无结器件,同时还可以降低寄生三极管效应对器件的影响。     

新型的低高压MOS接口电路

本文介绍一种由八个高压MOS器件组成的低高压MOS接口电路.它采用与目前国际上先进的NMOS大规模集成电路工艺技术完全兼容的N阱硅栅等平面CMOS工艺,而不需要附加任何工艺步骤.本文描述了高压MOS器件的物理模型,介绍了器件结构和工艺设计,并给出了高压MOS器件的漏击穿电压时沟道长度、漂移区长度、离子注入剂量和延伸源场极的关系的实验结果.这种高压MOS器件的漏击穿电压最大可达400V(在零栅偏压时),最大饱和漏电流可达35mA(在栅压为10V时),而导通电阻低到600(?)(在栅压为10V时).     

基于锎源的N沟道VDMOS器件单粒子效应研究

分析了N沟道VDMOS器件的单粒子辐射损伤机理和损伤模式,讨论了VDMOS器件的单粒子辐射加固措施。使用锎源,对采取了加固措施的一款200V高压N沟道VDMOS器件进行单粒子效应试验研究。对比分析了不同漏源电压和栅源电压以及不同真空度对VDMOS单粒子效应的影响,可为VDMOS器件的单粒子辐射加固、试验验证及应用提供参考。     

基于锎源的N沟道VDMOS器件单粒子效应研究

分析了N沟道VDMOS器件的单粒子辐射损伤机理和损伤模式,讨论了VDMOS器件的单粒子辐射加固措施。使用锎源,对采取了加固措施的一款200 V高压N沟道VDMOS器件进行单粒子效应试验研究。对比分析了不同漏源电压和栅源电压以及不同真空度对VDMOS单粒子效应的影响,可为VDMOS器件的单粒子辐射加固、试验验证及应用提供参考。     

高压VDMOS器件的研制及其抗辐照特性研究

利用SILVACO工艺模拟软件和器件模拟软件以及L—Edit版图设计工具,我们对一款高压VDMOS功率器件进行了模拟仿真和优化设计。利用自主开发的VDMOS工艺流程完成了器件的实际流片。测试结果表明,器件的源漏击穿电压达到600V以上,导通电阻小于2．5Ω,跨导为4S,栅一源泄漏电流约为±100nA,零栅电压时的漏一源泄漏电流约为10υA,二极管正向压降约为1．2V。采用二维器件模拟仿真工具以及相关物理模型对所研制的高压VDMOS器件的SEB和SEGR效应进行了分析,并通过对所研制的器件样片采用钴-60y射线源进行辐照实验,研究了在一定剂量率、不同总剂量水平下辐照对所研制的高压VDMOS器件相关电学参数的影响。     

Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study

The novel features of an asymmetric double gate single halo (DG-SH) doped SOI MOSFET are explored theoretically and compared with a conventional asymmetric DG SOI MOSFET. The two-dimensional numerical simulation studies demonstrate that the application of single halo to the double gate structure results in threshold voltage roll-up, reduced DIBL, high drain output resistance, kink free output characteristics and increase in the breakdown voltage when compared with a conventional DG structure. For the first time, we show that the presence of single halo on the source side results in a step function in the surface potential, which screens the source side of the structure from the drain voltage variations. This work illustrates the benefits of high performance DG-SH SOI MOS devices over conventional DG MOSFET and provides an incentive for further experimental exploration.     

A novel technique to determine the gate and drain bias dependentseries resistance in drain engineered MOSFETs using one single device

A new measurement method is explained for the extraction of the source and drain series resistance of drain engineered MOSFETs from their low frequency ac characteristics as a function of gate and drain bias using only one single MOSFET. Experimental results indicate, the effect of drain voltage dependent series resistance is relevant both in the ohmic and in the saturation region of the MOSFET. In addition the new measurement method is extended in such a way that it can be used to measure the series resistance as a function of gate bias only at low drain bias. Comparison of this single transistor measurement technique with other methods, needing a set of identical transistors with different channel lengths, shows that our method gives equal results. Finally attention is also given to the modeling of the series resistance in the ohmic and saturation region. For both regions simple, accurate compact model expressions have been derived     

SEGR- and SEB-hardened structure with DSPSOI in power MOSFETs

Single event irradiation-hardened power MOSFET is the most important device for DC/DC converter in space environment application.Single event gate rupture (SEGR) and single event burnout (SEB),which will degrade the running safety and reliability of spacecraft,are the two typical failure modes in power MOSFETs.In this paper,based on recombination mechanism of interface between oxide and silicon,a novel hardened power MOSFETs structure for SEGR and SEB is proposed.The structure comprises double stagger partial silicon-on-insulator (DSPSOI) layers.Results show that the safety operation area (SOA) of a 130 V N-channel power MOSFET in single event irradiation environment is enhanced by up to 50％ when the linear-energy-transfer value of heavy ion is a constant of 98 MeV.cm2/mg in the whole incident track,and the other parameters are almost maintained at the same value.Thus this novel structure can be widely used in designing single event irradiation-hardened power MOSFETs.     

一种200V/100A VDMOS器件开发

分析了功率MOSFET最大额定电流与导通电阻的关系,讨论了平面型中压大电流VDMOS器件设计中导通电阻、面积和开关损耗的折衷考虑,提出了圆弧形沟道布局以增大沟道宽度,以及栅氧下部分非沟道区域采用局域氧化技术以减小栅电容的方法,并据此设计了一种元胞结构。详细论述了器件制造过程中的关键工艺环节,包括栅氧化、光刻套准、多晶硅刻蚀、P阱推进等。流水所得VDMOS实测结果表明,该器件反向击穿特性良好,栅氧耐压达到本征击穿,阈值电压2.8V,导通电阻仅25mΩ,器件综合性能良好。     

A three-terminal intelligent power MOSFET with built-in reversebattery protection for automotive applications

An intelligent power MOSFET with built-in reverse battery protection, which is important for automotive power switches, has been developed. The protection is accomplished by integrating an additional power MOSFET in series with a power MOSFET and the control circuit of the additional power MOSFET. The reverse battery protection is achieved without using external control signals. The positive drain breakdown voltage for the proposed MOSFET is 71 V and the negative drain current at a drain voltage of -16 V is only -750 μA. The on-state resistance is 170 mΩ. This new intelligent power MOSFET can replace the conventional three-terminal power MOSFET's used in automotive applications     

0.5μm部分耗尽SOI MOSFET中的寄生双极效应

0.5μm部分耗尽SOI MOSFET的寄生双极效应严重影响了SOI器件和电路的抗单粒子和抗瞬态γ辐射能力。文中显示,影响0.5μm部分耗尽SOI NMOSFET寄生的双极器件特性的因素很多,包括NMOSFET的栅上电压、漏端电压和体接触等,尤其以体接触最为关键。在器件处于浮体状态时,0.5μm SOI NMOSFET的寄生双极器件很容易被触发,导致单管闭锁。因此,在设计抗辐射SOI电路时,需要尽量降低SOI NMOSFET寄生双极效应,以提高电路的抗单粒子和抗瞬态γ辐射能力。     

High-Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1 A/mm

High-performance inversion-type enhancement- mode (E-mode) n-channel In_0.65Ga_0.35As MOSFETs with atomic-layer-deposited Al₂O₃ as gate dielectric are demonstrated. A 0.4-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 10 nm shows a gate leakage current that is less than 5 times 10^-6 A/cm² at 4.0-V gate bias, a threshold voltage of 0.4 V, a maximum drain current of 1.05 A/mm, and a transconductance of 350 mS/mm at drain voltage of 2.0 V. The maximum drain current and transconductance scale linearly from 40 mum to 0.7 mum. The peak effective mobility is ~1550 cm²/V ldr s at 0.3 MV/cm and decreases to ~650 cm²/V ldr s at 0.9 MV/cm. The obtained maximum drain current and transconductance are all record-high values in 40 years of E-mode III-V MOSFET research.     

基于HfO2栅介质的Ga2O3 MOSFET器件研制

采用金属有机化学气相沉积(MOCVD)方法在(010) Fe掺杂半绝缘Ga2O3同质衬底上外延得到n型β-Ga2O3薄膜材料,材料结构包括400 nm的非故意掺杂Ga2O3缓冲层和40 nm的Si掺杂Ga2O3沟道层.基于掺杂浓度为2.0×1018 cm-3的n型β-Ga2O3薄膜材料,采用原子层沉积的25 nm的HfO2作为栅下绝缘介质层,研制出Ga2O3金属氧化物半导体场效应晶体管(MOSFET).器件展示出良好的电学特性,在栅偏压为8V时,漏源饱和电流密度达到42 mA/mm,器件的峰值跨导约为3.8 mS/mm,漏源电流开关比达到108.此外,器件的三端关态击穿电压为113 V.采用场板结构并结合n型Ga2O3沟道层结构优化设计能进一步提升器件饱和电流和击穿电压等电学特性.     

基于GaAs PHEMT工艺的60~90GHz功率放大器MMIC

研制了一款60~90 GHz功率放大器单片微波集成电路(MMIC),该MMIC采用平衡式放大结构,在较宽的频带内获得了平坦的增益、较高的输出功率及良好的输入输出驻波比(VSWR)。采用GaAs赝配高电子迁移率晶体管(PHEMT)标准工艺进行了流片,在片测试结果表明,在栅极电压为-0.3 V、漏极电压为+3 V、频率为60~90 GHz时,功率放大器MMIC的小信号增益大于13 dB,在71~76 GHz和81~86 GHz典型应用频段,功率放大器的小信号增益均大于15 dB。载体测试结果表明,栅极电压为-0.3 V、漏极电压为+3 V、频率为60~90 GHz时,该功率放大器MMIC饱和输出功率大于17.5 dBm,在71~76 GHz和81~86 GHz典型应用频段,其饱和输出功率可达到20 dBm。该功率放大器MMIC尺寸为5.25 mm×2.10 mm。