Photorefractive effects in proton exchanged LiTaO3optical waveguides

A circuit model is proposed to describe photorefractive effects in LiNbO₃/LiTaO₃ channel waveguides at any intensity level. Capacitive charge storage at the waveguide boundaries is assumed to be provided by trapping states associated with photoconductivity. A consequence of this model is that photoconductive transients are independent of optical intensity at low intensity levels. Photovoltaic and photoconductive effects in proton exchange LiTaO₃ channel waveguides were experimentally investigated. Dark conductivities of 2×10^-15 to 2 ×10^-14(Ω-cm)^-1 were extrapolated from photoconductivities up to 2×10^-13 (Ω-cm)^-1 for power levels of 0.1 to 3 mW. Large DC voltage dependent effects on the conductivity were observed. Straight channel waveguides were observed to be free of photovoltaic effects for output power levels below 35-75 mW     

A multimode digital detector readout for solid-state medicalimaging detectors

A multipurpose digital detector readout for medical imaging applications is presented. The readout is capable of measuring both current and charge, allowing a single detector array to perform imaging functions previously accomplished with two separate machines. The circuit employs a variable rate ΣΔ analog-to-digital converter (ADC) to measure current over a 130-dB dynamic range in a 1 kHz band and resolve charge pulses down to 360 e^- at 100 000 events/s. Detector currents of up to 7 μA and charge pulses as large as 25 fC can be measured. A low-noise charge sensing amplifier (CSA) is combined with digital pulse shaping to optimize the noise performance and flexibility of the charge measurements. Fabricated in an 1.2 μm complimentary metal-oxide-semiconductor (CMOS), the circuit occupies 1.5 mm² and dissipates 11 mW/channel from a 5 V supply     

Noise in buried channel charge-coupled devices

In this paper we discuss the noise measured at the output of a buried channel charge-coupled device (BCCD) linear shift register. The measured noise arises from four sources; the electrical insertion of signal charge, the output amplifier, dark current, and bulk state trapping. In making these measurements the concept of correlated double sampling was used in an output circuit which had a noise level which was equivalent to less than 3O noise electrons. A critical component in this output was a low noise MOSFET which was achieved by use of the buried channel technology. A low noise input structure for electrical insertion of signal charge was used which introduced a signal which had a noise level which ranged from less than 10 e^-to as high as 60 e^-depending on the size of the signal charge. The dark current noise was found to be well characterized as a shot noise and levels on the order of 20 e^-were measured. The above low noise levels made possible direct measurement of the noise due to bulk state trapping, and depending on the signal size and clock rate noise levels were measured which ranged from less than 10 to over 100 noise electrons. One of the most important bulk traps was found to be due to gold impurities which had a density of ∼ 2 × 10¹¹cm^-3.     

17 GHz broadband amplifier with 25 dB gain using a 0.3 μmAlGaAs/GaAs/AlGaAs HEMT technology

A broadband amplifier chip based on AlGaAs/GaAs/AlGaAs quantum well FETs with 0.3 μm gate length has been designed and fabricated. The amplifier can be operated with single-ended or differential inputs with an input resistance of 50 Ω. The output signals are differential with both internal load resistances at 100 Ω, the chip area is 1×1 mm², and the power consumption is ~375 mW     

A BiCMOS front-end system with binary delay line for capacitivedetector read-out

As part of the entire readout chip, a low-power high-gain transresistance amplifier has been developed, followed by a high-speed, low-power small offset comparator and a binary delay line. The amplifier is balanced, fully differential in circuit topology, and symmetrical in layout, making it radiation tolerant and relatively insensitive to varying magnetic fields. Also, the comparator is fully symmetrical with a balanced input stage. Before irradiation (pre-rad) the transresistance amplifier has a measured differential gain of 110 mV/4 fC, an average 10/90% rise time (t_10/90%) of 20 to 50 ns depending on the bias conditions, a noise figure of 433⊕93.(C_t)^1.08 (where the symbol ⊕ stands for √(()²+() ²)) electrons (e^-), and a power consumption of 750 μW. The comparator uses bipolar transistors in the regenerative stage resulting in a small offset, a sensitivity <1.5 mV, and a power consumption of ≈350 μW at 40 MHz. The maximum pre-rad frequency at which the comparator is still functioning correctly is ≈100 MHz. Pre-rad, the binary delay line has a delay of 2.1 μs at 40 MHz and a power consumption of ≈450 μW/channel for a four-channel design. The complete readout channel-amplifier, comparator, and binary delay line-consumes ≈1.5 mW. The entire readout system was implemented in the radiation-hard 0.8-μm SOI-SIMOX BiCMOS-PJFET technology of DMILL     

A high-linearity 50-Ω CMOS differential driver for ISDNapplications

A CMOS differential line-driver amplifier that uses positive feedback in the input stage to give transconductance multiplication and pole-zero doublet insertion is reported. The gain-bandwidth product at 60 kHz is 30 MHz and the unity-gain frequency is 2.7 MHz. The circuit operates from a single 5-V power supply and can achieve a total harmonic distortion (THD) of -78 dB for a 6-V_pp differential output signal at 40 kHz and for a load of 100 Ω and/or 150 pF. For the same measuring condition but with a load of 50 Ω and/or 150 pF, the THD is -73 dB. A power supply rejection of more than 76 dB up to 150 kHz was obtained. The chip occupies an area of 1200 mil² in a 1.5-μm CMOS technology and dissipates 20 mW     

High-performance CMOS buffered gate modulation input (BGMI) readoutcircuits for IR FPA

A new CMOS current readout structure for the infrared (IR) focal-plane-array (FPA), called the buffered gate modulation input (BGMI) circuit, is proposed in this paper. Using the technique of unbalanced current mirror, the new BGMI circuit can achieve high charge sensitivity with adaptive current gain control and good immunity from threshold-voltage variations. Moreover, the readout dynamic range can be significantly increased by using the threshold-voltage-independent current-mode background suppression technique. To further improve the readout performance, switch current integration techniques, shared-buffer biasing technique, and dynamic charging output stage with the correlated double sampling circuit are also incorporated into the BGMI circuit. An experimental 128×128 BGMI readout chip has been designed and fabricated in 0.8 μm double-poly-double-metal (DPDM) n-well CMOS technology. The measurement results of the fabricated readout chip under 77 K and 5 V supply voltage have successfully verified both readout function and performance improvement. The fabricated chip has the maximum charge capacity of 9.5×10⁷ electrons, the transimpedance of 2.5×10⁹ Ω at 10 nA background current, and the arrive power dissipation of 40 mW. The uniformity of background suppression currents can be as high as 99%. Thus, high injection efficiency, high charge sensitivity, large dynamic range, large storage capacity, and low noise can be achieved In the BGMI circuit with the pixel size of 50×50 μm². These advantageous characteristics make the BCMI circuit suitable for various IR FPA readout applications with a wide range of background currents     

1.57 μm strained-layer quantum-well GaInAlAs ridge-waveguidelaser diodes with high temperature (130°C) and ultrahigh-speed (17GHz) performance

The fabrication of GaInAlAs strained-layer (SL) multiple-quantum-well (MQW) ridge-waveguide (RW) laser diodes emitting at 1.57 μm is discussed. Due to an optimized layer structure, a very high characteristic temperature of 90 K was obtained. As a consequence for episide-up mounted devices, the maximum continuous wave (CW)-operation temperature is 130°C. At room temperature, a maximum output power of 47 mW was measured for 600-μm-long lasers with one high-reflection coated facet. The low series resistance of 4 Ω (2 Ω) for 200-μm-(400-μm)-long devices yields an ultrahigh 3-dB bandwidth of 17 GHz. These static and dynamic properties also result from a high internal quantum-efficiency of 0.83 and a high differential gain of 5.5×10^-15 cm²     

A new cryogenic CMOS readout structure for infrared focal planearray

A new current readout structure for the infrared (IR) focal-plane-array (FPA), called the switch-current integration (SCI) structure, is presented in this paper. By applying the share-buffered direct-injection (SBDI) biasing technique and off focal-plane-array (off-FPA) integration capacitor structure, a high-performance readout interface circuit for the IR FPA is realized with a pixel size of 50×50 μm². Moreover, the correlated double sampling (CDS) stage and dynamic discharging output stage are utilized to improve noise and speed performance of the readout structure under low power dissipation. In experimental SCI readout chip has been designed and fabricated in 0.8-μm double-poly-double-metal (DPDM) n-well CMOS technology. The measurement results of the fabricated readout chip at 77 K with 4 and 8 V supply voltages have successfully verified both the readout function and the performance improvement. The fabricated chip has a maximum charge capacity of 1.12×10⁸ electrons, a maximum transimpedance of 1×10⁹ Ω, and an active power dissipation of 30 mW. The proposed CMOS SCI structure can be applied to various cryogenic IR FPA's     

A CMOS low-distortion fully differential power amplifier withdouble nested Miller compensation

A four-stage fully differential power amplifier using a double-nested Miller compensated structure is presented. The multiple-loop configuration used results in a lower harmonic distortion, at least in the audio band, compared to conventional three-stage amplifiers with nested Miller compensation. Design criteria and stability conditions for good stability of amplifiers using a multiple- (greater than two) loop topology are presented. The amplifier operates with a single power supply which has a minimum value of 3 V. With a 5-V supply, power dissipation is 10 mW and total harmonic distortion (THD) is -83 dB for a -V_p-p differential output signal at 10 kHz and a load of 50 Ω. With an 8 Ω load and for a 10-kHz, 4-V _p-p output signal, THD is -68 dB. The chip area is 0.625 mm ² in a 1.5-μm single-poly, double-metal, n-well CMOS technology     

High-gain transimpedance amplifier in InP-based HBT technology forthe receiver in 40-Gb/s optical-fiber TDM links

A monolithic integrated transimpedance amplifier for the receiver in a 40-Gb/s optical-fiber TDM system has been fabricated in an InP-based HBT technology. Despite its high gain (transimpedance of 2 kΩ in the limiting mode, 10 kΩ in the linear mode) the complete amplifier was realized on a single chip. Clear output eye diagrams were measured up to 43 Gb/s under realistic driving conditions. The voltage swing of 0.6 V_pp at the differential 50 Ω output does not change within the demanded input dynamic range of 6 dB. At the upper input current level even 48 Gb/s were achieved. The power consumption is approximately 600 mW at a single supply voltage of -5.5 V     

A 10-b 50-MHz CMOS D/A converter with 75-Ω buffer

A 10-b 50-MHz digital-to-analog (D/A) converter for video applications that is based on a dual-ladder resistor string is presented. This approach allows the linearity requirements to be met without the need for selection or trimming. The D/A decoding scheme reduces the glitch energy, and signal-dependent switch signals reduce high-frequency distortion. The output buffer allows driving 1 V_pp to 75 Ω. The chip consumes 65 mW at maximum clock frequency and a full-swing output signal. The device is processed in a standard 1.6-μm CMOS process with a single 5-V supply voltage. The double-ladder architecture allows the requirements for small cell area and high linearity to be separated. Compensation techniques have been applied to reduce the second- and third-order distortion components; at 5-MHz signal frequency the total harmonic distortion is -53 dB     

Femto Joule logic circuit with enhancement-type Schottky barrier gate FET

As an approach to an advanced LSI logic, a high-speed and low-power femto-joule logic circuit has been developed by using an enhancement-type Schottky barrier gate FET (ESBT) with³¹P implanted channel layer. A direct coupled transistor logic (DCTL) was designed using ESBT and resistor as a basic logic circuit. To evaluate the dynamic performance of the logic circuit, a 15-stage ring oscillator with an output buffer was integrated on a chip. A power-delay product was found in the femto-joule range. The logic swing is about 0.4 V and typical noise margin is 30 percent of the logic swing. A high-speed (40 ns) and low-power (10 mW) 4 bit ALU has been developed by using DCTL, NOR gates. Furthermore, improving ESBT channel layer carrier profile to the higher carrier concentration and abruptly changing shallower carrier profile by³¹P and¹¹B double implantation resulted in advanced characteristics of ESBT and logic circuit using it as follows. ESBT transconductance was increased by a factor of two. Power-delay product reduced to 80 percent of that of logic circuit, using ESBT with³¹P single implanted channel layer, was satisfactorily confirmed, together with a circuit density as large as 300 gates/ mm².     

A high-efficiency vertical-cavity surface-emitting switching laserfabricated with post-growth cavity mode positioning

The first room-temperature continuous-wave (CW) operation of the double heterostructure optoelectronic switching laser implemented as a vertical-cavity laser is described. A deposited dielectric top reflector of SiO₂/TiO₂ allowed the use of a cavity etch back technique after the sample was grown, to position the cavity mode at the desired wavelength. Room temperature CW threshold currents as low as 4.8 mA for a 14-μm-diameter device were obtained with slope efficiencies of 0.45 mW/mA. The maximum CW output power was 2.5 mW and the resistivity was 4×10^-4 Ωcm²     

Large-swing CMOS buffer amplifier

A circuit configuration for a CMOS buffer amplifier is described. The circuit, which is an enhancement of a previously reported buffer amplifier, features a large output voltage swing and a well-controlled quiescent current. A buffer amplifier of this type has been implemented in a 1.5-μm CMOS technology. The prototype occupies an area of 275 mil². It works with a 5-V supply and can drive more than 4.2 V (peak to peak) in to 300 Ω with a total harmonic distortion of less than 0.025%     

A BiCMOS limiting amplifier for SONET OC-3

This paper presents a Synchronous Optical NETwork (SONET) OC-3 155.52 Mb/s limiting amplifier, which is implemented in a 1.0 μm double-poly double-metal N-well BiCMOS technology. Composed of amplifier cells, a slicer, an output driver, and offset cancellation circuits, this limiting amplifier allows an input dynamic range of 36 dB (6 mV_pp~400 mV_pp) and provides a constant output 1 V _pp across a 50 Ω load for long-haul 40 km application. The active area of this limiting amplifier is 0.8 mm×3.0 mm. It consumes 130 mW from a single -5 V supply voltage     

Comparison of self-aligned and non-self-aligned GaAs E/D MESFETs

The device characteristics and circuit performance of self-aligned GaAs E/D-MESFETs have been compared. The fabrication process for both devices is discussed. Electrical measurements across a 2-in wafer showed that an average self-aligned 40-μm-wide, 1-μm-long enhancement device has transconductance of 275±17 mS/mm, an intrinsic K -value of 16.3±2.7 mS/V, a series resistance of 0.88±0.1 Ω-mm, and a threshold deviation of 28 mV. Corresponding data for the non-self-aligned devices were 191±19 mS/mm, 10.3±1.4 mS/V, 1.2±0.2 Ω-mm, and 45 mV, respectively. An ECL-compatible 1-kb static RAM and a 4-kb static RAM were fabricated using both self-aligned and non-self-aligned processes for comparison. Using the self-aligned process, the power consumption of the 1-kb SRAM was 230 mW, compared to 530 mW for the non-self-aligned SRAM, while access times remained the same. Typical access times for self-aligned 4-b SRAM devices ranged from a minimum of 2.8 ns to a maximum of 3.8 ns. This 1-ns range is considerably less than that of a typical non-self-aligned device with 2.5 ns of access time scatter     

Parallel optical interconnection for uncoded data transmission with1 Gb/s-per-channel capacity, high dynamic range, and low powerconsumption

The design, realization, and characterization of a multichannel dc-coupled ECL-voltage compatible parallel optical interconnection with a bit rate of up to 1 Gb/s-per-channel is reported. The transmitter module consists of an array of laser diodes with low threshold currents and the 50 Ω matching network, the receiver module of a photo diode array and an amplifier array. All the opto-electronic and electronic components are fabricated as arrays with a pitch of 250 μm. The total power consumption is 110 mW per channel, For a BER <10¹⁴ the dynamic range is 15 dB for a bit rate per channel of 200 Mb/s, 13 dB for 630 Mb/s, and 8 dB for 1 Gb/s. The channel crosstalk is below -48 dB (electrical). The size of the opto-electronic parts (12 channels, without electrical connectors) is only 10 mm (length)×5 mm (width)×4 mm (height)     

50 J discharge-pumped XeCl laser

An X-ray preionized XeCl laser with a wide aperture of 10×10 cm² is described. The density for preionization electrons is estimated from an X-ray energy distribution to be greater than 6×10⁹ cm^-3 under operational gas conditions. In high pressure operation at 4500 torr, sufficient preionization has led to successful discharge-breakdown at a low E/N of 6.4×10^-17 V-cm², resulting in a high electrical efficiency of 3.1% with an output energy of 17.6 J. An output energy of 50 J in an 85-ns (FWHM) optical pulse has been extracted from an active volume of about 10:1 for a pulse-forming-line (PFL) voltage of 400 kV. The effects of impedance transformation of a pulse-transmission-line (PTL) following the PFL have been investigated using two types of PTL with output impedances of 0.26 and 0.48 Ω     

40 Gbit/s limiting output buffer in 80 nm CMOS

A 40 Gbit/s 1V limiting output buffer for an AC-coupled 50 /spl Omega/ load with a differential output swing of 660 mV and a gain of 18 dB is presented. A power consumption of only 24 mW and a simulated risetime of 11 ps are achieved by means of a systematic buffer optimisation.