一种光接收机中的高增益宽动态范围跨阻放大器

As the front-end preamplifiers in optical receivers, transimpedance amplifiers （TIAs） are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time, the TIAs should possess a wide dynamic range （DR） to prevent the circuit from becoming saturated by high input currents. Based on the above, this paper presents a CMOS transimpedance amplifier with high gain and a wide DR for 2.5 Gbit/s communications. The TIA proposed consists of a three-stage cascade pull push inverter, an automatic gain control circuit, and a shunt transistor controlled by the resistive divider. The inductive-series peaking technique is used to further extend the bandwidth. The TIA proposed displays a maximum transimpedance gain of 88.3 dBΩ with the -3 dB bandwidth of 1.8 GHz, exhibits an input current dynamic range from 100 nA to 10 mA. The output voltage noise is less than 48.23 nV/√Hz within the -3 dB bandwidth. The circuit is fabricated using an SMIC 0.18 μm 1P6M RFCMOS process and dissipates a dc power of 9.4 mW with 1.8 V supply voltage.     

1.25-Gb/s regulated cascode CMOS transimpedance amplifier for Gigabit Ethernet applications

A transimpedance amplifier (TIA) has been realized in a 0.6-/spl mu/m digital CMOS technology for Gigabit Ethernet applications. The amplifier exploits the regulated cascode (RGC) configuration as the input stage, thus achieving as large effective input transconductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. Test chips were electrically measured on a FR-4 PC board, demonstrating transimpedance gain of 58 dB/spl Omega/ and -3-dB bandwidth of 950 MHz for 0.5-pF photodiode capacitance. Even with 1-pF photodiode capacitance, the measured bandwidth exhibits only 90-MHz difference, confirming the mechanism of the RGC configuration. In addition, the noise measurements show average noise current spectral density of 6.3 pA//spl radic/(Hz) and sensitivity of -20-dBm for a bit-error rate of 10/sup -12/. The chip core dissipates 85 mW from a single 5-V supply.     

1-Gb/s zero-pole cancellation CMOS transimpedance amplifier for Gigabit Ethernet applications

A zero-pole cancellation transimpedance amplifier (TIA) has been realized in 0.35 μm RF CMOS tech nology for Gigabit Ethernet applications. The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration. Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ω for 1.5 pF photodiode capaci tance, with a gain-bandwidth product of 3.4 THz·Ω. Even with 2 pF photodiode capacitance, the bandwidth exhibits a decline of only 300 MHz, confirming the mechanism of the zero-pole cancellation configuration. The input resis tance is 50 Ω, and the average input noise current spectral density is 9.7 pA/(Hz)~(1/2). Testing results shows that the eye diagram at 1 Gb/s is wide open. The chip dissipates 17 mW under a single 3.3 V supply.     

应用于千兆以太网的1-Gb/s 零极点对消CMOS跨阻放大器

A zero-pole cancellation transimpedance amplifier（TIA）has been realized in 0.35μm RF CMOS technology for Gigabit Ethernet applications.The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration.Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ωfor 1.5 pF photodiode capaci- tance,with a gain-bandwidth product of 3.4 THz·Ω.Even with 2 pF photodiode capacitance,the bandwidth exhibits a decline of only 300 MHz,confirming the mechanism of the zero-pole cancellation configuration.The input resis- tance is 50Ω,and the average input noise current spectral density is 9.7 pA/√ Hz.Testing results shows that the eye diagram at 1 Gb/s is wide open.The chip dissipates 17 mW under a single 3.3 V supply.     

20 mW 1.25 Gbit/s CMOS transimpedance amplifier with 30 dB dynamic range

A 1.25 Gbit/s transimpedance amplifier using a novel photodiode capacitance cancellation technique has been demonstrated in 0.35 mum CMOS technology. The transimpedance amplifier achieved a transimpedance gain of 17.1 kOmega as well as a wide dynamic range from +1 to -29 dBm while consuming only 20 mW from a 3 V supply     

带有电流监控的1.25Gbit/s CMOS跨阻放大器

文章提出一种速率为1.25 Gbit/s、具有可控电流监控的光纤通信用跨阻放大器(TIA)电路,该放大器可以通过拉电流和灌电流两种方式来检测电流监控的电流流向.设计使用的是0.18 μm的标准互补型金属氧化物半导体(CMOS)工艺.仿真结果表明,光电流在1 μA～1 mA范围内时,各种工艺条件下检测到的光电流误差均小于...     

A variable gain amplifier with 50-dB control range for 900-MHz applications

A variable gain amplifier for 900-MHz applications has been designed and fabricated in a BiCMOS process with f/sub T/ = 24 GHz. The amplifier has linear-in-dB gain control with a 50-dB control range. The maximum gain is 28 dB and the third-order output intercept point (OIP3) is 13.7 dBm. The gain is achieved in one gain stage with a cascoded output. The amplifier bias network and the gain-control circuitry are temperature compensated for temperature-independent gain at any gain setting. The bias network also uses a feedback loop to cancel out undesired low frequencies present at the radio-frequency input. The maximum output power is +10 dBm and the output 1-dB compression point is +8.7 dBm. Active chip area is 0.1 mm/sup 2/. The amplifier is packaged in a SOT-363 and consumes 30 mA from a 2.8-V supply.     

A high dynamic range ultralow-current-mode amplifier with pico-ampere sensitivity for biosensor applications

A novel ultralow-current-mode amplifier (ULCA) serving for on-chip biosensor signal pre-amplification in the integrated biosensing system (IBS) has been presented and verified in SMIC 0.18 μm CMOS technology by elaborately considering gain, bandwidth, noise, offset, and mismatch. The proposed ULCA solved the noise, bandwidth, and current headroom dilemma in the reported works, and can completely satisfy the specifications of IBS. It provides a current gain of 20 dB, 3 dB bandwidth of 7.03 kHz and input dynamic range of 20 bit, with only 1 nA of DC quiescent current, while the input offset current and noise current are less than 16.0 pA and 4.67 pArms, respectively.     

A CMOS readout amplifier for instrumentation applications

An integrated readout amplifier for instrumentation applications in smart sensor systems is presented. A fully integrated CMOS version of such an amplifier has been developed using switched-capacitor techniques. The amplifier system provides differential input capability, programmable amplification, clock generation, and low-pass filtering on the chip. The output signal is continuous in time and the system can be used without any of the special precautions necessary for sampled-data circuits. Emphasis was put on high PSRR (-63 dB at DC), low noise (10-μV_rms input equivalent wideband noise) and offset, low harmonic distortion, and small amplification error (<0.06% at 4 V_pp). To cover a large field of applications, only slightly different realizations can be used for capacitive sensors as well as for resistive sensor bridges     

A 50-MHz CMOS amplifier channel for a laser radar

An integrated CMOS amplifier channel consisting of a transimpedance preamplifier, postamplifiers, and gain control circuitry has been designed for the receiver of a pulsed time-of-flight laser radar. The measurement results, a total transimpedance ofZ _t 250 k with a bandwidth ofBW 65 MHz and an input-referred noise current ofi _ni 7 pA/Hz, show that a range measurement resolution of centimeter/decimeter class could be achieved by detecting the edge of the received laser pulse.     

Wideband high dynamic range CMOS variable gain amplifier for low voltage and low power wireless applications

A high frequency CMOS variable gain amplifier (VGA) employing a new gain stage cell is proposed. A design technique based on the proposed VGA enables enhancement of its operating frequency up to about 350 MHz with a gain control range of 84 dB. The power consumption of the VGA implemented using a 0.18 /spl mu/m CMOS standard process is about 3 mA at 1.8 V supply voltage.     

A CMOS differential buffer amplifier with accurate gain andclipping control

A CMOS fully differential buffer amplifier with accurate gain and clipping control is presented. The gain is made variable by controlling the amount of the feedback around the power amplifier by means of an additional gain control loop. A new clipping technique is used to control the clipping level of the amplifier. The amplifier is realized in a 1.2 μm CMOS process with a single 5 V power supply. Measurements confirm the presented techniques     

Design of a low-power 3.5-GHz broad-band CMOS transimpedance amplifier for optical transceivers

This paper describes a novel low-power low-noise CMOS voltage-current feedback transimpedance amplifier design using a low-cost Agilent 0.5-/spl mu/m 3M1P CMOS process technology. Theoretical foundations for this transimpedance amplifier by way of gain, bandwidth and noise analysis are developed. The bandwidth of the amplifier was extended using the inductive peaking technique, and, simulation results indicated a -3-dB bandwidth of 3.5 GHz with a transimpedance gain of /spl ap/60 dBohms. The dynamic range of the amplifier was wide enough to enable an output peak-to-peak voltage swing of around 400 mV for a test input current swing of 100 /spl mu/A. The output noise voltage spectral density was 12 nV//spl radic/Hz (with a peak of /spl ap/25 nV//spl radic/Hz), while the input-referred noise current spectral density was below 20 pA//spl radic/Hz within the amplifier frequency band. The amplifier consumes only around 5 mA from a 3.3-V power supply. A test chip implementing the transimpedance amplifier was also fabricated using the low-cost CMOS process.     

A linear and wide dynamic range transimpedance amplifier with adaptive gain control technique

A linear and wide dynamic range transimpedance amplifier (TIA) for the pulsed time-of-flight imaging LADAR application has been designed and simulated in a 0.18 μm 3.3 V CMOS technology. Specific design techniques, including adaptive gain control technique to widen linear dynamic range, pseudo-differential structure of the front end to decrease the common-mode noise and noise minimization to improve SNR, have been proposed to achieve challenging designs goals with linear dynamic range of 5000:1, high transimpedance gain of 89 dB Ω, bandwidth up to 150 MHz, equivalent input-referred noise current less than 8 \({\text{pA}}/\sqrt {\text{Hz}}\), in 2 pF photodiode parasitic capacitance. The proposed TIA consumes 165 mW with 3.3 V power supply.     

A CMOS vector lock-in amplifier for sensor applications

The design of an integrated lock-in amplifier is discussed, specifically conceived for the detection of low-level signals at a harmonic of the drive frequency in magnetically excited resonant structures. The circuit includes in-phase and quadrature analogue signal processing channels, whose outputs feed an integrated ΣΔ analogue to digital converter. The circuit can be operated in different configurations, depending on the application requirements: in particular, by combining the digitized outputs of the two channels, vector operation can be obtained. The entire analogue chain, including the ΣΔ modulator, was designed using fully differential elaboration. The circuit was developed in a , dual poly-Si, four metal layers analogue CMOS technology with high resistivity poly-Si option. Circuit performance is discussed on the basis of transistor-level simulations and measurement results.     

A CMOS monolithic amplifier for cardiac EIT applications

Analog Integrated Circuits and Signal Processing - This paper presents a low-noise amplifier (LNA) with superior linearity for ultra-wideband (UWB) purposes. Linearity is a significant parameter...     

A compact rail-to-rail CMOS buffer amplifier with very low quiescent current

In this work, a very compact, rail-to-rail, high-speed buffer amplifier for liquid crystal display (LCD) applications is proposed. Compared to other buffer amplifiers, the proposed circuit has a very simple architecture, occupies a small number of transistors and also has a large driving capacity with very low quiescent current. It is composed of two complementary differential input stages to provide rail-to-rail driving capacity. The push–pull transistors are directly connected to the differential input stage, and the output is taken from an inverter. The proposed buffer circuit is laid out using Mentor Graphics IC Station layout editor using AMS 0.35 μm process parameters. It is shown by post-layout simulations that the proposed buffer can drive a 1 nF capacitive load within a small settling time under a full voltage swing, while drawing only 1.6 μA quiescent current from a 3.3 V power supply.     

A novel tunable gain CMOS buffer amplifier for large resistive loads

An all-OTA analog buffer amplifier configuration capable of driving large resistive loads is presented. The proposed configuration features high input swing, gain tunability, wide-bandwidth, and low design complexity. The concept is validated with simulation results in Cadence Virtuoso using SCL 0.18-μm technology parameters. Using a ±0.9 V power supply, the buffer with a gain of 1, can drive a 1 V_p−p sinusoid into a 50 Ω load with a THD of better than 0.015%, with a 3-dB bandwidth of 1.55 GHz and consumes 9 mW. The proposed configuration is demonstrated with gain values varying from 0.25 V/V to 5 V/V and with different load values 16 Ω to 5.6 kΩ. The voltage gain is tunable over more than a decade with reasonable power levels. With low-gain OTA, the proposed buffer configuration works well without any complex frequency compensation circuit that makes the all-OTA analog buffer amplifier configuration simple compared to the existing buffer amplifiers.     

A RGC-based,low-power,CMOS transimpedance amplifier for 10Gb/s optical receivers

ABSTRACT

In this paper, a new low-power transimpedance amplifier (TIA) based on a modified Regulated Cascode (RGC) circuit structure followed by a closed-loop post-amplifier is proposed for 10 Gb/s applications. The main objective of this work is to reduce the power consumption while, the frequency bandwidth of the proposed amplifier is increased considerably. The booster of a conventional RGC is modified by a cascoded transistor and its effect on the performance of the circuit is studied mathematically, which are verified by simulations. The bandwidth extension is occurred due to increasing the gain of the booster amplifier in the RGC stage, which isolates further the input capacitance and results in a reduced input resistance value hence, a higher input pole frequency is obtained in comparison with other conventional RGC structures. On the other hand, by using an active inductive peaking technique, the frequency of the output pole is also increased which results in a further extension of the frequency bandwidth for the proposed circuit. The proposed TIA is simulated using 90 nm CMOS technology parameters, which shows a 50.5 dBΩ transimpedance gain, 7.3 GHz frequency bandwidth and 1.22 µA_rms input referred noise value for only 1 mW of power consumption at 1.2 V supply voltage.     

A low-power low-noise CMOS amplifier for neural recording applications

There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff.