一种高电源抑制比的LDO电路的设计

电源抑制比（PSRR）反映的是电路对电源噪声的敏感程度,在电源管理电路中是极为重要的性能指标。总是希望有高的电源抑制比来抑制电源噪声对电路的影响。低压差线性稳压（LDO）电路中这个指标尤为重要,本文将设计一款具有高电源抑制比的低压差线性稳压器。     

Bang-Bang Control Class D Amplifiers: Total Harmonic Distortion and Supply Noise

The total harmonic distortion (THD) and the power supply noise, qualified by the power supply rejection ratio (PSRR) and by the power supply induced intermodulation distortion (PS-IMD), are recognized to be potential drawbacks of class D amplifiers. In this paper, analytical expressions for the THD, PSRR, and PS-IMD of the bang-bang control class D amplifier (bang-bang amp) are derived; the bang-bang amp is arguably the most power-efficient class D amp for low-voltage power-critical applications including hearing aids. Based on the derived expressions, the effects of important parameters on the THD, PSRR, and PS-IMD are investigated, providing good insight to the design of the bang-bang amp to meet given design specifications. The analytical analyses are verified by comparing them against HSPICE simulations and hardware measurements. The bang-bang amp is also compared against the prevalent pulsewidth modulation class D amp, and in most cases, the former is shown to possess superior parameters, including lower power dissipation and hardware advantages for low-voltage power-critical applications.     

一种高电源抑制比带隙基准电压源的设计

设计了一种基于反馈电路的基准电压电路。通过正、负两路反馈使输出基准电压获得了高交流电源抑制比(PSRR),为后续电路提供了稳定的电压。采用NPN型三极管,有效消除了运放失调电压对带隙基准电压精度产生的影响,并对电路进行温度补偿,大大减小了温漂。整个电路采用0.35μm CMOS工艺实现,通过spectre仿真软件在室温27℃、工作电压为4 V的条件下进行仿真,带隙基准的输出电压为1.28 V,静态电流为2μA,在-20~80℃范围内其温度系数约为18.9×10-6/℃,交流PSRR约为-107 dB。     

A micropower fourth-order elliptical switched-capacitor low-pass filter

A micropower fourth-order elliptical switched-capacitor (SC) low-pass filter for biomedical applications has been designed and measured. The charge transfer error of an SC integrator using a transconductance amplifier is discussed. Also first-order noise and PSRR calculations are performed and compared with the results of simulations and measurements. The measurements show that by careful optimization of the gain bandwidth, slew rate, and gain of the amplifiers, high-performance low-power SC filters can be constructed. The cutoff frequency of the filter is 5 kHz, the ripple in the passband is 0.27 dB, and stopband rejection is 49 dB. The power consumption of the filter is 190 /spl mu/W with /spl plusmn/2.5-V power supplies. The dynamic range of the filter is 75 dB, and the total harmonic distortion over the whole passband range is below 0.25% for a 2-V/SUB pp/ input signal. The PSRR of the filter is above 40 dB at frequencies below 3 kHz.     

一种折叠共源共栅运算放大器的设计

折叠共源共栅运放结构的运算放大器可以使设计者优化二阶性能指标,这一点在传统的两级运算放大器中是不可能的。特别是共源共栅技术对提高增益、增加PSRR值和在输出端允许自补偿是有很用的。这种灵活性允许在CMOS工艺中发展高性能无缓冲运算放大器。目前,这样的放大器已被广泛用于无线电通信的集成电路中。介绍了一种折叠共源共栅的运算放大器,采用TSMC 0.18混合信号双阱CMOS工艺库,用HSpice W 2005.03进行设计仿真,最后与设计指标进行比较。     

高电源抑制比的CMOS亚阈值多输出电压基准

基于工作在亚阈值区的MOS器件,运用CMOS电流模基准对CATA和PTAT电流求和的思想．提出一种具有低温漂系数、高电源抑制比（PSRR）的CMOS电压基准源,该电路可同时提供多个输出基准电压,且输出电压可调。该基准源基于CSMC0．5μm标准CMOS工艺,充分利用预调节电路并改进电流模基准核心电路。使整个电路的电源抑制比在低频时达到122dB,温度系数（TC）在0-100℃的温度范围内约7ppm／℃。     

一种低工艺敏感度,高PSRR带隙基准源

实现了一种高精度带隙基准源,该基准源在预调节电路中应用了电源行波减法技术,显著改善了输出电压的电源抑制比。提出了采用电流负反馈技术稳定预调节电路电流的方法,降低了带隙基准的温度特性和电源抑制比对阈值电压的敏感度。考虑晶体管阈值电压发生±20%变化的情况下,仿真得到的基准源的温度系数和电源抑制比变化分别只有0.11ppm和7dB。测试结果表明,该基准源在-20～100℃的范围内的有效温度系数为25.7ppm/℃,低频电源抑制比为-68dB。其功耗为0.5mW,采用中芯国际0.35μm5-V混合信号CMOS工艺实现,有效芯片面积为300μm×200μm。     

一种10-ppm/~oC低压CMOS带隙电压基准源设计

在对传统CMOS带隙电压基准源电路分析和总结的基础上,综合一级温度补偿、电流反馈和电阻二次分压技术,提出了一种10-ppm/oC低压CMOS带隙电压基准源。采用差分放大器作为基准源的负反馈运放,简化了电路的设计,放大器的输出用于产生自身的电流源偏置,提高了电源抑制比(PSRR)。整个电路采用TSMC 0.35mm CMOS工艺实现,采用Hspice进行仿真,仿真结果证明了基准源具有低温度系数和高电源抑制比。     

A 10-bit 205-MS/s 1.0- mm2 90-nm CMOS Pipeline ADC for Flat Panel Display Applications

This paper describes a 10-bit 205-MS/s pipeline analog-to-digital converter (ADC) for flat panel display applications with the techniques to alleviate the design limitations in the deep-submicron CMOS process. The switched source follower combined with a resistor-switch ladder eliminates the sampling switches and achieves high linearity for a large single-ended input signal. Multistage amplifiers adopting the complementary common-source topology increase the output swing range with lower transconductance variation and reduce the power consumption. The supply voltage for the analog blocks is provided by the low drop-out regulator for a high power-supply rejection ratio (PSRR) under the noisy operation environment. The pipeline stages of the ADC are optimized in the aspect of power consumption through the iterated calculation of the sampling capacitance and transconductance. The ADC occupies an active area of 1.0 mm² in a 90-nm CMOS process and achieves a 53-dB PSRR for a 100-MHz noise tone with the regulator and a 55.2-dB signal-to-noise-and-distortion ratio for a 30-MHz 1.0-V_PP single-ended input at 205 MS/s. The ADC core dissipates 40 mW from a 1.0-V nonregulated supply voltage.     

一种高电源抑制比带隙基准源的设计

带隙基准源是LDO中的重要模块,其性能的好坏直接影响到LDO整个系统的性能,为此本文针对以上问题进行相关研究,设计一种具有较高的PSRR和较低的稳定输出电压的带隙基准电压源。文中结合工程实际的要求设计了一款具有高的电源抑制比（PSRR）、低的输出基准电压的带隙基准电压源。本设计采用SMIC公司的0.18μm工艺进行仿真,Hspice的仿真结果表明该基准源在电源抑制比（PSRR）、温度特性等方面有良好的性能。     

LDO线性稳压器中高性能误差放大器的设计

设计了一个共源共栅运算跨导放大器,并成功地将其应用在一款超低功耗LDO线性稳压器芯片中。该设计提高了电源抑制比(PSRR),并具有较高的共模抑制比(CMRR)。电路结构简单,静态电流低。该芯片获得了高达99 dB的电源抑制比。     

A new PWM controller with one-cycle response

This paper proposes a new nonlinear control technique that has one-cycle response, does not need a resetable integrator in the control path, and has nearly constant switching frequency. It obtains one-cycle response by forcing the error between the switched variable and the control reference to zero each cycle, while the on and off pulses of the controller are adjusted each cycle to ensure near constant switching frequency. The small switching frequency variation due to changes in the reference signal and supply voltage and delays in the circuit are quantified. Using double-edge modulation, the switching frequency variation is further reduced, thus, the associated signal distortion is minimized. An experimental 0-20 kHz bandwidth 95 W RMS power audio amplifier using the control method demonstrates the applicability of this control technique for high-fidelity audio applications. The amplifier has a power supply ripple rejection (PSRR) of 63 dB at 120 Hz. Additionally, the total harmonic distortion plus noise (THD+N) is less than 0.07% measured with a power supply ripple of 15%     

Offset voltage, CMRR and PSRR of a long-tailed pair: an integrated approach

An integrated treatment of the input offset-voltage Vos, common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) of a simple resistively loaded bipolar differential amplifier establishes the basic theoretical relationships between these parameters and indicates that `Early-voltage? mismatch of the constituent devices limits the attainable CMRR and PSRR.     

Improved clock buffer with high PSRR for SC circuit applications

Clock feedthrough in SC circuits results in low PSRR figures, incompatible with high-performance signal processing. A high-PSRR CMOS clock buffer is presented here, which blocks this power supply (PS) noise coupling path. The presented circuit is a significant improvement over an earlier circuit proposed by the same author, but having a PSRR of over 40 dB now.<>     

一种具有高电源抑制比的低功耗CMOS带隙基准电压源

文章设计了一种适用于CMOS工艺的带隙基准电压源电路，该电路采用工作在亚阈值区的电路结构，并采用高增益反馈回路，使其具有低功耗、低电压、高电源电压抑制比和较低温度系数等特点。     

A high PSRR CMOS voltage reference with 1.2 V operation

A high power supply rejection ratio (PSRR) CMOS band-gap reference (BGR) with 1.2 V operation is proposed in this paper. The reference features include an error amplifier with a trimming circuit and a trimming resistor array on the chip. Local positive feedback is used in the error amplifier to obtain high gain. By trimming the resistor array, the PSRR of the error amplifier is trimmed around one to obtain a high PSRR. The trimming resistor array is controlled externally. The post simulation results indicate that the PSRR is up to ?130 dB@DC and ?89 dB@10 kHz. The experimental results show that, under a supply voltage of 1.2 V the measured PSRR is ?103 dB@dc and ?74 dB@10 kHz.     

一种宽电源电压带隙基准源的设计

提出一种可在宽电源电压范围下工作的带隙基准源设计.由于采用了一些新的结构,使得其电源抑制比和温度稳定性有明显提高.为支持电源管理芯片的休眠工作模式以降低待机功耗,电路中专门设置了一个辅助的微功耗基准,在正常模式下为电路提供偏置,在休眠模式中替代主基准以节省功耗.仿真结果表明,该基准源提供的1.27V基准电压在-20至120℃范围内的最大温漂为3.5mV.当供电电压由3V变化至40V时,基准电压的变化为56μV.在低于10kHz的频率范围内基准源具有大于100dB的电源抑制比.芯片采用1.5μm BCD(Bipolar-CMOS-DMOS)工艺设计与实现.实验结果证实上述设计目标已基本实现.     

一种可减小工艺影响的带隙基准电压源

提出了一种新颖的基准电压源结构,有效地减小了运算放大器由于工艺偏差给基准电压源带来的影响。该电路在面积上与现有传统结构基本相同,并且具有与传统结构相同的温度补偿系数和良好的电源抑制比(PSRR)。     

Modeling and Technique to Improve PSRR and PS-IMD in Analog PWM Class-D Amplifiers

Although power-supply noise, qualified by power- supply rejection ratio (PSRR), has been recognized as a potential drawback of Class-D amplifiers (CDAs) compared to linear amplifiers, the mechanisms of PSRR for CDAs are not well established. It is also not well recognized that the power-supply noise can intermodulate with the input signal, manifesting into power-supply induced intermodulation distortion (PS-IMD), and that the PS-IMD can be significantly larger than the output distortion component at supply noise frequency. Furthermore, techniques to improve PSRR and PS-IMD are largely unreported in literature. In this brief, by means of a linear model, the PSRR and PS-IMD of single-feedback and double-feedback CDAs are analyzed and analytical expressions derived. A simple method is proposed to improve PSRR and PS-IMD with very low hardware overheads, and the improvement is ~ 26 dB. Analytical expressions for PSRR and PS-IMD of the improved design are derived and the pertinent parameters thereof are investigated. The model and analyses provide practical insight to the mechanisms of PSRR and PS-IMD, and how various parameters may be varied to meet a given specification.     

CMOS voltage references using lateral bipolar transistors

Two bandgap references are presented which make use of CMOS compatible lateral bipolar transistors. The circuits are designed to be insensitive to the low beta and alpha current gains of these devices. Their accuracy is not degraded by any amplifier offset. The first reference has an intrinsic low output impedance. Experimental results yield an output voltage which is constant within 2 mV, over the commercial temperature range (0 to 70/spl deg/C), when all the circuits of the same batch are trimmed at a single temperature. The load regulation is 3.5 /spl mu/V//spl mu/A, and the power supply rejection ratio (PSRR) at 100 Hz is 60 dB. Measurements on a second reference yield a PSRR of minimum 77 dB at 100 Hz. Temperature behaviour is identical to the first circuit presented. This circuit requires a supply voltage of only 1.7 V.