声扫检测中易误判的塑封器件的验证方法

塑封器件在高可靠性领域应用越来越广泛,为了降低使用风险,很有必要进行相应的检测或筛选,扫描声学显微镜检查就是其中一种很重要的无损检测手段。但是,在进行声扫时,对于某些最新的封装方式,需要特殊情况特殊分析,以避免因为器件的封装形式而非器件的缺陷拒收产品。在电子封装设计时,芯片表面可能涂覆一层有机材料来保护集成电路。但这种材料声扫结果往往与真正的分层一样显示为负波,容易误判为不合格。就这种结构及其声扫结果提出了几种验证方法。     

The appropriateness of plastic encapsulated microcircuits in aspecific wooden-round application

Improvements in design, materials, and processes of plastic encapsulated microcircuits (PEM) have increased their reliability dramatically, to the point where PEM can achieve the `20-year lifetime in unpowered storage' required by certain wooden-round applications. PEM are now the parts of choice from cost, market-availability, performance, and reliability viewpoints. Nevertheless, PEM require appropriate vendor selection, verification by highly accelerated stress test (HAST), and manufacturing precautions. The potential failure mechanisms of package damage, internal part corrosion, and intermetallic growth, due to high temperature and humidity exposure, have been largely eliminated by improvements in the plastic and in the assembly process, and by the addition of die passivation. Models and test methodologies for accelerating (and thereby identifying) these physical phenomena have been developed, proven by testing, and generally accepted within the industry. After thoroughly defining the application temperature/humidity environments, the models are used to define a test program to qualify candidate PEM. This program consists of a high temperature life test, a humidity/temperature HAST and a completely assembled board-level HAST. To insure that subsequent manufacturing processes at Textron DS (including higher assemblies) do not damage qualified PEM, the manufacturing flow has been modified to minimize human contact with components, to eliminate any potentially corrosive chemical interaction with PEM, and to minimize exposure to moisture     

塑封微电路筛选鉴定和DPA技术的研究

由于塑封器件结构和材料等因素,存在非气密性、易受温度形变等特有潜在缺陷.有效的筛选和鉴定已经成为检验塑封微电路(PEMs)质量和提高应用可靠性的关键.DPA作为产品质量检验与可靠性评价技术,能提供PEM生产与设计、工艺和制造缺陷的信息.介绍了一套筛选、鉴定和DPA技术相结合的PEMs产品保证方法,可以作为向高可靠性要求用户提供高质量PEMs的主要评价手段.     

新型塑封器件开封方法以及封装缺陷

随着塑封器件(PEMs)质量和可靠性的不断提高,塑封器件的应用领域进一步扩展,也逐步应用于军事领域.去除塑料包封层,露出芯片表面,是DPA(破坏性物理分析)及FA(失效分析)的关键一步.对塑封器件的开封技术进行了简要的介绍,并对开封中发现的一些失效模式进行分析.通过对塑封器件开封方法的研究,确保塑封器件的开封质量,为进一步对塑封器件进行DPA和失效分析建立了基础.     

Application of the Taguchi method to chip scale package (CSP)design

A three-dimensional (3-D) nonlinear finite element model of an overmolded chip scale package (CSP) on flex-tape carrier has been developed by using ANSYS^TM finite element simulation code. The model has been used to optimize the package for robust design and to determine design rules to keep package warpage within acceptable Joint Electron Device Engineering Council (JEDEC) limits. An L₁₈ Taguchi matrix has been developed to investigate the effect of die thickness and die size, mold compound material and thickness, flex-tape thickness, die attach epoxy and copper trace thicknesses, and solder bail collapsed stand-off height on the reliability of the package during temperature cycling. For package failures, simulations performed represent temperature cycling 125°C to -40°C. This condition is approximated by cooling the package which is mounted on a multilayer printed circuit board (PCB) from 125°C to -40°C. For solder ball coplanarity analysis, simulations have been performed without the PCB and the lowest temperature of the cycle is changed to 25°C. Predicted results indicate that for an optimum design, that is low stress in the package and low package warpage, the package should have smaller die with thicker overmold. In addition to the optimization analysis, plastic strain distribution on each solder ball has been determined to predict the location of solder ball with the highest strain level. The results indicate that the highest strain levels are attained in solder balls located at the edge of the die. The strain levels could then be used to predict the fatigue life of individual solder balls     

热膨胀系数不匹配导致的塑封器件失效

塑封器件使用过程中由于塑封材料和芯片之间热膨胀系数的不匹配,导致在外界温度变化时的应力释放对芯片造成损伤。文中通过VLSI失效分析,对这种应力造成的芯片损伤进行了研究,并提出利用环境应力试验和可靠性分析的方法暴露热膨胀系数不匹配导致芯片损伤的技术。     

Influence of underfill materials on the reliability of coreless flip chip package

A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutectic Sn37Pb solder bump, two kinds of underfill materials and Sn_3.0Ag_0.5Cu solder balls. Regarding to the yield, the peripheral solder joints were often found not to connect with the substrate due to the warpage at high temperature, modification of reflow profile was benefit to improve this issue. All the samples passed the moisture sensitive level test with a peak temperature of 260 °C and no delamination at the interface of underfill and substrate was found. In order to know the reliability of coreless flip chip package, five test items including temperature cycle test (TCT), thermal shock test (TST), highly accelerated stress test (HAST), high temperature storage test (HTST) and thermal humidity storage test (THST) were done. Both of the two underfill materials could make the samples pass the HTST and THST, however, in the case of TCT, TST and HAST, the reliability of coreless flip chip package was dominated by underfill material. A higher Young’s modules of underfill, the more die crack failures were found. Choosing a correct underfill material was the key factor for volume production of coreless flip chip package.     

High density packaging technology ultra thin package & new tab package

As electronic devices become more highly integrated, the demand for small, high pin count packages has been increasing. We have developed two new types of IC packages in response to this demand. One is an ultra thin small outline package (TSOP) which has been reduced in size from the standard SOP and the other, which uses Tape Automated Bonding (TAB) technology, is a super thin, high pin count TAB in cap (T.I.C.) package. In this paper, we present these packages and their features along with the technologies used to improve package reliability and TAB. Thin packages are vulnerable to high humidity exposure, especially after heat shock.1 The following items were therefore investigated in order to improve humidity resistance: (1) The molding compound thermal stress, (2) Water absorption into the molding compound and its effect on package cracking during solder dipping, (3) Chip attach pad area and its affect on package cracking, (4) Adhesion between molding resin and chip attach pad and its affect on humidity resistance. With the improvements made as a result of these investigations, the reliability of the new thin packages is similar to that of the standard thicker plastic packages.     

A Reliability Evaluation of Plastic Packaged Semiconductor Components

Qualification testing programs have been developed for assessing the reliability of commercial grade discrete semiconductors for use in office business machines. These programs include accelerated stresses of high temperature storage (HTS) and high temperature reverse bias (HTRB) for 1000 hours, and a sequence test of thermal cycle and thermal shock followed by storage at 85°C and 85% RH (85/85) for 1000 hours. Both hermetic and plastic encapsulated parts have been tested more than 15 million part hours. HTRB and 85/85 are about twice as effective as HTS in identifying potentially unreliable parts. Plastic packaged semiconductors are inherently capable of withstanding 85/85 for 1000 hours without parameter degradation. The value of qualification testing against the 85/85 environment is demonstrated by the observed correlation of machine failure rates in the field with the relative humidity in the use environment. The observed failure rate of plastic parts is not more than 3.2 times that of hermetic parts. Plastic parts are capable of reliable operation, but the marked differences in reliability between different vendors and between different part types from the same vendor require increased process and materials control in order to achieve the potential of which plastic parts are capable.     

A universal reliability prediction model for SMD integrated circuits based on field failures

This paper makes a review of integrated circuit field failures on three types of environment respectively, Ground Benign (G_B), Ground Fixed (G_F), and Airborne Inhabited Cargo (A_IC). It appears that for permanent working G_B, there was no package related failures and 2/3 of the failures had EOS origin. For G_F and A_IC most of the failures were open balls bonds and open solder joints. A universal predicting reliability model is therefore proposed for the die part and for the package part. This study has been carried out in the frame of a working group, to update the French standard UTEC 80810 (ex RDF93 from CNET), and is an alternative guide to the obsolete MIL-HDBK-217F for predicting reliability calculations.     

Qualification approaches and thermal cycle test results for CSP/BGA/FCBGA

Qualification of newly developed multifunctional electronic packages, e.g. system in a package (SIP), are becoming complex at the package level and even more at the assembly and system levels. After many years of data collection, just recently industry agreed to release an industry-wide specification for single die area array package assembly qualification.Probability risk assessment, being implemented by NASA for space flight missions, may be narrowed at the element level for advanced electronic systems and SIP, and further narrowed at the electronic subsystem level. This paper will review the key elements of an industry-wide specification recently published by the IPC (association connecting electronics industries). It will report on a few other unique qualification approaches that are currently being either implemented or developed for risk reduction in high reliability applications. Risk level assessment based 2-P, 3-P, and LogNormal distributions will be compared for plastic ball grid array (PBGA) and flip chip BGA (FCBGA). For this case, risks are compared using cycles-to-failures (CTFs) test results for temperature ranges of −30 to 100 °C and 0 to 100 °C (two profiles).In addition, CTFs up to 1,500 cycles in the range of −55 to 125 °C for a 784 I/O FCBGA (flip chip BGA, a 175 I/O FPBGA (fine pitch BGA)), and a 313 I/O PBGA (plastic BGA) are compared. Inspection results along with scanning electron microscopy and optical cross-sectional photos revealing damage and failure mechanisms are also included.     

GaAs微波单片集成电路(MMIC)的可靠性研究

本文介绍了GaAs MMIC的可靠性研究与进展，重点介绍了工艺表征工具（TCV）、工艺控制监测（PCM）和统计工艺控制（SPC）等实现产品高质量、高可靠性和可重复性的可靠性保障技术，为国内GaAs MMIC可靠性研究提供了新的思路。     

On the Effectiveness of the System Validation Based on the Black Box Testing Methodology

With the advancement of technology in recent years, effective fault diagnosis became a necessity to verify the performance and ensure the quality of complex systems. In this paper, an original verification methodology for complex consumer electronic devices is presented. Verification of the system which consists of hardware （integrated circuit） and corresponding software within a flat panel TV set is in the focus. Proposed methodology provides reliable functional failure detection using the concept of black box testing. Further, the approach is fully automated, improving the reliability and speed of failure detection. The methodology effectiveness has been experimentally evaluated and the analysis results have been reported.     

Reliability Study of High-Density EBGA Packages Using the Cu Metallized Silicon

The reliability of high-density enhanced ball grid array (EBGA) packages using the eight-layer Cu metallization silicon was discussed. The key failure mechanisms included the die cracking (in the vicinity of the edge) and thin film delamination. It was noticed that the failure was unique to the Cu metallization silicon. The large package body size (45 mm$^{2}$) and the die size (approximately 15 mm$^{2}$ ) provided additional manufacturing and reliability challenges. The die-edge defects induced during the wafer sawing process were exhibited to be the culprits of the die cracking and the thin film delamination failures. Additionally, the height of die attach fillets significantly influenced the stresses on the die edge, and the excessive fillet height was found to help extend initial cracks at the edge of the silicon. The results demonstrated the adoption of a dual-step wafer sawing scheme and resin blades would control the defects and reduce the failure rate dramatically. A mixture of low-stress encapsulation and die attach materials would help improve the overall reliability of the packages as well. The solder joint reliability of the package was very robust based on the board-level reliability testing results. The statistical analysis of the test results confirmed that most of the die cracking and thin film delamination failures were early-life failures and random. A good sample screening scheme and the process improvement procedure would help improve the reliability and insure the customer a low failure rate for the lifetime of the product. The predicted reliability of the package met the application life needs for the products with process improvement plans in place.      

Failure physics of integrated circuits — A review

This paper is a review of the most important results on failure physics of integrated circuits, as a synthesis of what has been recently encountered in the literature concerned with these problems.In the first part of the paper systematization of failure modes in integrated circuits is accomplished so that all failure modes are divided into four groups according to their origin: (i) failure modes associated with chip; (ii) failure modes resulting from leads and bonds; (iii) failure modes associated with encapsulation; and (iv) failure modes due to external effects and overstress. Also, some typical failure mode distributions of different types of integrated circuits are given and the effects of the changeover from LSI to VLSI on failure mode distributions are discussed.In the second part of the paper the most important tests for enhancing of the failure modes are enumerated and relationship between the failure modes and the tests for their detection is given. Also, the role of electrical testing by the curve tracer and the accompanying analytical techniques (scanning electron microscopy, transmission electron microscopy, electron beam microprobe, Auger electron spectroscopy and X-ray radiograph) are discussed. Finally, the diagnostic technique is described which, using simple electrical testing by the curve tracer and some tests for enhancing of the failure modes (high temperature bake and high temperature burn-in), enables simple detection of integrated circuit failure modes.In the third part of the paper a survey of test structures for failure analysis of integrated circuits is made. Test structures are divided into three groups according to the kind of the failure mode tested by them. First, the test structures for the analysis of the failures due to the process induced defects are described. Then, the test structures for the analysis of the failures due to traps at the interface silicon-oxide and mobile alcali ions in oxide are discussed. Finally, the test structures for the analysis of the metallization failures are considered.     

Assembly-level reliability: a methodology for effectivemanufacturing of IC packages

This paper discusses the general methodology of assembly level reliability (ALR) as part of a corporate effort at designing reliability into the whole assembly process of integrated circuit (IC) packages. Semiconductor packages with assembly-induced defects sometimes do escape detection due to a variety of reasons. Trying to eliminate this problem by approaching it piecemeal may result only in single process optimization, but does not guarantee full assembly line balancing for error-free production. ALR is a systematic 4-prong approach which uses a combination of techniques for synergistic effects. (1) Problems of immediate needs have to be addressed and contained, (2) The proper steps must then be taken to ensure that similar issues do not resurface. (3) Design-for-manufacturability principles must be applied; e.g., the design of the package can be simplified to reduce the number of assembly steps, increase throughput, and cut cost. (4) Qualification methodologies have to be revisited. Less expensive but well-characterized test chips can be introduced in lieu of actual devices. Accelerated testing with a good understanding of the failure mechanisms facilitates faster product qualification to ensure time-to-market advantage. Together with these more cost-effective qualification techniques, the proper reliability-monitoring features must be installed. Only then can the true vision of ALR be accomplished, viz, ensuring recognition, by both customers and competitors, as a Company that continuously manufactures defect-free parts     

Multiple impact characterization of wafer level packaging (WLP)

Wafer level packaging (WLP) of connectivity RF components for mobile devices has emerged as a low-cost and high performance, enabling technology. WLP devices are electronic components with an exposed die that utilizes a ball pitch compatible with standard surface mount technology (SMT) equipment and common printed circuit board (PCB) design techniques. WLP allows the devices to be directly mounted to the PCB of portable devices. One concern of adopting WLP for mobile device applications is reliability under multiple dynamic loading conditions, such as phone drop, due to the fragile nature of the exposed silicon die and the unique packaging designs. A series of dynamic 4-point bend tests were conducted to evaluate the multiple impact reliability of WLP samples. The purpose of this work was to better understand the failure modes and actual reliability of WLP under uniaxial loading, which is commonly observed in mobile drop simulations and tests. The results have been applied to WLP failure prediction for the system-level drop test by using simulation technology.     

Using charged device model testing to eliminate real-world ESD failures

Of 30 bipolar, BiCMOS, and CMOS monolithic, integrated circuit products that were ESD classified to the socketed Charged Device Model (CDM), 27 had ≥500 V withstand voltages and experienced no real-world CDM failures. Two of the three focus products with < 500 V withstand voltages initially had numerous manufacturing-induced CDM failures. Analysis of these two products showed that both socketed and non-socketed CDM testing induced damage at the same failure sites as identified on real-world CDM failures. However, only non-socketed CDM testing consistently reproduced the subtle damage observed on the real-world failures. On one of the focus products, the more severe damage induced by socketed CDM testing resulted in an open circuit rather than the resistive short that occurred on both the non-socketed and real-world CDM failures.Once the physics of CDM failure on the three focus products were fully understood, the ESD redesigns were relatively straightforward. On all three products, diffused series resistors and/or clamping devices with fast response times were added to the pins with inadequate CDM robustness. For each product, these redesigns boosted the socketed CDM withstand voltages for the previously susceptible pins to ≥1500 V and eliminated real-world CDM failures.Based on this work, a combined socketed and non-socketed CDM test approach is proposed for classifying/evaluating products and driving CDM robustness improvements. Guidelines for CDM testing and CDM improvement programs are also provided.     

A square ring on square ring (SoS) ceramic strength testing technique for VLSI packaging

This paper describes a square ring on square ring (SoS) strength testing technique for reliability evaluation of ceramic pin grid array (PGA) packages. The unique features of this new technique are that the residual stresses are included in the strength results and that the package does not have to be cut, ground, or modified in any way to test the strength. The testing procedure is simple: after the fixture is calibrated for coplanarity, the package is placed in the SoS apparatus and force is applied until the ceramic fails. The ultimate force to failure is then converted into ceramic strength by using Finite Element Modeling (FEM). This paper also discusses failure analysis of ceramic packages that have been tested to failure with the SoS technique, ceramic strength and statistics, and verification of FEM models. The SoS apparatus consists of cantilevered beams and the free end of the beams come into contact with the edge of the package; therefore, the fixture conforms to the contour of the package during testing. This strength testing technique is currently being used to monitor the changes in strength and Weibull slope of PGAs. It is also being used for reliability evaluation of the heat sink side and cavity side of PGAs as received from suppliers and during the various stages of assembly/environmental processes.     

高可靠先进微系统封装技术综述

在人工智能、航空航天、国防武器装备电子系统小型化、模块化、智能化需求驱动下,系统级封装设计及关键工艺技术取得了革命性突破。新型的系统封装方法可把不同功能器件集成在一起,并实现了相互间高速通讯功能。封装工艺与晶圆制造工艺的全面融合,使封装可靠性、封装效率得到极大的提升,封装寄生效应得到有效抑制。文章概述了微系统封装结构及类型,阐述了高可靠晶圆级芯片封装(WLP)、倒装焊封装(BGA)、系统级封装(SIP)、三维叠层封装、TSV通孔结构的实现原理、关键工艺技术及发展趋势。