应用推动数字信号处理器发展

本文从设计和应用的角度分析了数字信号处理器(DSP)的特点，详细地从结构、指令集和运算单元方面阐述了DSP区别于其它处理器的特点；介绍了DSP的发展概况，从复杂指令单个乘法累加运算单元发展到复杂指令两个运算单元，又发展到简单指令多个运算单元，并指出是应用推动了DSP的飞速发展；最后，对DSP的发展作了预测，DSP将在多发射、嵌入式DSP核和控制运算混合处理器方向发展。     

A 30-MHz mixed analog/digital signal processor

A multiplying encoder architecture that is implemented in the design of a mixed analog and digital signal processor is presented. The processor is suitable for performing both high-speed A/D conversion and digital filtering in a single chip. The device can resolve the input with 8 b at 30 Msample/s and perform 28 multiply and 28 add operations per sample under typical conditions. The processor is designed for a 28-tap programmable FIR (finite impulse response) filter with analog input signal which can be used for waveform shaping of the modem to obtain the desired transmission performance for business satellite communication and mobile communication. The chip is fabricated in a 1-μm double-polysilicon and double-metal CMOS technology. The chip size is 9.73×8.14 mm², and the chip operates with a single +5.0-V power supply. Typical power dissipation is 950 mW; 330 mW is dissipated in analog and 620 mW is in the digital block     

A DSP Architecture for High‐Speed FFT in OFDM Systems

This paper presents digital signal processor (DSP) instructions and their data processing unit (DPU) architecture for high‐speed fast Fourier transforms (FFTs) in orthogonal frequency division multiplexing (OFDM) systems. The proposed instructions jointly perform new operation flows that are more efficient than the operation flow of the multiply and accumulate (MAC) instruction on which existing DSP chips heavily depend. We further propose a DPU architecture that fully supports the instructions and show that the architecture is two times faster than existing DSP chips for FFTs. We simulated the proposed model with a Verilog HDL, performed a logic synthesis using the 0.35 µm standard cell library, and then verified the functions thoroughly.     

LSI Processor for Digital Signal Processing and Its Application to 4800 Bit/s Modem

This paper describes a fast data processing LSI unit tailored to the digital signal processing (DSP) applications in the field of electrical communications. The results of successful application to the 4800 bit/s modem are also given. The LSI processor discussed here adopts a firmware control scheme to enhance the flexibility and freedom of application and extensively utilizes the pipeline processing technique to attain high speed data handling capability. The various operations encountered in DSP systems are unified into one operation of the typeA times B + C rightarrow Dand the LSI processor is designed to continuously perform this operation, while the data to be operated are transferred sequentially into the processor controlled by exterior firmware. The developed LSI handles 8 bit data at the clock frequency of 1.152 MHz and manages 144 K operations per second (6.9 μs cycle time). The LSI is an N-MOS chip containing 1500 gates and packaged in a 40 pin DIP. The automatic equalizer for 4800 bit/s modem was implemented using two of the developed LSI processors and about 4 K ROM and 1 K RAM memory chips. The measurement on this modem gave the error rate of 10^-5atS/N = 17.6dB and error free phase jitter allowance of 55° p-p. Application of the LSI processor to digital filters for roll-off spectrum shaping and timing signal extraction is also described.     

A reconfigurable 8 GOP ASIC architecture for high-speed datacommunications

A flexible and reconfigurable signal processing ASIC architecture has been developed, simulated, and synthesized. The proposed architecture compares favorably to classical DSP and FPGA solutions. It differs from general-purpose reconfigurable computing (RC) platforms by emphasizing high-speed application-specific computations over general-purpose flexibility. The proposed architecture can he used to realize any one of several functional blocks needed for the physical layer implementation of data communication systems operating at symbol rates in excess of 125 Msymbols/s. Multiple instances of a chip based on this architecture, each operating in a different mode, can be used to realize the entire physical layer of high-speed data communication systems. The architecture features the following modes (functions): real and complex FIR/IIR filtering, least mean square (LMS)-based adaptive filtering, discrete Fourier transforms (DFT), and direct digital frequency synthesis (DDFS) at up to 125 Msamples/s. All of the modes are mapped onto a common, regular data path with minimal configuration logic and routing. Multiple chips operating in the same mode can be cascaded to allow for larger blocks     

DSP中MAC的微系统结构设计

在实际的高性能定点数字信号处理器(DSP)设计过程中，往往需要设计一个功能复杂的乘累加器。也就是说，乘累加器不光是要同时完成通常所见的带符号数和无符号数的乘加及乘减运算，而且还需要同时完成整数乘加和小数乘加运算，无偏差的舍入运算，饱和等功能。另外，为了解决DSP中数据相关的问题，往往要求乘累加器在单拍完成所有的这些运算，因此很难找到一个高速度低成本的实现方案。文章首先给出了通常的高性能定点DSP中乘累加器所需要完成的功能需求，然后提出并实现了一个16位高性能乘累加器，将其所需要完成的上述各种功能巧妙地整合起来在单拍内完成，而完成所有上述功能只需要3级4：2压缩和一次超前进位的加法运算。该乘累加器采用0．35μm工艺实现，已经嵌入到数字信号处理器中并已经成功应用于实际的工程项目。     

基于DSP的激光标记数字控制系统设计

为了设计激光标记数字振镜控制系统,采用数字信号处理器芯片作为数字控制板的主处理器,使用具有高传输速率和支持热插拔的通用串行总线进行上位机与数字控制板的通信;标记图形的数据处理算法由具有高速运算能力的数字信号处理器完成,复杂可编程逻辑器件芯片完成控制信号的时序控制和输出,使用传送差分信号的RS-485总线进行控制系统与数字振镜和激光器的通信,根据理论分析和参量模拟,得到了对数字振镜的转动角度和激光器功率的高精度控制。结果表明,该系统可以实现实时、高速、高精度的激光标记。     

An 80-MOPS-peak high-speed and low-power-consumption 16-b digitalsignal processor

This paper describes a 16-b fixed point digital signal processor (DSP), especially its multiply-accumulate (MAC) unit, memories, and instruction set. By adopting a redundant binary multiplier and a variable pipeline structure, this DSP's MAC unit, compared to a conventional MAC unit, consumes about 15% less power and operates 24% faster. Furthermore, its double-speed MAC mechanism can realize twice the performance of a single MAC operation while consuming only 69% more power. By being able to more finely control which portions of memory are activated, the data ROM and data RAM's precharge current was reduced to about 1/8 of the conventional ROM and RAMs. We redesigned the instruction set and reduced its width from 32 b to 24 b based on the analysis of data generated by simulating an application program on our previous DSP. The reduction in instruction width made our on-chip instruction memory size 33% smaller than the previous one. This chip is fabricated with a 0.5-μm double-metal-layer CMOS process and achieves 80-MOPS-peak double speed multiply-accumulate performance     

KISS-16V2: a one-chip ASIC DSP solution for GSM

Outlines the requirements for the various digital signal processing functions of the pan-European digital mobile cellular telephone system in terms of computational power and RAM and ROM capacities, and describes a digital signal processor (DSP) solution which is able to integrate all of these digital baseband functions for a hand-held terminal onto one VLSI chip. The KISS-16V2 processor, a low-power CMOS 16-b DSP, is optimized for digital telecommunications, especially for Groupe Speciale Mobile (GSM). A power-down mode together with the capability of memory and multiplier standby operation make this DSP well suited for handheld devices. A design strategy based on the extensive use of cell compilers and synthesis tools reduces the design of further DSP derivations to a minimum.<>     

一种电机FOC算法DSP系统设计及实现

本文设计了一种适用于电机矢量控制算法的数字信号处理系统的微架构定义,包括其指令集定义、存储器模型以及与主CPU的交互模式.该设计具有通过固定部分多操作数有效缩减指令编码长度提高代码密度以及后台执行多周期指令提高ALU并行效率的显著优点.文中给出了典型的FOC控制算法在DSP （Digital Signal Processor）指令集上实现的指令周期数,也给出了对应架构的电路实现情况,最终以ARM CORTEX-M0及几款主流DSP作为比较基线,通过实测实验数据证明了体系结构的高能效比,以较为有限的电路面积代价,极大提高了集成DSP的嵌入式系统的运行效率.     

数字音频网络处理器的系统设计

提出了基于CobraNet技术和DSP技术的网络数字音频处理器的设计方案。该设计利用CM2模块(Co-braNet技术的硬件部分)的实时音频传输功能以及ADSP21161N的片上处理能力和接口通信能力实现。数字信号处理流程和算法可通过PC机进行配置。较详细地给出了数字音频网络处理器的软硬件实现方案。     

A flexible adaptive FIR filter VLSI IC

The architecture and features of the Motorola DSP56200 are described. The DSP56200 is an algorithm-specific cascadable digital signal processing peripheral designed to perform the computationally intensive tasks associated with finite impulse response (FIR) and adaptive FIR digital filtering applications. The DSP56200 is implemented in high-performance, low-power 1.5-μm HCMOS technology and is available in a 28-pin DIP package. The on-chip computation unit includes a 97.5-ns 24-bit×24-bit coefficient RAM, and a 256-bit×16-bit data RAM. Three modes of operation allow the part to be used as a single, dual, or single adaptive FIR filter, with up to 256 taps per chip. In the adaptive mode, the part performs the FIR filtering and least-mean-square (LMS) coefficient update operations for a single tap in 195 ns, permitting use of the part as a 19-kHz sampling rate, 256-tap adaptive FIR filter. A programmable DC tap, coefficient leakage, and adaptation coefficient parameters in the adaptive FIR mode allow the DSP56200 to be used in a wide variety of adaptive FIR filtering applications. The performance of the part in an echo canceler configuration is presented. Typical applications of the part are also described     

Word-parallel CRC computation on VLIW DSP

Cyclic redundancy check (CRC) is widely used for error detection. For optimal performances, a method has been developed for bit-parallel processing, but it may not take advantage of parallel processor architecture. Here, a method is proposed for using the full power of a very long instruction word (VLIW) digital signal processor (DSP) architecture in CRC computation. The method is at least four times faster for 8, 16 and 32 bits CRC     

基于ARM和DSP的微机线路保护装置

在微机线路保护中,利用数字信号处理器（DSP）高效快速的数字信号处理能力和嵌入式先进的精简指令集芯片机器（ARM）处理器强大的以太网通信功能,采用DSP＋ARM9的双中央处理器（CPU）的硬件结构,两者之间采用双口随机存储器（RAM）进行数据交换。软件设计基于嵌入式Linux操作系统,移植了Bootloader、内核,构建了Ramdisk的根文件系统,并移植了应用程序。     

An efficient locally pipelined FFT processor

The fast Fourier transform (FFT) is a very important algorithm in digital signal processing. The locally pipelined (LPPL) architecture is an efficient structure for FFT processor designing in a real-time embedded system. Two basic building blocks, to the LPPL FFT processor, the butterfly in pipeline, and address generating, are discussed in this brief. Based on the "deep" feedback to butterfly-2, a novel approach for pipelined architecture, the radix-2 single-path deep delay feedback architecture is proposed. For length-N discrete Fourier transform computation, the dominant hardware requirements are minimal for complex multipliers log/sub 4/N-1 and adders 2log/sub 4/N. As an integral need of the LPPL FFT processor design, address generating and coefficient store-load structures are also presented.     

基于 DSPC6678多核平台的实时任务调度架构设计分析

分析了数字信号处理器（DSP） C6678的多核模式,设计了一种基于C6678高速多核DSP硬件平台的实时任务调度软件架构,实现了实时任务调度。通过实际测试,整体设计满足了设计指标。     

通用异步串行收发器UART核在DSP芯片中的设计与实现

UART是广泛使用的串行数据通信电路,因其要求的传输线少,可靠性高,传输距离远,所以系统间互联常采用RS—232接口方式。文章基于Verilog HDL语言,结合有限状态机的设计方法来实现UART,将其核心功能集成到DSP上,使整体设计紧凑、小巧,实现的UART功能稳定、可靠,为DSP的RS—232接口提供了一种新的解决方案。该IP核已用于一款32位浮点DSP芯片的设计中。     

Unsupervised image thresholding: hardware architecture and its usage for FPGA-SoC platform

ABSTRACT

Otsu’s global automatic image thresholding operation is used in various image processing applications. It needs computation of normalized cumulative histogram, mean and cumulative moments that are compute-intensive operations. In this paper, a custom architecture is presented for an efficient computation of Otsu’s algorithm along with its utilization as an intellectual property (IP) core in a field programmable gate array (FPGA) based system-on-chip (SoC) environment for the application of connected component analysis (CCA). A self-normalization technique is employed, where single-cycle, read–modify–write operations are performed with block random access memories (BRAMs) and digital signal processing (DSP)slices. The architecture is designed for 640 × 480 size of images that are captured by a high-resolution analouge camera and buffered in a DDR2 SDRAM of Xilinx ML-507 platform at 25.175 MHz clock frequency. The embedded PowerPC processor core is used to control the frame acquisition process. Experimental results on Virtex-5 xc5vfx70t FPGA device show that the architecture utilizes 1.4% slices, 2.7% BRAMs and 3.9% DSP48E slices. The total power consumption of the design is 1440.59 mW. The proposed architecture as an IP core is able to work in real-time with standard VGA resolution video and requires low computational resources.     

Implementation of a Viterbi Processor for a Digital Communications System with a Time-Dispersive Channel

This paper describes the theory, design, and testing of a Viterbi processor for a digital communication system with intersymbol interference over fading time-dispersive channels. The requirement is to implement the Viterbi algorithm for a channel memory of 9 baud at a data rate of 2400 bits/s. The processor is partitioned into three subprocessors corresponding to the correlation, state metric evaluation, and state decision-making operations. For prototype evaluation, each subprocessor is being implemented as a separate chip using4-5 mum CMOS technology. The architecture, circuit design, and subsystem characterization of the correlator chip are described in some detail. The chip is required to evaluate 1024 state transition metrics in each baud interval (about 400 ns) using a pipeline architecture. Simulation and initial test results verify the correct operation of the chip with an adequate-speed safety margin. The theory of operation and architecture of the state metric chip are described. With off-chip memory for state metric storage, the state transition metrics from the correlator chip are used to determine the winning (optimal) path in the Viterbi trellis and to calculate the corresponding 16-bit state metric for each baud interval. Implementation of the third chip which is required to make a state decision regarding the bit sequence sent is presently being investigated.