Single clock partial scan

Existing partial-scan designs use a separate scan clock to simplify scan flip-flop selection and test generation methods. Such designs require multiple clock trees and create clock-signal routing problems that, in general, require tight control of clock skew. The author examines using the system clock for the scan operation and includes experimental results based on ISCAS89 benchmark circuits     

Designing in power-down test circuits

Built-in self-test circuitry that is active only during testing is described. The benefit of these types of circuits is that defects that are not uncovered within the test circuitry will not contribute to failures in the host's ICs. Thus, the overall reliability of the IC in its targeted application should increase. Also, since the test circuitry is inactive, there will be less overall power consumption. Layout issues, simulation models, and interface/isolation considerations are discussed. Some general design guidelines are given     

Designing new ternary reversible subtractor circuits

The reducing of the width of quantum reversible circuits makes multiple-valued reversible logic a very promising research area. Ternary logic is one of the most popular types of multiple-valued reversible logic, along with the Subtractor, which is among the major components of the ALU of a classical computer and complex hardware. In this paper the authors will be presenting an improved design of a ternary reversible half subtractor circuit. The authors shall compare the improved design with the existing designs and shall highlight the improvements made after which the authors will propose a new ternary reversible full subtractor circuit. Ternary Shift gates and ternary Muthukrishnan–Stroud gates were used to build such newly designed complex circuits and it is believed that the proposed designs can be used in ternary quantum computers. The minimization of the number of constant inputs and garbage outputs, hardware complexity, quantum cost and delay time is an important issue in reversible logic design. In this study a significant improvement as compared to the existing designs has been achieved in as such that with the reduction in the number of ternary shift and Muthukrishnan-Stroud gates used the authors have produced ternary subtractor circuits.     

Board-level partitioning for partial scan using fuzzy logic

We present a board-level partitioning scheme for improved partial scan on the resulting integrated circuits (IC). Fuzzy logic rules and two adaptation techniques allow us to simultaneously minimize four important independent objective functions in the examined problem formulation. The maximum among all sets in the partition are the following quantities: 1) number of scanned nodes in a set; 2) number of incident nets to a set; 3) number of inputs to any set; and finally 4) the period of the global clock. The sets must satisfy upper and lower capacity bounds. We experimented with some ISCAS'89 benchmark circuits and we compared the performance of our tool with four iterative improvement heuristics, each considering only one of the four different functions. Our experimental results indicate that the performance of the proposed tool is very effective     

Lower bounds on arithmetic circuits via partial derivatives

In this paper we describe a new technique for obtaining lower bounds on restricted classes of non-monotone arithmetic circuits. The heart of this technique is a complexity measure for multivariate polynomials, based on the linear span of their partial derivatives. We use the technique to obtain new lower bounds for computing symmetric polynomials (that hold over fields of characteristic zero) and iterated matrix products (that hold for all fields).Dedicated to the memory of Roman Smolensky     

Designing layout–timing independent quantum-dot cellular automata (QCA) circuits by global asynchrony

The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synchronize data flows, and the way to power QCA cells, make the design of QCA circuits quite different from VLSI and introduce a variety of new design challenges and the most severe challenges are due to the fact that the overall timing of a QCA circuit is mainly dependent upon its layout. This fact is commonly referred to as the “layout = timing” problem. To circumvent the problem, a novel self-timed QCA circuit design methodology referred to as the Globally Asynchronous, Locally Synchronous (GALS) Design for QCA is proposed in this paper. The proposed technique can significantly reduce the layout–timing dependency from the global network of QCA devices in a circuit; therefore, considerably flexible QCA circuit design and floorplanning will be possible.     

Precise pose and assembly detection of generic tubular joints based on partial scan data

Neural Computing and Applications - Intelligent and accurate determination of the position and orientation, or pose, of a workpiece which is manually placed is essential for automating fabrication...     

Boundary scan with built-in self-test

The authors propose a way to merge boundary scan with the built-in self-test (BIST) of printed circuit boards. Their boundary-scan structure is based on Version 2.0 of the Joint Task Action Group's recommendations for boundary scan and incorporates BIST using a register based on cellular automata (CA) techniques. They examine test patterns generated from this register and the more conventional linear-feedback shift register. The advantages of the CA register, or CAR, are its modularity, which allows modification without major redesign, its higher stuck-at fault coverage, and its higher transition fault coverage     

Competitive learning with floating-gate circuits

Competitive learning is a general technique for training clustering and classification networks. We have developed an 11-transistor silicon circuit, that we term an automaximizing bump circuit, that uses silicon physics to naturally implement a similarity computation, local adaptation, simultaneous adaptation and computation and nonvolatile storage. This circuit is an ideal building block for constructing competitive-learning networks. We illustrate the adaptive nature of the automaximizing bump in two ways. First, we demonstrate a silicon competitive-learning circuit that clusters one-dimensional (1-D) data. We then illustrate a general architecture based on the automaximizing bump circuit; we show the effectiveness of this architecture, via software simulation, on a general clustering task. We corroborate our analysis with experimental data from circuits fabricated in a 0.35-mum CMOS process.     

Designing Triggers with Trigger-By-Example

One of the obstacles that hinder database trigger systems from their wide deployment is the lack of tools that aid users in creating trigger rules. Similar to understanding and specifying database queries in SQL3, it is difficult to visualize the meaning of trigger rules. Furthermore, it is even more difficult to write trigger rules using such text-based trigger rule languages as SQL3. In this paper, we propose TBE (Trigger-By-Example) to remedy such problems in writing trigger rules visually by using QBE (Query-By-Example) ideas. TBE is a visual trigger rule composition system that helps the users understand and specify active database triggers. TBE retains benefits of QBE while extending features to support triggers. Hence, TBE is a useful tool for novice users to create simple triggers in a visual and intuitive manner. Further, since TBE is designed to hide the details of underlying trigger systems from users, it can be used as a universal trigger interface.     

Synthesizing circuits with implicit stability constraints

Test synthesis constraints embody conditions that a circuit must meet to be fully testable. Algorithms similar to those of automatic test pattern generation transform the circuit and repair rule violations corresponding to the constraints. This form of test synthesis occurs early in the design process; allowing effective investigation of performance and area trade-offs. A prototype implementation indicted that test logic inserted in this way creates little performance or area overhead     

Ferroelectric neuron circuits with adaptive-learning function

A neon circuit which consists of nonvolatile metal-ferroelectric-semiconductor field effect transistors (MFSFETs) and a uni-junction transistor (UJT) has been proposed. In the proposed circuit MFSFETs act as analog memories to store the synaptic weights which can be changed by the adaptive-learning process during the operations. In this paper, we first simulate the operation of the ferroelectric neuron circuit using a circuit simulator, SPICE. It is shown that the output frequency of the proposed neuron circuit can be changed after it processes a certain number of input pulses. Then, we report the fabrication of UJTs and UJT pulse oscillation circuits using silicon-on-insulator (SOI) substrates. It is found that the output frequency increases with decreasing the charging time of the capacitor in the circuit and that the operation at higher frequencies is possible for integrated UJT oscillation circuits. Finally, we demonstrate the memory and learning properties of n-channel ferroelectric-gate FETs using (Pb,La)(Zr,Ti)O₃ (PLZT) films. It is shown that the drain current of the PLZT/SrTiO₃/Si FETs can be controlled by a “write” pulse before the measurements.     

用Excel软件进行起重机总体设计

起重机总体设计是一项十分繁重的工作，为了追求方案最佳化，必须进行多种方案计算比较，而这些工作又多是重复性的工作，编制专用软件又要花大量的精力，作者采用电子表格软件Excel较好的处理了这一工作，值得借鉴和参考。     

Speeding up processing with approximation circuits

Current microprocessors employ a global timing reference to synchronize data transfer. A synchronous system must know the maximum time needed to compute a function, but a circuit usually finishes computation earlier than the worst-case delay. The system nevertheless waits for the maximum time bound to guarantee a correct result. As a first step in achieving variable pipeline delays based on data values, approximation circuits can increase clock frequency by reducing the number of cycles a function requires. Instead of implementing the complete logic function, a simplified circuit mimics it using rough calculations to predict results. The results are correct most of the time, and simulations show improvements in overall performance in spite of the overhead needed to recover from mistakes.     

CMOS circuits with subvolt supply voltages

This overview of multiple-voltage use in low-power design proposes a circuit taxonomy to help determine the most effective low-power techniques for specific circuit types and presents related simulation results     

Piezoelectric microphone with on-chip CMOS circuits

An IC-processed piezoelectric microphone with on-chip, large-scale integrated (LSI) CMOS circuits has been designed, fabricated, and tested in a joint, interactive process between a commercial CMOS foundry and a university micromachining facility. The 2500×2500×3.5 μm ³ microphone has a piezoelectric ZnO layer on a supporting low-pressure chemical-vapor-deposited (LPCVD), silicon-rich, silicon nitride layer. The optimum residual-stress-compensation scheme for maximizing microphone sensitivity produces a slightly buckled microphone diaphragm. A model for the sensitivity dependence of device operation to residual stress is confirmed by applying external strain. The packaged microphone has a resonant frequency of 18 kHz, a quality factor Q≈40, and an unamplified sensitivity of 0.92 mV/Pa. Differential amplifiers provide 49 dB gain with 13 μV A-weighted noise at the input