Determination of gate-bias dependent source/drain series resistance and effective channel length for advanced MOS devices

In this paper, an improved method for determining the gate-bias dependent source and drain series resistances R_D and effective channel length L_eff = L_M − ΔL (L_M is the mask channel length and ΔL is the channel length reduction) of advanced MOS devices is developed for the purpose of providing a better accuracy for the modeling of the current–voltage characteristics of LDD MOSFETs operating from 25 to 120 °C. Our results show that both ΔL and R_SD decrease with increasing gate-bias, but increase with increasing temperature. In addition, the gate-bias dependence of ΔL and R_SD becomes weaker as the temperature rises. Experimental data obtained from devices fabricated using the 0.14 and 0.09 μm DRAM technologies are included in support of the theoretical work developed.     

Dynamic hot-carrier induced degradation in n-channel polysilicon thin-film transistors

The effects of hot-carriers under dynamic stress on the transfer characteristics and the noise performance of n-channel polysilicon thin-film transistors are analysed. The observed decrease in the on-state current is directly related to the mobility of a damaged region extended over a length of about 0.53 μm beside the drain, which is evaluated through analysis of the transfer characteristics at low drain voltage. The mobility degradation in the damaged region is due to the formation of traps located near the polysilicon/gate oxide interface as evidenced by the 1/f noise measurements.     

On the geometrical dependence of low-frequency noise in SiGe HBTs

We present an investigation of the dependence of low-frequency noise on device geometry in advanced npn silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs). The devices examined in this work have fixed emitter width (W_E = 0.4 μm), but varying emitter length (0.5 μm  L_E  20.0 μm), and thus the ratio of the emitter perimeter (P_E) to the emitter area (A_E) varies widely, making it ideal for examining geometrical effects. The SPICE noise parameter A_F extracted from these devices decreases with increasing L_E. Furthermore, the low-frequency noise measured on SiGe HBTs with significantly different P_E/A_E ratios suggests a possibility that the fundamental noise source for the diffusion base current may be located at the emitter periphery. Transistors with different distances between the emitter edge and the shallow trench edge (XEC), and shallow trench edge to deep trench edge (XTC), are also investigated. The SiGe HBTs with a smaller value of XEC have higher low-frequency noise, but no significant difference is found in devices with varying XTC. Explanations of the observed noise behavior are suggested.     

Carrier injection efficiency for the reliability study of 3.5–1.2 nm thick gate-oxide CMOS technologies

The hot carrier (HC) reliability has been investigated in MOSFETs with ultra-thin SiO₂ gate-oxide ranging from T_ox=3.5 to 1.2 nm and in high speed CMOS technologies in order to identify the worst-case of HC injections. Distinctions are obtained between the influence of the T_ox thinning and the shrink of the gate-length with L_G ranging from 0.25 to 0.1 μm. Results show that the worst-case of HC damage can be different from the bias condition of the maximum substrate current (IB) in N-channel devices and of the hot electron (HE) injections in P-channel devices with the T_ox and L_G margin. It is shown that the interface trap generation (ΔN_it) has become the main damage mechanism at long term with the use of the correlation between charge pumping analysis and drain current reduction. We focus on the hole injection efficiency, the extension of the degraded region (ΔL) with the L_G reduction and the influence of the carrier energy which all participate to the degradation of ultra-thin gate-oxide MOSFETs submitted to carrier injections.     

High breakdown voltage Schottky rectifier fabricated on bulk n-GaN substrate

Vertical Schottky rectifiers have been fabricated on a free-standing n-GaN substrate. Circular Pt Schottky contacts with different diameters (50 μm, 150 μm and 300 μm) were prepared on the Ga-face and full backside ohmic contact was prepared on the N-face by using Ti/Al. The electron concentration of the substrate was as low as 7 × 10¹⁵ cm⁻³. Without epitaxial layer and edge termination scheme, the reverse breakdown voltages (V_B) as high as 630 V and 600 V were achieved for 50 μm and 150 μm diameter rectifiers, respectively. For larger diameter (300 μm) rectifiers, V_B dropped to 260 V. The forward turn-on voltage (V_F) for the 50 μm diameter rectifiers was 1.2 V at the current density of 100 A/cm², and the on-state resistance (R_on) was 2.2 mΩ cm², producing a figure-of-merit (V_B)²/R_on of 180 MW cm⁻². At 10 V bias, forward currents of 0.5 A and 0.8 A were obtained for 150 μm and 300 μm diameter rectifiers, respectively. The devices exhibited an ultrafast reverse recovery characteristics, with the reverse recovery time shorter than 20 ns.     

Source/drain optimization of underlapped lightly doped nanoscale double-gate MOSFETs

The impact of the spacer length at the source (L_s) and drain (L_d) on the performance of symmetrical lightly-doped double-gate (DG) MOSFET with gate length L = 20 nm is analyzed, with the type and doping concentration of the spacers kept the same as in the channel material. Using the transport parameters extracted from experimental data of a double-gate FinFET, simulations were performed for optimization of the underlapped gate-source/drain structure. The simulation results show that the subthreshold leakage current is significantly suppressed without sacrificing the on-state current for devices designed with asymmetrical source/drain extension regions, satisfying the relations L_s = L/2 and L_d = L. In independent drive configuration, the top-gate response can be altered by application of a control voltage on the bottom-gate. In devices with asymmetrical source/drain extension regions, simulations demonstrate that the threshold voltage controllability is improved when the drain extension region length is increased.     

Multilayered coated infra-red surface plasmon resonance fibre sensors for aqueous chemical sensing

A series of surface plasmonic fibre devices were fabricated by depositing multiple thin coatings on a lapped section of a standard single mode telecoms fibre forming a D-shaped section and then inscribing a grating-type structure using UV light. The coatings consisted of base coatings of semi-conductor (germanium) and dielectric (silicon dioxide) materials, followed by different metals. These fibre devices showed high spectral refractive index sensitivity with high coupling efficiency in excess of 40 dB for indices in the aqueous regime and below, with estimated index sensitivities of Δλ/Δn = 90–800 nm from 1 to 1.15 index range and Δλ/Δn = 1200–4000 nm for refractive indices from 1.33 to 1.39.     

The influence of stud bumping stress on device degradation in scaled MOSFETs

This paper presents the effect of area bumping on device degradation in scaled metal-oxide-semiconductor field-effect transistors (MOSFETs). We have investigated the gate channel length dependence of g_m degradation after stud bumping above the MOSFETs and changes in the charge pumping currents for those devices. The von Mises’s equivalent stress is used to simulate the distribution of mechanical stress at the gate edges. From the relationship between the distribution of the von Mises’s equivalent stress and the change in the charge pumping currents after stud bumping, we show that stress concentrates within 0.1 μm of the gate edges. Furthermore, by estimating the amount of increased interface-state density we predicted that stud bumping stress greatly influences the device degradation of scaled MOS devices.     

New insight on negative bias temperature instability degradation with drain bias of 28 nm High-K Metal Gate p-MOSFET devices

The degradation of negative bias temperature instability (NBTI) on 28 nm High-K Metal Gate (HKMG) p-MOSFET devices under non-uniform stress condition has been systematically studied. We found the asymmetry between forward and reverse Idsat shift under non-uniform stress condition is significant for long channel devices even under low drain bias stress (e.g., Vds = −0.1 V and gate channel length L = 1 μm), and seems to be dominated by a minimally required critical length (L = 0.2 μm derived from the experimental data). To the authors’ best knowledge, these are new phenomena reported. We attribute these anomalous NBTI characteristics with drain bias to the local self-heating (LSH) activated NBTI degradation mechanism. One semi-empirical analytical model, which fits well with our experimental data, is then proposed in this paper.     

Optimization of HfSiON using a design of experiment (DOE) approach on 0.45 V Vt Ni-FUSI CMOS transistors

We report for the first time that the optimization of a HfSiON process on Ni-FUSI devices is best tackled using a design of experiments (DOE [Myers RH, Montgomery. Response surface methodology. New York, DC: Wiley; 1995]) approach. We show that a DOE allows for directly linking process parameters to relevant short channel performance metrics. By tuning the SiO₂ thickness, HfSiO thickness, Hf concentration, nitridation parameters and by using response surface modeling (RSM), we report an improvement of 12%/17% in nMOS/pMOS drive current (I_dsat 600/255 uA/μm at I_off = 20 pA/μm and V_dd = 1.1 V) over our reference process. In parallel, we demonstrate that by selecting the right parameters, plasma nitridation can outperform thermal nitridation with NH_3. We believe that this new approach will be useful for device engineers and can be easily applied.     

Power Trench MOSFETs with very low specific on-resistance for 25V applications

In this paper, an investigation of the benefits of deep ultra violet lithography for the manufacturing of Trench MOSFETs and its impact on device performance is presented. We discuss experimental results for devices with a pitch size down to 0.6 μm fabricated with an unconventional implant topology and a simplified manufacturing scheme. The fabricated Trench MOSFETs are benchmarked against previously published TrenchMOS technologies by de-embedding the parasitic substrate resistance, revealing a record-low specific on-resistance of 5.3 mΩ mm² at a breakdown voltage of 30 V (V_gs = 10 V).     

A two-dimensional semi-analytical analysis of the subthreshold-swing behavior including free carriers and interfacial traps effects for nanoscale double-gate MOSFETs

In the present paper, an accurate surface potential and the subthreshold swing (S) models including the free carriers and interfacial traps effect have been presented. Exploiting these new device models, we have found that the incorporation of the free carriers' effect leads to the improvement of the subthreshold swing accuracy in comparison with the classical models. The inclusion of the free carriers has a major role in determining the subthreshold parameters behavior due to the extra surface potential generated at the interface, which may affect the electric field and carriers transport in weak inversion regime. We have demonstrated that S is very sensitive to the short channel lengths (L less than 40 nm). For a device with a small silicon body thickness (t_si=5 nm), S is increased dramatically with the reduction of the channel length. The developed approaches are verified and validated by the good agreement found with the 2D numerical simulations for a wide range of device parameters and bias conditions. The proposed models can also be implemented into devices simulators, such as SPICE, to study the degradation of nanoscale digital CMOS-based circuits.     

Evaluation of SiGe:C HBT intrinsic reliability using conventional and step stress methodologies

The reliability of SiGe:C HBT devices fabricated using the Freescale’s 0.35-μm RF-BICMOS process was evaluated using both conventional and step stress methodologies. This device technology was assessed to determine its capability for various power amplifier applications (e.g., WLAN, Bluetooth, and cellular phone), which are more demanding than conventional circuit designs. The step stress method was developed to allow a rapid evaluation of product reliability, as well as, a quick method to monitor product reliability. For all tests the collector current I_C and collector voltage V_C were kept constant throughout the test, and the current gain β (I_C/I_B) was continuously monitored. The nominal bias condition was V_C = 3.5-V and J_C = 50-kA/cm² (or 0.5-mA/μm²). The “failure criterion” for all reliability evaluations was −10% degradation in β from the initial value at the start of each stress test or interval. The median time to failure (MTTF) at a junction temperature (T_JCN) of 150 °C for the conventional stress test was 1.86E6-h, and the thermal activation energy was 1.33-eV. In contrast for the temperature step stress tests the combined results gave an MTTF at T_JCN = 150 °C of 5.2E6-h and a thermal activation energy of 1.44-eV. Considering the differences in the two test methods, these results are quite close to one another. The intrinsic reliability of this device at the nominal bias condition and T_JCN = 150 °C is more than adequate for a 5-year system life.     

A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32 nm node and beyond

A novel SiGe-S/D structure for high performance pMOSFET called two-step recessed SiGe-source/drain (S/D) is developed with careful optimization of recessed SiGe-S/D structure. With this method, hole mobility, short channel effect and S/D resistance in pMOSFET are improved compared with conventional recessed SiGe-S/D structure. To enhance device performance such as drain current drivability, SiGe region has to be closer to channel region. Then, conventional deep SiGe-S/D region with carefully optimized shallow SiGe SDE region showed additional device performance improvement without SCE degradation. As a result, high performance 24 nm gate length pMOSFET was demonstrated with drive current of 451 μA/μm at V_dd of 0.9 V and I_off of 100 nA/μm (552 μA/μm at V_dd of 1.0 V). Furthermore, by combining with V_dd scaling, we indicate the extendability of two-step recessed SiGe-S/D structure down to 15 nm node generation.     

NBTI and hot-carrier effects in accumulation-mode Pi-gate pMOSFETs

Negative bias temperature instability (NBTI) and hot-carrier induced device degradation in accumulation-mode Pi-gate pMOSFETs have been studied for different fin widths ranging from 20 to 40 nm. The NBTI induced device degradation is more significant in narrow devices. This result can be explained by enhanced diffusion of hydrogen at the corners in multiple-gate devices. Due to larger impact ionization, hot-carrier induced device degradation is more significant in wider devices. Finally, hot-carrier induced device degradation rate is highest under stress conditions where V_GS = V_TH.     

Degradation of n-channel a-Si:H/nc-Si:H bilayer thin-film transistors under DC electrical stress

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated, using as channel material hydrogenated amorphous silicon (a-Si:H)/nanocrystalline silicon (nc-Si:H) bilayers, deposited at 230 °C by plasma-enhanced chemical vapor deposition, and SiN_x as gate dielectric. The stability of these devices is investigated under three bias stress conditions: (i) gate bias stress (V_G = 25 V, V_D = 0), (ii) on-state bias stress (V_G = 25 V, V_D = 20 V) and (iii) off-state bias stress (V_G = −25 V, V_D = 20 V). It is found that the TFT degradation mechanisms are strongly dependent on the bias stress conditions, involving generation of deep and tail states in the active area of the channel material, carrier injection (electrons or holes) within the gate insulator and generation of donor trap states at the gate insulator/channel interface. The common features and the differences observed in the degradation behaviour under the different bias stress conditions are discussed.     

Hot-carrier induced series resistance enhancement model (HISREM) of nMOSFET's for circuit simulations and reliability projections

This paper proposes a physically realizable reliability model of nMOSFET's that is applicable for reliability projections in IC design. We have devised a hot-carrier induced series (drain) resistance enhancement model (HISREM) which is based on the increase of the interface trapped charge (ΔNit) near the drain region and is physically realizable in circuit simulations of the hot-carrier induced degradation under operating conditions. The proposed HISREM requires only one parameter (ΔNit) for reliability projections in IC design without extraction of a set of stressed parameter files. The proposed HISREM s shows a good agreement between the simulation results from SPICE and experiment data of the hot-carrier induced degradation of device characteristics. The HISREM has been demonstrated by employing a NMOS inverter and a conventional CMOS operational amplifier. The HISREM is shown to be much simpler and more efficient for reliability projections in both digital and analog IC design rather than the commercial reliability simulator with parameter degradation models which require extraction of a set of stressed parameter files (i.e., Vto, γ, μ_o, θ, V_max, ).     

Study of passivation defects by electroluminescence in AlGaN/GaN HEMTS on SiC

This paper presents a new method of passivation control by electroluminescence (EL) in 0.15 μm AlGaN/GaN HEMT. The electroluminescence signature in one finger HEMTs (W = 1 × 100 μm), and eight fingers ones (W = 8 × 125 μm), is modified by defects located at the passivation/semiconductor interface and is characterized by a light emission along the drain contact. This abnormal emission reveals some modification of the electric field distribution in the gate-drain space probably induced by traps located at the passivation/semiconductor interface. These traps contribute to the creation of a virtual gate in the gate-drain space.     

An investigation of surface state capture cross-sections for metal–oxide–semiconductor field-effect transistors using HfO2 gate dielectrics

MOSFETs and MOSCs incorporating HfO₂ gate dielectrics were fabricated. The I_DS–V_DS, I_DS–V_GS, gated-diode and C–V characteristics were investigated. The subthreshold swing and the interface trap density were obtained. The surface recombination velocity and the minority carrier lifetime in the field-induced depletion region measured from the gated diodes were about 2.73 × 10³ cm/s and 1.63 × 10⁻⁶ s, respectively. The effective capture cross section of surface state was determined to be 1.6 × 10⁻¹⁵ cm² using the gated-diode technique in comparison with the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO₂ gate oxide was also made.