离子束刻蚀HgCdTe成结机制分析

根据由离子束刻蚀HgCdTe pn结C-V曲线,判定其为线性缓交结;由1/C3-V曲线斜率可知杂质浓度分布梯度.利用泊松方程(零偏压时耗尽层宽度作为边界条件)积分计算出其电场分布、电势分布等重要结特性.并且进一步从微观理论分析讨论了离子束刻蚀HgCdTe成结机制过程.     

ITO/Si/Al结构太阳电池pn结光电特性仿真研究

设计了基于SILVACO-TCAD仿真工具的具有ITO/Si/Al结构太阳电池单元,研究了在此结构中pn结特性对光电流的影响.研究表明,pn结位置越浅,光电流越大;光电流随pn结中杂质浓度增加而先增加后减小,电流极值向短波方向移动.     

激光束制作硅Pn结

最近,英国英格兰的赫里特-瓦特大学发明一种激光化学汽相淀积(CVD)方法制成具有整流特性的pn结.这种pn结具有类同硅单晶pn结的I/V特性,但不是理想的突变结.轻掺杂的pn结的整流比率为250:1(在正向压降为0.8V下,结面积为10×2μm),在2V下     

简讯

为了改善功率半导体器件的耐压特性,日本东芝公司最近研究成功硅直接成结法.方法是将两片洗净干燥后的抛光片,正面相重叠,在N_2气中1000℃下加热,使重叠处结合成一体,当两片硅片分别为P型和n型时,即可形成pn结.新工艺能精确控制结深及杂质浓度分     

硼扩散源及其在半导体器件中的应用

在半导体器件工艺中,多数情况是在硅衬底中掺 p 型或者 n 型杂质形成 pn 结。而最基本的 pn 结形成方法,一般采用杂质的热扩散法。通常,这种扩散工艺是由预沉积和再扩散两步工序组成的。首先是预沉积工序,它是在硅表面形成浅的高浓度杂质扩散区,其次是再扩散工序,它是使结更深地向硅衬底内推进,控制表面杂质浓度。认为控制了这个杂质浓度和结深就确定了半导体器件的性能,这种说法也并不过分。而且还可以说,预沉积将大大影响扩散的好坏。因此,本文简要说明一下关于预沉积中 p 型杂质(硼)扩散源的情况。同时,介绍一下最近 Owens-Illinois 公司研究的新的硼扩散源“Boro+~(TM)”(以下省略 TM)的优点。     

变容二极管C-V特性的控制技术

本文针对变容二极管生产难点：C－V曲线的控制,在理论上分析了PN结纵横向结构对PN结C－V特性、串联电阻、反向电流的影响,得出了适当减小芯片面积,调高杂质浓度可以不增大串联电阻而减小反向电流、改善C－V特性的结论,并应用于生产。     

GaAs超突变结变容管的C—V特性和击穿电压

本文假设了一种与外延材料的掺杂分布比较接近的杂质浓度分布函数,导出了超突变结的电容—电压(C—V)特性以及容—压斜率指数与外加电压(γ—V)关系的计算公式,并计算了GaAs超突变结的雪崩击穿电压V_B.给出了C—V、γ—V和V_B的计算结果.     

一种基于传输线理论的pn结二极管小信号模型

为了精确表征毫米波频段pn结二极管的特性,提出了一种基于传输线理论的pn结二极管小信号模型。该模型包括表征pn结的本征部分和寄生部分。以量化的pn结耗尽区串联电阻作为中间项,通过非线性传输线理论近似方法,推导出全新的pn结二极管小信号模型的拓扑结构。通过导纳参数和阻抗参数的参数解析提取方法,提取等效电路中各元件参数值。使用某磷化铟(InP)工艺线加工所得2×3μm、8×8μm、4×16μm二极管的散射参数数据进行验证。结果表明,在1～110 GHz频率范围内,不同偏压的模型仿真结果与测试结果均吻合较好,同时也能表明模型在毫米波频段内有良好的适用性。     

衬底温度对NiO:Cu/ZnO异质pn结的光电性能影响

利用磁控溅射方法改变衬底温度,制备了一系列Ni O:Cu/ZnO异质pn结。实验结果表明,当衬底温 度从室温升高到300℃时,NiO:Cu/ZnO异质pn结的整流特性明显得到 改善;与此同时,NiO:Cu/ZnO异质 pn结的光学透过率也从40%增大到80%。这可能是由于NiO:Cu薄膜结晶质量改善,薄膜内 缺陷减少所致。 继续增加衬底温度至400℃,异质结的整流特性有所削弱,这可能是 由于生长在异质结下层 的NiO:Cu薄膜影响了其上ZnO薄膜的生长,进而影响到异质结的整流特性。这一结论,得到 X射线衍射(XRD)、原子力显微镜(AFM)和紫外(UV)谱测试结果的支持。     

长波长InGaAs扩散结PIN光电二极管正面入光结构的理论分析

本文指出,对扩散pn结的正面入光结构,突变结理论有一定局限性。由于p~+区内杂质浓度的分布,在扩散区中存在十分强的自建漂移场,因而光生载流子将在自建场的作用下漂移进pn结内。由于载流子的漂移速度V_d远大于扩散速度V_f,因此可制得性能优异的PIN光电二极管,制作工艺比背面入光结构简单。已制得光电响应时间低达80ps的正面入光PIN二极管。     

Characteristics of diffused P-N junctions in epitaxial layers

A one-dimensional analysis has been made to determine properties of diffused p-n junctions in epitaxial layers with nonuniform impurity concentration. Impurity diffusion from the surface and from the substrate is assumed to have complementary error function distribution. The transcendental equations obtained by analytical integration of Poisson's equation were evaluated numerically with the IBM 7090/94. Junction depth, impurity gradient and impurity level at the junction are given for a variety of diffusion parameters and impurity concentrations. In addition, graphs are presented, showing the relationship between reverse voltage and depletion layer thickness, capacitance per unit area, and peak electric field for the case of silicon. A comparison between the actual impurity profile and the usual linear approximation using the impurity gradient at the junction gives the range of depletion layer thickness or reverse voltage in which such an approximation is justified. Further, examples are presented of the electric field distribution in the depletion layer for several impurity concentration profiles. Calculated and experimentally determined values of some readily accessible junction characteristics show reasonably good agreement.     

Si-Si直接键合的杂质分布

在Si-Si直接键合过程中,界面处存在一层很薄的厚度恒定的本征SiO2.Si对SiO2中的杂质的抽取效应,导致了杂质在界面处的浓度大大降低,根据改进了的杂质在Si-Si直接键合片中分布模型,推导出了杂质分布的表达式,在理论上和实验上都对该式进行了验证.杂质通过SiO2再向Si中扩散的杂质总量与Si-Si扩散相比大大减少,使所形成的p-n+结的结深减小.     

Si-Si直接键合的杂质分布

在Si-Si直接键合过程中,界面处存在一层很薄的厚度恒定的本征SiO2.Si对SiO2中的杂质的抽取效应,导致了杂质在界面处的浓度大大降低,根据改进了的杂质在Si-Si直接键合片中分布模型,推导出了杂质分布的表达式,在理论上和实验上都对该式进行了验证.杂质通过SiO2再向Si中扩散的杂质总量与Si-Si扩散相比大大减少,使所形成的p-n 结的结深减小.     

Examination of electrostatic potential distribution across an implanted p-n junction by electron holography

In the manufacture of semiconductor microelectronic devices, a p-n junction is formed usually by implanting a high concentration of impurity into a less heavily doped region and then heat annealing. A Si/Si p-n junction test sample has been made following the above practical process and thinned for electron holographic observation by using argon ion-milling. From the reconstructed phase image, the phase shift induced by potential drop across p-n junction can be seen clearly. To characterize quantitatively this potential drop, the mean inner potential V0 of silicon was measured precisely by electron holographic method. By measuring 25 different crystalline silicon spheres with diameter ranging from 40 to 170 nm, an average result of V0 = 12.16 +/- 0.83 V was obtained. By using this V0 value, a quantitative measurement yields the potential drop approximately 0.70 V, which is reasonably consistent with expected Si/Si junction parameter. The thickness of electric dead layer in depletion region produced from this measuring is approximately 20 nm on each sample surface.     

A method for determining the emitter and base lifetimes in p-n junction diodes

A method is described that provides an experimental means for the first time to separate and determine the emitter and base lifetimes in a p-n diode after the junction has been fabricated. In the method, several static and transient measurements are analyzed using physical models of the diode characteristics. To illustrate the method, diffused silicon diodes are fabricated having substrate (base) impurity concentrations ranging from 10¹⁴to nearly 10¹⁷phosphorous atoms per cubic centimeter. The results show an emitter lifetime that is much smaller than the base lifetime in the diode having the highest base doping concentration. In this diode, the recombination current from the emitter is 65 percent of the recombination current from the base, demonstrating the significance of the emitter in governing the static current-voltage dependence. The importance of emitter recombination to the transient characteristics is also demonstrated. The paper emphasizes the techniques by which the base and emitter lifetimes are distinguished. It also demonstrates the need for carefully basing the quantitative analysis of the measurements on the underlying diode physics. The method described here applies not only to p-n diodes but also to junction solar cells and transistors.     

Peripheral and diffused layer effects on doping profiles

The impurity profile of an epitaxial layer has been determined from the capacitance-voltage (C-V) characteristics of a diffused p-n junction. TheC-Vcharacteristics were corrected for peripheral and diffused layer effects. Peripheral capacitance corrections account for the lateral spread of the space-charge region, whose periphery is assumed to be cylindrical. Diffused layer corrections account for the penetration of the space-charge region into the diffused layer, assumed to be Gaussian. The importance of these corrections can be estimated from graphs that cover a wide range of practical diffusion conditions and junction diameters. The sensitivity of profiles to the assumed Gaussian diffusion are examined. Finally, the corrections are applied to an experimental junction and the results are presented from a computer printout. The Appendix includes graphs for determining the space-charge width of a Gaussian-diffused silicon junction, given the diffused layer sheet resistance, junction depth, and background concentration.     

Avalanche breakdown characteristics of a diffused P-N junction

A one-dimensional analysis is presented on the avalanche breakdown characteristics of a diffused p-n junction diode. By numerically integrating the carrier ionization rate in a junction space-charge layer, avalanche breakdown voltage is calculated for diffused diodes of silicon and germanium; this voltage is graphically illustrated throughout a range of parameters applicable to most practical situations. In addition, for calculating the maximum cutoff frequency of varactor diodes, junction capacity is similarly illustrated assuming the device is biased to avalanche breakdown. From these illustrations, and from an accompanying nomograph which relates the physical constants of a junction to its impurity atom gradient, the above parameters can be readily established without additional calculations. Further, examples are also presented to demonstrate the reduction of breakdown voltage resulting from a rapid increase of conductivity within the space-charge layer of a diffused p-n junction; this situation approximates many epitaxial and double diffused structures.     

重掺杂发射区中禁带宽度和少子复合寿命的确定方法

禁带宽度和少子复合寿命是硅晶体管发射区中重要的物理参数。本文利用p-n结反向扩散电流的温度特性和借助于线性外推法,提出了一种确定绝对零度时禁带宽度的新方法。由于发射区重掺杂,本文考虑了载流子的费米-狄拉克统计分布。提出了确定发射区中少子复合寿命的方法。该方法简便实用。     

Variability study and design considerations of p-n junction hyperabrupt varactor diodes

Variability analysis of the hyperabrupt epitaxial p-n junction varactor diode has been carried out. Results are given for the dependence of the electrical parameters on the various physical parameters of the device. A comparison has been made between a Schottky hyperabrupt varactor and a p-n junction hyperabrupt varactor, and the undesirable effects of the impurity compensation in the latter case are clearly brought out.     

Calculations of cutoff frequency, breakdown voltage, and capacitance for diffused junctions in thin epitaxial silicon layers

Recent developments in high-quality silicon varactors for low-noise parametric amplifiers and high-efficiency harmonic generators necessitate the use of epitaxial silicon layers that are thinner than 10 microns, with resistivity less than 1 Ω-cm. This paper extends Breitschwerdt's recent calculations [1] to such thin epitaxial layers, and also includes the calculation of series resistance and capacitance per unit area in a range useful for microwave diode design. A planar geometry for the junction has been assumed. The impurity distribution of the in-diffusion from the surface and the out-diffusion from the substrate are assumed to be complementary error functions. Depletion layer characteristics of the p-n junction-- including junction depth, impurity gradient at the junction, depletion layer width, capacitance per unit area, and avalanche breakdown voltage--are predicted for various epitaxial layer resistivities. The capacitance per unit area at breakdown is also presented in graphical form. Series resistance has been obtained by numerical integration of various impurity distributions. Zero-bias cutoff frequency for various layer thicknesses is presented graphically as a function of junction depth and breakdown voltage. The calculations predict that there are optimum diffusion conditions for maximum cutoff frequency and for maximum breakdown voltage with a given epitaxial layer thickness. They indicate that the optimum zero-bias cutoff frequency is nearly inversely proportional to the thickness of the epitaxial layer. For instance, the maximum cutoff frequency of a junction in a 2-µ layer can exceed 600 GHz compared with 300 GHz in a 4-µ layer, and 140 GHz in an 8-µ layer. Calculated and experimentally determined characteristics show reasonably good agreement.