COMS LNA的ADS设计研究

结合一个具体的低噪声放大器(LNA)设计实例,介绍了如何运用射频设计软件ADS(Advanced Design System)对CMOS低噪声放大器进行电路设计和仿真。设计中先初步构建了一个共源共栅结构的低噪声放大器电路,然后利用ADS对电路进行调试和优化,结合调试的过程说明了使用ADS的一些方法和技巧,并且最终设计出低功耗、低噪声、高增益、高稳定性的低噪声放大器,仿真的各项参数都达到了预期的指标要求。     

无线应用中的低噪声放大器设计与分析

低噪声放大器在接收系统中能降低系统的噪声和提高接收机灵敏度,是接收系统的关键部件.描述了一种用于无线通信射频(RF)前端的低噪声放大器(LNA)的设计,先总体阐述了低噪声放大器的主要技术和性能指标,然后在采用ATF34143微波晶体管的基础上,依据低噪声放大器的各项指标来同步进行电路的设计、优化和ADS仿真,结果表明设计的低噪声放大器完全满足性能指标要求,其功率增益可达16dB,噪声系数(NF)在0.5dB以下.     

利用Cadence设计COMS低噪声放大器

结合一个2.4 GHz CMOS低噪声放大器(LNA)电路,介绍如何利用Cadence软件系列中的IC 5.1.41完成CMOS低噪声放大器设计.首先给出CMOS低噪声放大器设计的电路参数计算方法,然后结合计算结果,利用Cadence软件进行电路的原理图仿真,并完成了电路版图设计以及后仿真.仿真结果表明,电路的输入/输出均得到较好的匹配.由于寄生参数,使得电路的噪声性能有约3 dB的降低.对利用Cadence软件完成CMOS射频集成电路设计,特别是低噪声放大器设计有较好的参考价值.     

精密放大器和低噪声失调电路技术

介绍了精密放大器的现状和实现精密放大器的低噪声失调电路技术,着重讨论了自稳零和斩波稳零电路技术,定量分析了这两类电路技术对电路噪声的影响,给出了各自的仿真结果。理论分析和仿真结果均表明,该两类电路技术能很好地抑制电路的失调和噪声,实现微弱传感器信号的精确放大。最后对精密放大器的未来发展空间作了展望。     

微波低噪声放大器的设计与仿真

低噪声放大器在接收系统中能降低系统的噪声和接收机灵敏度,是接收系统的关键部件。文中按照低噪声放大器电路的设计要求,完成了2GHz基站前端射频低噪声放大器的电路设计,并通过ADS仿真软件对电路进行仿真和优化。最终表明,采用本方案设计的LNA增益约为15dB,噪声系数约为1．2dB,性能稳定,完全达到了通信接收机中对LNA指标的要求。     

射频低噪声放大器的ADS设计

本文首先简要介绍了低噪声放大器设计的理论基础,并以2.1-2.4Ghz低噪声放大器为例,详细阐述了如何利用Agilent公司的ADS软件进行分析和优化设计该电路的过程,仿真结果完全满足设计指标,最后对微波电路的容差特性进行了模拟分析,对于S波段低噪声放大器的设计研究有着重要的参考价值.     

基于ADS仿真的宽带低噪声放大器设计

讨论了超高频(UHF)波段宽带、高增益低噪声放大器的设计方法及设计过程,阐述了器件的选择、电路形式和元件初值的确定。利用高级设计系统(Advanced Design System,ADS)进行优化,并给出优化后的仿真结果。设计低噪声放大器,还要考虑结构和工艺。给出主要技术指标的测试结果,与仿真结果比较一致。结果表明,基于ADS软件仿真设计地低噪声放大器性能好、成本低、体积小、成品率高。     

基于gm/Id方法的跨阻放大器设计

针对短沟道晶体管数学模型高复杂度问题,文章提出了一种适用于刻画短沟道晶体管模型的gm/Id方法.该方法主要通过建立电路指标与晶体管尺寸的关系来优化电路性能.采用gm/Id方法设计了一种低功耗、低噪声和宽带宽的2.5 Gbit/s跨阻放大器,并进行了版图后仿真,仿真结果表明,当光电二极管电容为250 fF、跨阻放大器的低...     

X 波段雷达接收机中低噪声放大器的研究

现代雷达系统结构对接收机的性能提出了更高的要求.低噪声放大器能降低系统的噪声和提高接收机灵敏度,是接收系统的重要组成部分.本文设计的低噪声放大器应用于接收机的前端,利用集成芯片 ATF36163完成了电路的设计并且通过研究 RF 电路中的参数灵敏度对该低噪声放大器进行了灵敏度分析.结果表明:经过参数灵敏度分析的低噪声放大器不仅符合接收机对 LNA 的指标要求,还能使性能更加稳定     

低噪声放大器（LNA）的网络匹配设计方法研究

研究分析了低噪声放大器的设计方法,介绍了低噪声放大器的特点,同时还介绍了低噪声放大器的网络组成和性能指标.给出了应用一种网络匹配法设计的低噪声放大器,并对电路进行了S参数和NF的仿真,并采用Asoft公司的Designer软件包通过模拟集成电路国家重点实验室双极晶体管模型进行了设计分析.结果证明:这种应用Smith Tool工具设计网络匹配电路具有方便快捷的优点,可符合工业基本要求.     

5.8GHzWiMAX低噪声放大器设计与仿真

介绍了一种基于IEEE802.16标准的高频段WiMAX低噪声放大器(LNA)的设计方法,工作频段在5.8 GHz,采用稳 茂0.15 μm pHEMT工艺4×50 μm晶体管大信号模型,选用Current-Reused结构作为LNA电路结构,并优化设计LNA的电路 偏置电路.利用Agilent公司的 ADS2008 ...     

Design of a capacitor cross-coupled dual-band LNA with switched current-reuse technique

This paper presents the design of a 2.5/3.5-GHz dual-band low-power and low-noise CMOS amplifier (LNA), which uses the capacitor cross-coupling technique and current-reuse method with four switches. The proposed LNA uses a single RF block and a broadband input stage, which is a key aspect for the easy reconfiguration of a dual-band LNA. Switching at the inter-stage and output allows for the selection of a different standard. The dual-band LNA attenuates the undesired interference of a broadband gain response circuit, which allows the linearity of the amplifier to be improved. The capacitor cross-coupled gm-boosting method improves the NF and reduces the current consumption. The proposed LNA employs a current-reused structure to decrease the total power consumption. The inter-stage and output switched resonators switch the LNA between the 2.5-GHz and 3.5-GHz bands. The proposed dual-band LNA optimises power consumption by the securing gain, noise figure and linearity. The simulated performance reveals gains of 16.7 dB and 19.6 dB, and noise figures of 3.04 dB and 2.63 dB at the two frequency bands, respectively. The linearity parameters of IIP3 are ?5.7 dBm at 2.5 GHz and ?9.7 dBm at 3.5 GHz. The proposed dual-band LNA consumes 5.6 mW from a 1.8 V power supply.     

一种三态增益控制的单片低噪声放大器

报道了一种移动通信系统中用的采用使能电路实现三态增益控制的单片低噪声放大器。详细阐述了使能电路和负反馈支路的设计方法。主要研制结果为 :f0 为 180 0 MHz;G1为19d B、N F1为 2 .0 d B;G2 为 10 d B、N F2 为 2 .7d B;G3 为 - 2 0 d B。     

Noise figure optimization of inductively degenerated CMOS LNAs with integrated gate inductors

This paper discusses noise figure optimization techniques for inductively degenerated cascode CMOS low-noise amplifiers (LNAs) with on-chip gate inductors. Seven different optimizations techniques are discussed. Of these, five new cases provide power match and balance the transistor noise contribution and the noise contribution from all parasitic resistances in the gate circuit to achieve the best noise performance under the constraints of integrated gate inductor quality factor, power consumption, and gain. Three of the power matched techniques (two power constrained optimizations and a gain-and-power constrained optimization) are recommended as design strategies. These three optimization techniques significantly improve the noise figures for LNA designs that are to employ on-chip gate inductors.     

基于Multisim 10的射频LNA仿真和设计

NI Multisim 10是著名的EDA软件,其仿真功能非常强大,RF电路中LNA的设计是一个难题。使用Multisim设计RF LNA电路,利用虚拟网络分析仪和Smith圆图,对典型RF LNA电路的各种参数进行仿真测试,进而设计阻抗匹配网络,优化电路性能,在设计实践中取得了很好的效果。这对于通信电子产品的设计,对于RF电路的教学和创新型实验具有重要的意义。     

适合批量生产的低噪声放大组件设计

为了满足大批量生产的需求,从电路原理、工艺装配、调试测试等方面考虑,对放大组件中正交桥、限幅器、偏置电路、电压转换、放大电路和结构工艺等方面进行优化设计。并通过计算机仿真软件ADS和HFSS优化电路拓扑,采用表面贴装技术实现组件装配。有自适应功能的偏置电路稳定了FET的工作电流和工作电压,有效地简化了调试和工艺步骤。经试验验证,组件调试简单、一致性好,提高了生产效率,实现了稳定的批量生产。     

2.45 GHz 0.18 μm全差分CMOS低噪声放大器设计

设计了一个基于TSMC 0.18 μm CMOS工艺的2.45 GHz全差分CMOS低噪声放大器.根据电路结构特点,采用图解法对LNA进行功耗约束下的噪声优化,以选取最优的晶体管栅宽;设计了仅消耗15 μA电流的偏置电路;采用在输入级增加电容的方法,在改善输入匹配网络特性的同时,解决了栅极电感的集成问题.仿真结果表明:LNA噪声系数为1.96 dB,功率增益S_(21)超过20 dB,输入反射系数S_(11)和输出反射系数S_(22)分别小于-30 dB和-20 dB,反向功率增益S_(12)小于-30 dB,1 dB压缩点和三阶互调输入点IIP3分别达到-17.1 dBm和-2.55 dBm,整个电路在1.8 V电源下功耗为22.4 mW.     

A novel CMOS low-noise amplifier design for 3.1- to 10.6-GHz ultra-wide-band wireless receivers

An ultra-wideband (UWB) 3.1- to 10.6-GHz low-noise amplifier (LNA) employing a common-gate stage for wideband input matching is presented in this paper. Designed in a commercial 0.18-/spl mu/m 1.8-V standard RFCMOS technology, the proposed UWB LNA achieves fully on-chip circuit implementation, contributing to the realization of a single-chip CMOS UWB receiver. The proposed UWB LNA achieves 16.7/spl plusmn/0.8 dB power gain with a good input match (S11<-9 dB) over the 7500-MHz bandwidth (from 3.1 GHz to 10.6 GHz), and an average noise figure of 4.0 dB, while drawing 18.4-mA dc biasing current from the 1.8-V power supply. A gain control mechanism is also introduced for the first time in the proposed design by varying the biasing current of the gain stage without influencing the other figures of merit of the circuit so as to accommodate the UWB LNA in various UWB wireless transmission systems with different link budgets.     

用于SiGe HBT LNA的新型双有源偏置电路的设计

偏置工作点是影响低噪声放大器(LNA)线性度的因素之一.为了保证LNA能够更好地对信号进行线性放大,稳定的偏置工作点对于放大器来说显得尤为重要.提出了一种新型有源偏置技术,通过同时采用两个电流源为LNA提供直流偏置,以达到稳定放大器偏置工作点的目的.基于JAZZ 0.35 μm SiGe工艺,采用该新型双有源偏置技术,设计了一款LNA.在1.8～2.2 GHz频带时,放大器的增益为22.03±0.46 dB,噪声系数小于3.7dB,2.0 GHz时的输入3阶交调点(IIP3)为5 dBm,相对于传统无源偏置的LNA提高了10 dBm.仿真验证了该新型有源偏置技术对提高LNA线性度的有效性.     

AC Modeling of the ggNMOS ESD Protection Device

From AC analysis results utilizing a 2‐dimensional device simulator, we extracted an AC‐equivalent circuit of a grounded‐gate NMOS (ggNMOS) electrostatic discharge (ESD) protection device. The extracted equivalent circuit is utilized to analyze the effects of the parasitics in a ggNMOS protection device on the characteristics of a low noise amplifier (LNA). We have shown that the effects of the parasitics can appear exaggerated for an impedance matching aspect and that the noise contribution of the parasitic resistances cannot be counted if the ggNMOS protection device is modeled by a single capacitor, as in prior publications. We have confirmed that the major changes in the characteristics of an LNA when connecting an NMOS protection device at the input are reduction of the power gain and degradation of the noise performance. We have also shown that the performance degradation worsens as the substrate resistance is reduced, which could not be detected if a single capacitor model is used.