碳化硅材料在微电子机械系统中的应用

碳化硅材料包括单晶碳化硅、多晶碳化硅、无定形碳化硅等,由于其显著的材料特性,如耐热、耐磨、化学惰性和高硬度等,近年来在微电子机械系统(MEMS)领域受到越来越多的关注。应用特定的工艺条件将碳化硅材料制成MEMS器件,可以在某些特殊条件下使用,克服了常规材料本身的局限性,从而为碳化硅材料的应用开发了新的领域。追踪这一国际热点研究问题,针对以上几种不同形态材料,分别举例说明了它们在MEMS领域应用的进展情况。     

基于谐振原理的RF MEMS滤波器的研制

采用与IC工艺兼容的硅表面MEMS加工技术,以碳化硅材料作为结构材料,研制出一种新型的基于谐振原理工作的RF MEMS滤波器。详细介绍了器件的工作原理、制备方法、测试技术和结果,并对测试结果做出分析。该RF MEMS滤波器由弹性耦合梁连接两个结构尺寸和谐振频率完全相同的MEMS双端固支梁谐振器构成,MEMS谐振器的结构决定了滤波器的中心频率,弹性耦合梁的刚度决定了滤波器的带宽。在大气环境下测试器件的频响特性,得到中心工作频率为41.5MHz,带宽为3.5MHz,品质因数Q为11.8。     

无坑洞n-3C-SiC/p-Si(100)的LPCVD外延生长及其异质结构特性

在MBE/CVD高真空系统上,利用低压化学气相淀积(LPCVD)方法在直径为50mm的单晶Si(100)衬底上生长出了高取向无坑洞的晶态立方相碳化硅(3C-SiC)外延材料,利用反射高能电子衍射(RHEED)和扫描电镜(SEM)技术详细研究了Si衬底的碳化过程和碳化层的表面形貌,获得了制备无坑洞3C-SiC/Si的优化碳化条件,采用霍尔(Hall)测试等技术研究了外延材料的电学特性,研究了n-3C-SiC/p-Si异质结的I-V、C-V特性及I-V特性对温度的依赖关系.室温下n-3C-SiC/p-Si异质结二极管的最大反向击穿电压达到220V,该n-3C-SiC/p-Si异质结构可用于制备宽带隙发射极SiC/Si HBTs器件.     

硅MEMS器件加工技术及展望

介绍了几种典型的硅基MEMS加工技术以及应用,并简单展望了MEMS加工技术发展趋势。硅基MEMS加工技术主要包括体硅MEMS加工技术和表面MEMS加工技术。体硅MEMS加工技术的主要特点是对硅衬底材料的深刻蚀,可得到较大纵向尺寸可动微结构,体硅工艺包括湿法SOG(玻璃上硅)工艺、干法SOG工艺、正面体硅工艺、SOI(绝缘体上硅)工艺。表面MEMS加工技术主要通过在硅片上生长氧化硅、氮化硅、多晶硅等多层薄膜来完成MEMS器件的制作,利用表面工艺得到的可动微结构的纵向尺寸较小,但与IC工艺的兼容性更好,易与电路实现单片集成。阐述了这些MEMS加工技术的工艺原理、优缺点、加工精度、应用等。提出了MEMS加工技术的发展趋势,包括MEMS器件圆片级封装(WLP)技术、MEMS工艺标准化、MEMS与CMOS单片平面集成、MEMS器件与其他芯片的3D封装集成技术等。     

SiCGe/3C-SiC异质结光控达林顿晶体管的设计与仿真

针对抗电磁干扰的需要提出了一种由SiCGe/3C-SiC异质结构成的光控达林顿晶体管设计.用多维器件模拟软件ISE对这种新型功率开关进行了特性仿真.结果表明,与采用其他结晶类型的碳化硅衬底相比,SiCGe与3C-SiC间较小的晶格失配有利于提高器件性能,可使其最大共射极电流增益达到890,获得最好的光触发特性和较好的Ⅰ-Ⅴ特性,饱和压降大约为4V.     

Design and Simulation of a Light-Activated Darlington Transistor Based on a SiCGe/3C-SiC Hetero-Structure

针对抗电磁干扰的需要提出了一种由SiCGe/3C-SiC异质结构成的光控达林顿晶体管设计.用多维器件模拟软件ISE对这种新型功率开关进行了特性仿真.结果表明,与采用其他结晶类型的碳化硅衬底相比,SiCGe与3C-SiC间较小的晶格失配有利于提高器件性能,可使其最大共射极电流增益达到890,获得最好的光触发特性和较好的Ⅰ-Ⅴ特性,饱和压降大约为4V.     

多晶SiC梳齿驱动器的模态分析

碳化硅以其优异的电学、机械和化学性能成为极端条件下MEMS器件应用的首选材料。梳齿驱动器的固有频率是MEMS器件结构设计中的一个重要参数。采用有限元分析方法,对多晶SiC梳齿驱动器进行了模态分析,得到了前六个模态的固有频率,并与相同结构的硅基梳齿驱动器的固有频率进行了比较,计算结果与理论预言十分吻合。     

3C-SiC悬臂结构干法刻蚀研究

基于感应离子耦合等离子体(ICP)刻蚀技术,采用SF6和O2作为刻蚀气体,以金属铝和SiO2作为刻蚀掩膜,系统地研究了3C-SiC悬臂结构的加工方法以及掩膜材料对刻蚀悬臂结构的影响。首先采用SF6和O2作为刻蚀气体刻蚀出SiC结构,其次采用SF6气体各向同性刻蚀Si衬底,释放已刻好的SiC悬臂梁结构。铝作为掩膜时,刻蚀最小结构尺寸为6μm,SiC表面几乎无损伤;SiO2作为掩膜时,刻蚀最小结构尺寸为4μm,但SiC表面损伤较大。上述研究结果为3C-SiC MEMS器件的制备提供了工艺基础。     

MEMS器件的封装材料与封装工艺

随着各种MEMS新产品的不断问世,先进的MEMS器件的封装技术正在研发之中.本研究综述了MEMS的封装材料,包括陶瓷、塑料、金属材料和金属基复合材料等.阐述了MEMS的主要封装工艺和技术,包括圆片级封装、单芯片封装、多芯片组件和3D堆叠式封装等.并展望了MEMS器件封装的应用和发展前景.     

低应力PECVD SiC晶圆级薄膜封装新技术

为了解决MEMS封装过程中易对微致动件造成损伤的问题,提出了一种低成本、与CMOS工艺兼容的晶圆级薄膜封装技术,用等离子体增强化学气相淀积(PECVD)法制备的低应力SiC作为封装和密封材料。此材料的杨氏模量为460 GPa,残余应力为65 MPa,可使MEMS器件悬浮时封装部位不变形。与GaAs,Si半导体材料相比,SiC具有较佳的物理稳定性,较高的杨氏模量等性能优势。将PECVD薄膜封装技术用于表面微结构和绝缘膜上Si(SOI)微结构部件(如射频开关、微加速度计等)封装中,不仅减小了封装尺寸,降低了芯片厚度,简化了封装工艺,而且封装芯片还与CMOS工艺兼容。较之晶圆键合封装方式,此晶圆级薄膜封装成本可降低5%左右。     

Temperature dependence of hot-carrier degradation in silicon-on-insulator dynamic threshold voltage MOS transistors

The authors analyze the influence of temperature on hot-carrier degradation of silicon-on-insulator (SOI) dynamic threshold voltage MOS (DTMOS) devices. Both low and high stress gate voltages are used. The temperature dependence of the hot-carrier effects in DTMOS devices is compared with those in SOI partially depleted (PD) MOSFETs. Possible physical mechanisms to explain the obtained results are suggested. This work shows that even if the stress gate voltage is low, the degradation of DTMOS devices stressed at high temperature could be significant.     

Switching times variation of MOSFET devices with temperature and high-field stress

Switching times of power MOSFET devices are investigated as function of temperature and high-field stress. Measurements show that important variations are obtained on the devices turn-on time. The threshold voltage is decreasing with temperature and varies with stress, especially at low temperatures. The oxide leakage current is found to be having safe values even at high temperatures, stressing the devices does not increase the leakage current to unsafe values except for very high temperatures.     

Investigation of Time–Dependent Resistive Switching Behaviors of Unipolar Nonvolatile Organic Memory Devices

Organic resistive memory devices are one of the promising next‐generation data storage technologies which can potentially enable low‐cost printable and flexible memory devices. Despite a substantial development of the field, the mechanism of the resistive switching phenomenon in organic resistive memory devices has not been clearly understood. Here, the time–dependent current behavior of unipolar organic resistive memory devices under a constant voltage stress to investigate the turn‐on process is studied. The turn‐on process is discovered to occur probabilistically through a series of abrupt increases in the current, each of which can be associated with new conducting paths formation. The measured turn‐on time values can be collectively described with the Weibull distribution which reveals the properties of the percolated conducting paths. Both the shape of the network and the current path formation rate are significantly affected by the stress voltage. A general probabilistic nature of the percolated conducting path formation during the turn‐on process is demonstrated among unipolar memory devices made of various materials. The results of this study are also highly relevant for practical operations of the resistive memory devices since the guidelines for time‐widths and magnitudes of voltage pulses required for writing and reading operation can be potentially set.     

一种用于MEMS超低值封装残余应力的测量方法

微机电系统(MEMS)封装残余应力是在封装工艺过程中芯片上产生的残余应力,它对于MEMS器件的热稳定性和长期贮存稳定性有着十分重大的影响,故而对MEMS封装残余应力的高精确度测量有利于封装应力的研究。由于封装残余应力十分微小,因此无法利用目前的测量手段直接测量封装应力,本文针对这个问题提出了一种基于应力放大结构和拉曼光谱法的封装应力测量方法,可以测量出MEMS器件中封装应力的平均水平。基于理论分析建立了原始封装模型与应力放大结构之间的放大关系,并提出应力放大结构的设计原则。接着采用3D有限元(FEM)仿真对一款高精确度MEMS微加速度计的封装应力测量进行了分析,其结果与理论分析具有很高吻合度。最后,针对该微加速度计的封装应力测量,成功制作了应力放大结构的芯片样片,并进行封装,随后拉曼光谱法被用于测量样片中的最大应力,进而计算出待测微加速度计中平均封装应力大小。实验结果与仿真分析具有很好的吻合度,证明本文所提出的测量方法具有相当的可靠性。     

ESD–RF co-design methodology for the state of the art RF-CMOS blocks

This paper describes an approach to design ESD protection for integrated low noise amplifier (LNA) circuits used in narrowband transceiver front-ends. The RF constraints on the implementation of ESD protection devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimise. The method is applied for the design of 0.25 μm CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional highly capacitive ggNMOS snapback devices. The methodology can be extended to other RF-CMOS circuits requiring ESD protection by merging the ESD devices in the functionality of the corresponding matching blocks.     

Performance and hot-carrier effects of small CRYO-CMOS devices

The performance characteristics of submicrometer CMOS devices operating at low/cryogenic temperatures (CRYO-CMOS) are determined. The advantages and problems in a CRYO-CMOS technology are experimentally studied in relation to the velocity saturation, source-drain resistances, mobility behavior, carrier freeze-out effects, hot-carrier effects, and circuit performance. The increase of the maximum transconductance at low temperatures (77, 4.2 K) has been confirmed even in the submicrometer channel region. However, improvement of inabilities at a VGnearly equal to 5 V is not so significant in devices with thinner oxides and less so in pMOS devices than in nMOS devices. Excellent subthreshold characteristics have been obtained at low temperatures, making very low-voltage operation possible. One problem found in the threshold control of pMOS transistors is that the boron ions implanted in the surface freeze out, causing unusual subthreshold behavior. Circuit delays have been improved by a factor of 2 to 3, and CRYO-CMOS shows the lowest power-delay product among existing semiconductor technologies with speed performance comparable to bipolar ECL devices. For LDD devices, speed improvements are only slightly smaller than for single-drain devices, while currents and transconductances in the linear regions are limited because of carrier freeze-out of the lightly doped drain. For both channel LDD devices, the transconductance degradations and VTshifts observed under dc stress conditions at 77 K are considered to result from electron injection into spacer oxides.     

The low frequency noise in HFETs estimates the effect of electrical stress

The effect of electrical stress on the low frequency noise in heterostructure field effect transistors is investigated in detail and is compared to the DC characteristics. Additionally, a model has been developed to describe the increase of the low frequency noise, depending on the change of other transistor parameters during the stress. Finally, a discussion about the model ability to be used for other devices is given.     

AC versus DC hot-carrier degradation in n-channel MOSFETs

The origins of the enhanced AC hot-carrier stress damage are examined. The enhancement in hot-carrier stress damage under AC stress conditions observed with respect to damage under DC stress conditions can fully be explained by the presence of three damage mechanisms occurring during both DC and AC operation: interface states created at low and mid-gate voltages, oxide electron traps created under conditions of hole injection into the oxide, and oxide electron traps created under conditions of hot-electron injection. It is shown that the quasi-static contributions of these mechanisms fully account for hot-carrier degradation under AC stress. The AC stress model is applied to devices from several different technologies and to several different AC stress waveforms. Excellent agreement is obtained in each case. The results demonstrate the validity of the model for frequencies up to 1 MHz. The absence of any transient effect indicates that the model could be applicable at much higher frequencies     

Reliability of the doping concentration in an ultra-thin body and buried oxide silicon on insulator (SOI) and comparison with a partially depleted SOI

This study compares the reliability of nMOSFETs with low- and high-doped ultra-thin body and buried oxide (UTBB) with fully depleted (FD) and partially depleted (PD) silicon on insulator (SOI). The high-doped devices display lower off-current leakage performance but more degradation in both hot-carrier stress (HCS) and positive bias temperature instability (PBTI) test at both room temperature and elevated temperature compared with the low-doped devices. The PBTI test indicates that the high-doped devices induce high tunneling leakage and that the degradation is highly associated with temperature. The degradation stabilizes with an increase in stress time. The thinner PD-SOI demonstrates low variation at the threshold voltage and low drive current under HCS. The FD-SOI has better drain leakage control than the PD-SOI.     

SAW quartz cuts with low stress and temperature sensitivity

The effects on Rayleigh wave velocity of strains and displacement gradients induced by isotropic in-plane stresses are modelled for a thin plate of quartz crystal. The stress sensitivity of SAW devices is calculated as a function of the quartz anisotropy. Comparison with loci of zero first-order temperature coefficients leads to the expectation of quartz cuts for SAW oscillator applications with low sensitivity to stress and temperature.