Mechanical properties and fracture analysis of glass substrate for PDPs

Abstract— A thermal shock test was carried out using high‐strain‐point glass substrates for plasma‐display panels. From the fracture analysis, the fracture stress was determined and compared with the initial edge strength. It was observed that the edge strength greatly decreased because of micro cracks that formed on the glass surface during testing. Therefore, it is important to prevent the formation of micro cracks in order to avoid failure as well as to minimize thermal stress in the process. Fatigue is also an important parameter in preventing the failure of the glass substrate when the stress on it lasts for a long period of time.     

Product design for strong cover glass

Strength is one of the most important properties of cover glass. In this study, fracture analysis is used to classify the breakage mode of cover glass into four typical modes. Moreover, the mechanism and evaluation method of each mode are investigated. Consequently, a chemical strengthening design with high compressive stress (CS) and low center tension (CT) is obtained. In addition, processing design is determined to be an important factor. Fining of edge processing and surface polishing after chemical strengthening are shown to enhance the edge and surface strength, respectively.     

High performance a‐IGZO thin‐film transistors with mf‐PVD SiO2 as an etch‐stop‐layer

In this work, we report on high‐performance bottom‐gate top‐contact (BGTC) amorphous‐Indium‐Gallium‐Zinc‐Oxide (a‐IGZO) thin‐film transistor (TFT) with SiO₂ as an etch‐stop‐layer (ESL) deposited by medium frequency physical vapor deposition (mf‐PVD). The TFTs show field‐effect mobility (μ_FE) of 16.0 cm²/(V.s), sub‐threshold slope (SS^?1) of 0.23 V/decade and off‐currents (I_OFF) < 1.0 pA. The TFTs with mf‐PVD SiO₂ ESL deposited at room temperature were compared with TFTs made with the conventional plasma‐enhanced chemical vapor deposition (PECVD) SiO₂ ESL deposited at 300 °C and at 200 °C. The TFTs with different ESLs showed a comparable performance regarding μ_FE, SS^?1, and I_OFF, however, significant differences were measured in gate bias‐stress stability when stressed under a gate field of +/?1 MV/cm for duration of 10⁴ s. The TFTs with mf‐PVD SiO₂ ESL showed lower threshold‐voltage (V_TH) shifts compared with TFTs with 300 °C PECVD SiO₂ ESL and TFTs with 200 °C PECVD SiO₂ ESL. We associate the improved bias‐stress stability of the mf‐PVD SiO₂ ESL TFTs to the low hydrogen content of the mf‐PVD SiO₂ layer, which has been verified by Rutherford‐Back‐Scattering‐Elastic‐Recoil‐Detection technique.     

A study of 3D cover glass design that improves handheld device drop reliability

Cover glass in commercial handheld devices is now evolving from flat (2D) to curved (3D) shapes. For example, some commercial devices have utilized sled‐shape cover glass, 1 which partially covers long edges of the device. According to the patents published by key handheld manufacturers, 2 , 3 we can expect more variety of 3D shaped cover glass for handheld devices in the market. In this study, we have focused on the reliability of 3D cover glass when it is dropped to a rigid surface. The key parameters under study are the corner/edge bend radius and angle of the cover glass, which determines the 3D shape of the cover glass. To achieve this goal, we developed a finite element model to simulate the drop 4 - 13 of a handheld device with 3D‐shaped glass. The model uses explicit algorithm to simulate the high speed impact on the device during the drop test. The glass performance was evaluated based on contact force between the glass and the ground and maximum principal stress in the glass. We showed that to avoid severe damage because of first impact between the glass and the ground, the bend angle of 3D glass has to be in the range between 0 and 45°. For drop angles of 45° and higher, with the proposed glass bend angle, the impact can be taken over by the edge of the back cover of the device. In addition, we showed that optimum glass bend radius is in the range of 3.8 mm and larger. This is required to reduce stress in glass because of impact. The approach and conclusions from the current study can serve as a general guideline to improve the 3D cover glass reliability of a handheld device.     

Organic light‐emitting diodes with enhanced out‐coupling efficiency using high‐refractive‐index glass frit

We have fabricated a novel type of substrate for organic light‐emitting diodes (OLEDs) to improve the light out‐coupling efficiency. It was fabricated by forming an excellent flat layer using a high‐refractive‐index B₂O₃‐SiO₂‐Bi₂O₃ frit glass on the light diffusive glass substrate. By using this substrate, we have sufficiently reduced the total internal reflection of OLEDs, and we successfully obtained more than 1.9 times higher light out‐coupling efficiency without spectral changes and viewing angle dependency. Furthermore, we have also successfully demonstrated 50 × 50 mm large‐area white OLEDs with this novel substrate.     

Silicon TFTs for flat panel displays

Liquid crystal displays work best when directly driven by an active matrix system. Such matrices can be made in different ways, but one of the most promising is the amorphous silicon thin film transistor (a-Si TFT) technology. Although an a-Si TFT technique seems quite suitable for LCD drives, polysilicon TFTs should be preferred for fast peripheral addressing circuits. Two basic TFT processes are proposed, using a-Si and SiO₂ films deposited on glass by the glow discharge technique. Silicon was deposited at 300°C in the first process and at 500°C in the second. Only in this latter case could silicon be easily recrystallized to give a polysilicon TFT on glass. This paper devotes most of its attention to the amorphous Si TFT. Static and dynamic characteristics are presented emphasizing the predominant role of traps, and a LC switching simulation is demonstrated. Finally a large area circuit is proposed and its problems discussed.     

Amorphous‐silicon thin‐film transistors made at 280°C on clear‐plastic substrates by interfacial stress engineering

Abstract— A process temperature of ～300°C produces amorphous‐silicon (a‐Si) thin‐film transistors (TFTs) with the best performance and long‐term stability. Clear organic polymers (plastics) are the most versatile substrate materials for flexible displays. However, clear plastics with a glass‐transition temperature (T_g) in excess of 300°C can have coefficients of thermal expansion (CTE) much larger than that of the silicon nitride (SiN^x) and a‐Si in TFTs deposited by plasma‐enhanced chemical vapor deposition (PECVD). The difference in the CTE that may lead to cracking of the device films can limit the process temperature to well below that of the T_g of the plastic. A model of the mechanical interaction of the TFT stack and the plastic substrate, which provides design guidelines for avoid cracking during TFT fabrication, is presented. The fracture point is determined by a critical interfacial stress. The model was used to successfully fabricate a‐Si TFTs on novel clear‐plastic substrates with a maximum process temperature of up to 280°C. The TFTs made at high temperatures have higher mobility, lower leakage current, and higher stability than TFTs made on conventional low‐T_g clear‐plastic substrates.     

Plasma damage‐free SiO2 deposition for low‐temperature poly‐Si AMLCDs

Abstract— High‐quality SiO₂ films have been fabricated at a substrate temperature of 300°C by utilizing a novel deposition method refered to as radical‐shower CVD (RS‐CVD), in which the substrates and material gases are completely separated from the plasma. On this account, SiO₂ deposition is achievable without plasma damage and excessive decomposition of the material gases. The electrical characteristics of RS‐CVD SiO₂ films are comparable to those of thermal SiO₂. Furthermore, the compact parallel‐plate structure of RS‐CVD is suitable for large‐area deposition.     

Nanocomposite sensitive polymeric films for SAW sensors deposited by the MAPLE direct write technique

A matrix-assisted pulsed laser evaporation direct write (MAPLE-DW) deposition technique was used to improve the properties of sensitive layers used in surface acoustic wave (SAW) sensors. In contrast with conventional deposition methods, MAPLE-DW allows the synthesis of uniform nanocomposite layers based on nanoparticles, in a special configuration that significantly reduces the energy loss by wave scattering. Ethanol, methanol, and toluene vapor were used as the target gases. The study compared sensors with polyethylenimine sensitive films and nanocomposite polymeric films based on SiO₂/Si nanoparticles (deposited by spray coating), and nanocomposite layers based on SiO₂ nanoparticles (deposited by MAPLE-DW). The sensors made from sensitive layers deposited by MAPLE-DW exhibited 3-5 times the sensitivity and 10-40 times the detection limit of the sensors deposited by spray coating.     

Recovery and immobilization of lead in cathode ray tube funnel glass by a combination of reductive and oxidative melting processes

Reductive melting treatment has been reported to be an effective method to recover lead from funnel glass in used cathode ray tubes, but a small amount of lead, a potential contaminant, remains in the treated glass. This paper applied a combination process of reductive and oxidative melting to the funnel glass to recover and immobilize lead in the glass. The funnel glass was melted in a lab‐scale reactor changing the atmosphere, and the effects of the temperature and the Na₂CO₃ dosage on the efficiencies of the lead recovery and immobilization were investigated. In the reductive melting, the lead recovery was promoted by increasing the Na₂CO₃ dosage, however the lead extraction from the glass into water and hydrochloric acid was increased. Although the content of lead in the glass after the reductive melting was low, the lead extraction into water and the acid was larger than 0.01 mg‐Pb/L‐water and 150 mg‐Pb/kg‐glass, respectively (Japanese environmental criteria). The lead extraction was decreased by the oxidative melting with SiO₂, Al₂O₃, MgO, and NaNO₃. In the proposed method, metallic lead was recovered from the funnel glass with high lead recovery, and the lead remaining in the glass was immobilized to meet the Japanese environmental criteria.     

Design and experiment of optical transparent microstrip antenna on glass and polycarbonate substrates

Microstrip antennas have the advantages of light weight, low profile, and conformal to the attached surface with antenna feed line. This work presents the design of transparent microstrip antennas by In₂O₃:Sn thin film on glass and polycarbonate substrates. The transparent conducting thin films of 21–300 nm thickness deposited by magnetron sputtering are measured by X‐ray diffraction for microstructure, 4‐point probe for electrical resistance, and spectrometer for optical transmittance. Analyses show that the 2.4 GHz antenna can achieve 5.1 and 4.7 dB antenna gain on glass (1.2 mm) and polycarbonate (0.7 mm) substrate, respectively. Experimental verification on glass substrate shows that the antenna achieves 3.1 dB gain and 86% optical transmittance on 550 nm wave length.     

White and tunable light emission of Ho3+ and Pr3+ ions co-doped phosphate glasses

The Ho³⁺ and Pr³⁺ ions co-doped phosphate glasses were prepared by melt quenching procedure with the various composition of (70-x-y)P₂O₅ + 20SiO₂ + 10CaO + xHo₂O₃ + yPr₂O₃ (x = 0.4, 0.6, 0.8, 1.0 mol%, y = 0.6, 0.8, 1.0 mol%). The structural investigation (based on X-ray diffraction analysis) confirmed amorphous character of these glass materials. The optical properties were studied. The glass samples have strong absorption at 360 nm, and the excitation light at 360 nm can excite Ho³⁺ and Pr³⁺ ions very well, causing them to produce synergistic luminescence. The glass sample 68.8P₂O₅ + 20SiO₂ + 10CaO + 0.4Ho₂O₃ + 0.8Pr₂O₃ emits strong white light under 360 nm excitation. The chromaticity coordinate values are x = 0.3378, y = 0.3472 in white light region, and it has a moderate correlated color temperature (CCT) of 5277 K. Decay time data reveals that there is energy transfer from Pr³⁺ to Ho³⁺ ions. This glass will be a good material for white light and tunable light emitting.     

Design and fabrication of PZT microcantilevers with freestanding structure

For developing freestanding piezoelectric microcantilevers with low resonant frequency, some critical mechanical considerations, especially cantilever bending, were given in this study. Two strategies, using piezoelectric thick films and adding a stress compensation layer, were calculationally analyzed for mitigating the cantilever bending, and then was applied for the fabrication of PZT freestanding microcantilevers. (100) oriented PZT thick films with the thickness of 6.93 μm were grown on the Pt/SiO₂/Si substrate by chemical solution deposition (CSD), and the SiO₂ layer with the thickness of 1.0 μm was kept under the PZT layer as a stress compensation layer of the freestanding microcantilevers. The freestanding microcantilevers fabricated with the micromachining process possessed the resonant frequency of 466.1 Hz, and demonstrated no obvious cantilever bending.     

Low‐temperature sputtered mixtures of high‐κ and high bandgap dielectrics for GIZO TFTs

Abstract— This paper discusses the properties of sputtered multicomponent amorphous dielectrics based on mixtures of high‐κ and high‐bandgap materials and their integration in oxide TFTs, with processing temperatures not exceeding 150°C. Even if Ta²O⁵ films are already amorphous, multicomponent materials such as Ta²O⁵—SiO² and Ta²O⁵—Al²O³ allow an increase in the bandgap and the smoothness of the films, reducing their leakage current and improving (in the case of Ta²O⁵—SiO²) the dielectric/semiconductor interface properties when these dielectrics are integrated in TFTs. For HfO²‐ based dielectrics, the advantages of multicomponent materials are even clearer: while HfO² films present a polycrystalline structure and a rough surface, HfO²—SiO² films exhibit an amorphous structure and a very smooth surface. The integration of the multicomponent dielectrics in GIZO TFTs allows remarkable performance, comparable with that of GIZO TFTs using SiO² deposited at 400°C by PECVD. For instance, with Ta²O⁵—SiO² as the dielectric layer, field‐effect mobility of 35 cm²/(V‐sec), close to 0 V turn‐on voltage, an on/off ratio higher than 10⁶, a subthreshold slope of 0.24 V/dec, and a small/recoverable threshold voltage shifts under constant current (I^D= 10 μA) stress during 24 hours are achieved. Initial results with multilayers of SiO²/HfO²—SiO²/SiO² are also shown, allowing a lower leakage current with lower thickness and excellent device performance.     

Effect of interfacial SiO2 thickness for low temperature O2 plasma activated wafer bonding

It was experimentally demonstrated that bonding strength strongly depends on the total SiO₂ thickness near the bonding interface for a given O₂ plasma surface activation. Systematic experiments of Si/SiO₂ and SiO₂/SiO₂ wafer bonding are performed for analyzing the evolution of the bonding surface energy with the interfacial oxide thickness. Optimum plasma exposure time increases with the interfacial SiO₂ thickness to achieve the maximum bonding strength in SiO₂/SiO₂ or SiO₂/Si. An optimal process option for plasma activated SiO₂/SiO₂ wafer bonding is proposed.     

Calculation of film stress from pitch measurements in LCD panel manufacturing

A method based on inverting a finite element model is presented for determining film stress from pitch changes before and after a film deposition step in liquid‐crystal display panel manufacturing. It differs from the conventional methods by making use of in‐plane deformation rather than out‐of‐plane measurements to calculate film stress. The resulting film stress is confounded with glass structural relaxation. Measurements of out‐of‐plane deformation at the edge of the sheet can be used with the pitch measurements to separate the effects of glass structural relaxation and film stress.     

Investigation of high extraction efficiency flip-chip GaN-based light-emitting diodes

In order to obtain higher light output power, the flip-chip structure is used. We studied the ratio of the light of GaN sides before and after fabricating metal reflector on p-GaN. The SiO₂/SiN _x dielectric film reflectors were deposited through plasma enhance chemical vapor deposition following the fabrication of metal reflector, and then the dielectric film reflectors on the electrodes were etched in order to expose the electrodes to the air. It is found that comparing with the flip-chip GaN-LED without dielectric film reflectors, light output power can be increased by as high as 10.2% after the deposition of 2 pairs of SiO₂/SiN _x dielectric film reflectors on GaN-LEDs, which cover the sidewalls and the areas without the metal reflector. This result indicates that the high reflector formed by multi-layer dielectric films is useful to enhance the light output power of GaN-based LED, which reflects light from step sidewalls and p-GaN without metal reflector to internal, and then light emits from the surface. Supported by the National Basic Research Program of China (Grant No. 2006CB604902), and the Funding Project for Academic Human Resources Development in Institutions of Higher Learning under the Jurisdiction of Beijing Municipality (Grant No. 05002015200504)     

Effect of buffered hydrofluoric acid etching on LCD glass substrates

Buffered hydrofluoric (BHF) acid was used in a TFT manufacturing process as a typical wet chemical agent. Hazing of an LCD glass substrate surface was sometimes observed after BHF chemical treatment during manufacturing. The haze consists of many micro‐sized hillocks on the substrate surface. This paper describes the formation and suppression mechanism of a typical LCD glass substrate made of Corning code 1737 glass. The hillocks were observed on an etched glass surface when NH₄F was added with HF as the buffered solution. Among the reaction products, ammonium‐based crystals were partially soluble in the etching solution. These ammonium‐based crystals were formed during BHF etching by masking an area of glass surface until the crystals were dissolved in the etching solution. In addition, hillocks composed of glass substrate material were detected on the masked area. The hillock density contour as the function of HF and NH₄F concentration was drawn for an etching rate of from about 0.03 to 0.13 μm/min. Hazing was effectively suppressed by dilution or agitation of BHF.     

Thermal stresses on membrane based microdevices

We developed a closed form analytical solution for thermal stresses on membrane based “released” MEMS devices. As all the layers forming the membrane has thicknesses close to one another, the assumption of having thick substrate fails. We employed stress superposition principles to obtain the intrinsic stresses caused by coefficient of thermal expansion (CTE) mismatch of the membrane layers. We also accounted for the membrane release. We illustrated that for a bilayer strip consisting of a thin film on a thick substrate, our formulation simplifies to the well-known Stoney equation. The results indicate that the thermal stress can be minimized by the appropriate choice of dielectric materials, metal electrode selections and deposition tools. Replacing the silicon nitride (Si₃N₄) layer deposited by low pressure chemical vapor deposition (LPCVD) with a silicon oxide (SiO₂) layer deposited by plasma enhanced chemical vapor deposition (PEVCD) reduces the average thermal stress by 93%.     

Low resistive silicon substrate as an etch-stop layer for drilling thick SiO2 by spark assisted chemical engraving (SACE)

Controlling precisely the depth in glass micro-drilling by spark assisted chemical engraving (SACE) remains challenging, particularly for low depths. The possibility of using an electrically conductive material as an etch-stop layer for SACE gravity-feed drilling is investigated in this paper. Micromachining with constant DC and pulsed DC of 30–35 μm thick SiO₂ deposited on low resistive silicon substrate demonstrated the etch-stop function of the conductive silicon. Measurements of etch rates and hole profiles along with scanning electron microscope imaging revealed the mechanism underlying the etch-stop process. Low resistive silicon is demonstrated to be a good etch-stop layer for SACE gravity-feed drilling. Demonstration of machining of SiO₂ layer on silicon as a substrate and an etch-stop layer opens up new possibilities to adapt SACE for developing devices on silicon platform.