Flexible AMOLEDs with low‐temperature‐processed TFT backplane technologies

Developments of backplane technologies, which are one of the challenging topics, toward the realization of flexible active matrix organic light‐emitting diodes (AMOLEDs) are discussed in this paper. Plastic substrates including polyimide are considered as a good candidate for substrates of flexible AMOLEDs. The fabrication process flows based on plastic substrates are explained. Limited by the temperature that plastic substrates can sustain, TFT technologies with maximum processing temperature below 400 °C must be developed. Considering the stringent requirements of AMOLEDs, both oxide thin‐film transistors (TFTs) and ultra‐low‐temperature poly‐silicon TFTs (U‐LTPS TFTs) are investigated. First, oxide TFTs with representative indium gallium zinc oxide channel layer are fabricated on polyimide substrates. The threshold voltage shifts under bias stress and under bending test are small. Thus, a 4.0‐in. flexible AMOLED is demonstrated with indium gallium zinc oxide TFTs, showing good panel performance and flexibility. Further, the oxide TFTs based on indium tin zinc oxide channel layer with high mobility and good stability are discussed. The mobility can be higher than 20 cm²/Vs, and threshold voltage shifts under both voltage stress and current stress are almost negligible, proving the potential of oxide TFT technology. On the other hand, the U‐LTPS TFTs are also developed. It is confirmed that dehydrogenation and dopant activation can be effectively performed at a temperature within 400 °C. The performance of U‐LTPS TFTs on polyimide is compatible to those of TFTs on glass. Also, the performance of devices on polyimide can be kept intact after devices de‐bonded from glass carrier. Finally, a 4.3‐in. flexible AMOLED is also demonstrated with U‐LTPS TFTs.     

Impact of bending on flexible metal oxide TFTs and oscillator circuits

Thin‐film circuits on plastic capable of high‐frequency signal generation have important applications in large‐area, flexible hybrid systems, enabling efficient wireless transmission of power and information. We explore oscillator circuits using zinc‐oxide thin‐film transistors (ZnO TFTs) deposited by the conformal, layer‐by‐layer growth technique of plasma‐enhanced atomic layer deposition. TFTs on three substrates—glass, 50‐µm‐thick freestanding polyimide, and 3.5‐µm‐thick spin‐cast polyimide—are evaluated to identify the best candidate for high‐frequency flexible oscillators. We find that TFTs on ultrathin plastic can endure bending to smaller radii than TFTs on commercial 50‐µm‐thick freestanding polyimide, and their superior dimensional stability furthermore allows for smaller gate resistances and device capacitances. Oscillators on ultrathin plastic with minimized parasitics achieve oscillation frequencies as high as 17 MHz, well above the cutoff frequency f_T. Lastly, we observe a bending radius dependence of oscillation frequency for flexible TFT oscillators and examine how mitigating device parasitics benefits the oscillator frequency versus power consumption tradeoff.     

Flexible thin‐film transistors application of amorphous tin oxide‐based semiconductors

The structural, optical, and electrical properties of Si‐doped SnO₂ (STO) films were investigated in terms of their potential applications for flexible electronic devices. All STO films were amorphous with an optical transmittance of ~90%. The optical band gap was widened as the Si content increased. The Hall mobility and carrier density were improved in the SnO₂ with 1 wt% Si film, which was attributed to the formation of donor states. Si (1 wt%) doped SnO₂ thin‐film transistor exhibited a good device performance and good stability with a saturation mobility of 6.38 cm²/Vs, a large I_on/I_off of 1.44 × 10⁷, and a SS value of 0.77 V/decade. The device mobility of a‐STO TFTs at different bending radius maintained still at a high level. These results suggest that a‐STO thin films are promising for fabricating flexible TFTs.     

Effects of gate‐bias stress on ZnO thin‐film transistors

Abstract— The effects of gate‐bias and thermal stress on the stability issues of zinc oxide thin film transistors (ZnO TFTs) deposited on glass substrates were investigated. The shift in threshold voltage for devices undergoing various post‐growth annealing conditions using a stretched‐exponential formalism was analyzed. The analysis indicated that the extracted parameters such as the time constant and the effective energy barrier (E^τ) can be correlated to the device trap states associated with the annealing conditions. Improvement in the channel conductance and interface quality, hence the resultant device stability, can therefore be resumed when subject to a thermal treatment at 400°C for 30 minutes compared with those annealed for a shorter time.     

Solution‐processed and low‐temperature metal oxide n‐channel thin‐film transistors and low‐voltage complementary circuitry on large‐area flexible polyimide foil

High‐performance solution‐based n‐type metal oxide thin‐film transistors (TFTs), fabricated directly on polyimide foil at a post‐annealing temperature of only 250 °C, are realized and reported. Saturation mobilities exceeding 2 cm²/(Vs) and on‐to‐off current ratios up to 10⁸ are achieved. The usage of these oxide n‐type TFTs as the pixel drive and select transistors in future flexible active‐matrix organic light‐emitting diode (AMOLED) displays is proposed. With these oxide n‐type TFTs, fast and low‐voltage n‐type only flexible circuitry is demonstrated. Furthermore, a complete 8‐bit radio‐frequency identification transponder chip on foil has been fabricated and measured, to prove that these oxide n‐type TFTs have reached already a high level of yield and reliability. The integration of the same solution‐based oxide n‐type TFTs with organic p‐type TFTs into hybrid complementary circuitry on polyimide foil is demonstrated. A comparison between both the n‐type only and complementary elementary circuitry shows the high potential of this hybrid complementary technology for future line‐drive circuitry embedded at the borders of flexible AMOLED displays.     

Flexible AMOLED displays on stainless‐steel foil

Abstract— The world's thinnest flexible full‐color 5.6‐in. active‐matrix organic‐light‐emitting‐diode (AMOLED) display with a top‐emission mode on stainless‐steel foil was demonstrated. The stress in the stainless‐steel foil during the thermal process was investigated to minimize substrate bending. The p‐channel poly‐Si TFTs on stainless‐steel foil exhibited a field‐effectmobility of 71.2 cm²/N‐sec, threshold voltage of ?2.7 V, off current of 6.7 × 10¹³ A/μm, and a subthreshold slope of 0.63 V/dec. These TFT performances made it possible to integrate a scan driver circuit on the panel. A top‐emission EL structure was used as the display element, and thin‐film encapsulation was performed to realize a thin and flexible display. The full‐color flexible AMOLED display on stainless‐steel foil is promising for mobile applications because of its thin, light, rugged, and flexible properties.     

Temporary bond—debond technology for high‐performance transistors on flexible substrates

Abstract— A processing technology based upon a temporary bond—debond approach has been developed that enables direct fabrication of high‐performance electronic devices on flexible substrates. This technique facilitates processing of flexible plastic and metal‐foil substrates through automated standard semiconductor and flat‐panel tool sets without tool modification. The key to processing with these tool sets is rigidifying the flexible substrates through temporary bonding to carriers that can be handled in a similar manner as silicon wafers or glass substrates in conventional electronics manufacturing. To demonstrate the power of this processing technology, amorphous‐silicon thin‐film‐transistor (a‐Si:H TFT) backplanes designed for electrophoretic displays (EPDs) were fabricated using a low‐temperature process (180°C) on bonded‐plastic and metal‐foil substrates. The electrical characteristics of the TFTs fabricated on flexible substrates are found to be consistent with those processed with identical conditions on rigid silicon wafers. These TFTs on plastic exhibit a field‐effect mobility of 0.77 cm²/V‐sec, on/off current ratio >10⁹ at Vds = 10 V, sub‐threshold swing of 365 mV/dec, threshold voltage of 0.49 V, and leakage current lower than 2 pA/μm gate width. After full TFT‐array fabrication on the bonded substrate and subsequent debonding, the flexible substrate retains its original flexibility; this enables bending of the EPD display without loss in performance.     

Two‐stage degradation in n‐channel LTPS‐TFTs under negative and positive bias stresses

Device degradation behaviors of n‐channel low‐temperature polycrystalline silicon thin film transistors under negative bias stress and positive bias stress were investigated. It was found that the threshold‐voltage has a two‐stage degradation, shifting to different direction with time. The mobility and the subthreshold swing SS both show a dependence on the stress time. It was determined that the interface trap states, the grain boundary trap states, and electron trapping together dominate the time‐dependent degradation behaviors. The trap is caused by the rupture of Si─H and Si─O bonds. A comprehensive model is proposed to explain the time‐dependent degradation behaviors clearly. In addition, after removing the stress, the recovery behaviors of threshold voltage V_th can be observed, which provide the evidence supporting the degradation model proposed.     

Circuits using uniform TFTs based on amorphous In‐Ga‐Zn‐O

Abstract— High‐performance and excellent‐uniformity thin‐film transistors (TFTs) having bottom‐gate structures are fabricated using an amorphous indium‐gallium‐zinc‐oxide (IGZO) film and an amorphous‐silicon dioxide film as the channel layer and the gate insulator layer, respectively. All of the 94 TFTs fabricated with an area 1 cm² show almost identical transfer characteristics: the average saturation mobility is 14.6 cm²/(V‐sec) with a small standard deviation of 0.11 cm²/(V‐sec). A five‐stage ring‐oscillator composed of these TFTs operates at 410 kHz at an input voltage of 18 V. Pixel‐driving circuits based on these TFTs are also fabricated with organic light‐emitting diodes (OLED) which are monolithically integrated on the same substrate. It is demonstrated that light emission from the OLED cells can be switched and modulated by a 120‐Hz ac signal input. Amorphous‐IGZO‐based TFTs are prominent candidates for building blocks of large‐area OLED‐display electronics.     

High‐performance vacuum‐processed metal oxide thin‐film transistors: A review of recent developments

Since 2010, vacuum‐processed oxide semiconductors have greatly improved with the publication of more than 1,300 related papers. Although the number of researches on oxide semiconductors has continued to increase year by year, the average field‐effect mobility of oxide semiconductor thin‐film transistors (TFTs) has not shown significant improvement; from 2010 to 2018; the average field‐effect mobility of vacuum‐processed n‐type oxide TFTs is around 20 cm²/Vs. To investigate the obstacles for performance improvements, the latest progress and researches on vacuum‐processed oxide semiconductor TFTs for high performance over the past decade are highlighted, along with the pros and cons of each technology. Finally, complementary metal oxide semiconductor (CMOS) logic circuits composed of both n‐ and p‐type oxide semiconductor TFTs are introduced, and future prospects for this state‐of‐the‐art research on the oxide semiconductors are presented.     

Amorphous‐silicon thin‐film transistors made at 280°C on clear‐plastic substrates by interfacial stress engineering

Abstract— A process temperature of ～300°C produces amorphous‐silicon (a‐Si) thin‐film transistors (TFTs) with the best performance and long‐term stability. Clear organic polymers (plastics) are the most versatile substrate materials for flexible displays. However, clear plastics with a glass‐transition temperature (T_g) in excess of 300°C can have coefficients of thermal expansion (CTE) much larger than that of the silicon nitride (SiN^x) and a‐Si in TFTs deposited by plasma‐enhanced chemical vapor deposition (PECVD). The difference in the CTE that may lead to cracking of the device films can limit the process temperature to well below that of the T_g of the plastic. A model of the mechanical interaction of the TFT stack and the plastic substrate, which provides design guidelines for avoid cracking during TFT fabrication, is presented. The fracture point is determined by a critical interfacial stress. The model was used to successfully fabricate a‐Si TFTs on novel clear‐plastic substrates with a maximum process temperature of up to 280°C. The TFTs made at high temperatures have higher mobility, lower leakage current, and higher stability than TFTs made on conventional low‐T_g clear‐plastic substrates.     

Lightweight electrowetting display on ultra‐thin glass substrate

Mobile display devices that use ultra‐thin (≤100 µm) glass substrates offer a combination of attractive characteristics: lightweight, high quality device fabrication process, thermal and dimensional stability, and mechanical flexibility. Electrowetting (EW) devices fabricated on ultra‐thin glass are demonstrated in this paper. Water contact angle, which is the most critical parameter of EW devices, changes from ~165° to 80° when a 20 V direct current (or alternating current) voltage is applied. EW devices on ultra‐thin glass show negligible hysteresis (~2°) and fast switching time of ~10 ms. EW device operation is maintained when the glass substrate is mechanically flexed. These results indicate the promise of narrow profile EW devices on ultra‐thin glass substrate for mobile and other devices, including video rate flexible electronic paper.     

Uniformity and bias‐temperature instability of bottom‐gate zinc oxide thin‐film transistors (ZnO TFTs)

Abstract— Short‐range uniformity and bias‐temperature (BT) instability of ZnO TFTs with SiO^x/SiN^x stacked gate insulators which have different surface treatments have been investigated. The short‐range uniformity of ZnO TFTs was drastically improved by N²O plasma treatment of the gate insulator. The variation in the gate voltage where a drain current of 1‐nA flows (Vgs at an Ids of 1 nA) was dramatically reduced from ±1.73 V to ±0.07 V by N²O plasma treatment of the gate insulator. It was clarified that the variations in the subthreshold characteristics of the ZnO TFTs could be reduced by N²O plasma treatment of the gate insulator due to a decrease in the variation of trap densities in deep energy levels from 0.9–2.0 × 10¹⁷ to 1.2–1.3×10¹⁷ cm^?3‐eV^?1. From the BT stress tests, a positive shift of Vgs at an Ids of 1 nA could be reduced by N²O plasma treatment of the gate insulator due to a decrease in the charge traps in the gate insulator. When the gate‐bias stress increases, state creation occured in the ZnO TFTs in addition to the charge trapping in the gate insulator. However, N²O plasma treatment of the gate insulator has little effect on the suppression of the state creation in ZnO TFTs under BT stress. The surface treatment of the gate insulator strongly affects the short‐range uniformity and the BT instability of Vth in the ZnO TFTs.     

Influence of channel‐deposition conditions and gate insulators on performance and stability of top‐gate IGZO transparent thin‐film transistors

Abstract— Amorphous‐oxide‐semiconductor thin‐film transistors (TFTs) have gained wide attention in recent years due to their many merits. In this paper, a series of top‐gate transparent thin‐film transistors (TFTs) based on amorphous‐indium—gallium—zinc—oxide (a‐IGZO) semiconductors have been fabricated and investigated. Specifically, low‐temperature SiNx and SiOx were used as the gate insulator and different Ar/O² gas‐flow ratios were used for a‐IGZO channel deposition to study the influences of gate insulators and channel‐deposition conditions. In addition to the investigation of device performance, the stability of these TFTs was also examined by applying constant‐current stressing. It was found that a high mobility of 30‐45 cm²/V‐sec and small threshold‐voltage shift in constant‐current stressing can be achieved using SiNx with suitable hydrogen‐content stoichiometry as the gate insulator and the carefully adjusted Ar/O² flow ratio for channel deposition. These results may be associated with hydrogen incorporation into the channel, the lower defect trap density, and the better water/oxygen barrier properties (impermeability) of the low‐temperature SiNx.     

Single‐source dual‐layer amorphous IGZO thin‐film transistors for display and circuit applications

In this study, the authors report on high‐quality amorphous indium–gallium–zinc oxide thin‐film transistors (TFTs) based on a single‐source dual‐layer concept processed at temperatures down to 150°C. The dual‐layer concept allows the precise control of local charge carrier densities by varying the O₂/Ar gas ratio during sputtering for the bottom and top layers. Therefore, extensive annealing steps after the deposition can be avoided. In addition, the dual‐layer concept is more robust against variation of the oxygen flow in the deposition chamber. The charge carrier density in the TFT channel is namely adjusted by varying the thickness of the two layers whereby the oxygen concentration during deposition is switched only between no oxygen for the bottom layer and very high concentration for the top layer. The dual‐layer TFTs are more stable under bias conditions in comparison with single‐layer TFTs processed at low temperatures. Finally, the applicability of this dual‐layer concept in logic circuitry such as 19‐stage ring oscillators and a TFT backplane on polyethylene naphthalate foil containing a quarter video graphics array active‐matrix organic light‐emitting diode display demonstrator is proven.     

Characteristics of a‐IZO TFTs with high‐κ HfSiOx gate insulator annealed in various conditions

In this work, we investigate the enhanced performance of amorphous indium zinc oxides‐based thin film transistors with hafnium silicate (HfSiO_x) gate insulators. HfSiO_x gate insulators annealed at various conditions are deposited by cosputtering of hafnium oxide and Si. The structural properties of HfSiO_x are investigated using the atomic force microscopy, X‐ray diffraction, and x‐ray photoelectron spectroscopy (XPS). techniques. Furthermore, the electrical characteristics of HfSiO_x are analyzed to investigate the effect of annealing conditions. We obtain optimal results for thin film transistors with HfSiO_x gate insulators annealed for 1 h at 100 °C, with a saturation mobility of 1.2 cm²/V · s, threshold voltage of 2.2 V, on current/off current ratio of 2.0 × 10⁶, and an insulator surface roughness of 0.187 nm root mean square.     

Development of flexible displays using back‐channel‐etched In–Sn–Zn–O thin‐film transistors and air‐stable inverted organic light‐emitting diodes

We developed flexible displays using back‐channel‐etched In–Sn–Zn–O (ITZO) thin‐film transistors (TFTs) and air‐stable inverted organic light‐emitting diodes (iOLEDs). The TFTs fabricated on a polyimide film exhibited high mobility (32.9 cm²/Vs) and stability by utilization of a solution‐processed organic passivation layer. ITZO was also used as an electron injection layer (EIL) in the iOLEDs instead of conventional air‐sensitive materials. The iOLED with ITZO as an EIL exhibited higher efficiency and a lower driving voltage than that of conventional iOLEDs. Our approach of the simultaneous formation of ITZO film as both of a channel layer in TFTs and of an EIL in iOLEDs offers simple fabrication process.     

High‐temperature thin‐film barriers for foldable AMOLED displays

We present a thin‐film dual‐layer bottom barrier on polyimide that is compatible with 350°C backplane processing for organic light‐emitting diode displays and that can facilitate foldable active‐matrix organic light‐emitting diode devices with a bending radius of <2 mm. We demonstrate organic light‐emitting diodes that survive bending over 0.5 mm radius for 10.000× based on the high‐temperature bottom barrier. Furthermore, we show compatibility of the bottom barrier with the backplane process by fabricating active‐matrix organic light‐emitting diode displays on GEN1‐sized substrates.     

Low‐temperature amorphous‐silicon backplane technology development for flexible displays in a manufacturing pilot‐line environment

Abstract— A low‐temperature amorphous‐silicon (a‐Si:H) thin‐film‐transistor (TFT) backplane technology for high‐information‐content flexible displays has been developed. Backplanes were integrated with frontplane technologies to produce high‐performance active‐matrix reflective electrophoretic ink, reflective cholesteric liquid crystal and emissive OLED flexible‐display technology demonstrators (TDs). Backplanes up to 4 in. on the diagonal have been fabricated on a 6‐in. wafer‐scale pilot line. The critical steps in the evolution of backplane technology, from qualification of baseline low‐temperature (180°C) a‐Si:H process on the 6‐in. line with rigid substrates, to transferring the process to flexible plastic and flexible stainless‐steel substrates, to form factor scale‐up of the TFT arrays, and finally manufacturing scale‐up to a Gen 2 (370 × 470 mm) display‐scale pilot line, will be reviewed.     

Letter: A new compensation pixel circuit with metal oxide thin‐film transistors for active‐matrix organic light‐emitting diode displays

This paper presents a novel compensation pixel circuit for active‐matrix organic light‐emitting diode displays, in which the coupling effect mask technology is developed to compensate the threshold voltage of driving thin‐film transistor whether it is positive or negative. Twenty discrete compensation pixel circuits have been fabricated by In‐Zn‐O thin‐film transistors process. It is measured that the non‐uniformity of the proposed pixel circuit is significantly reduced with an average value of 8.6%. Furthermore, the organic light‐emitting diode emission current remains constant during 6 h continuous operation, which also confirms the validity of the proposed pixel circuit.