Flexible thin‐film transistors application of amorphous tin oxide‐based semiconductors

The structural, optical, and electrical properties of Si‐doped SnO₂ (STO) films were investigated in terms of their potential applications for flexible electronic devices. All STO films were amorphous with an optical transmittance of ~90%. The optical band gap was widened as the Si content increased. The Hall mobility and carrier density were improved in the SnO₂ with 1 wt% Si film, which was attributed to the formation of donor states. Si (1 wt%) doped SnO₂ thin‐film transistor exhibited a good device performance and good stability with a saturation mobility of 6.38 cm²/Vs, a large I_on/I_off of 1.44 × 10⁷, and a SS value of 0.77 V/decade. The device mobility of a‐STO TFTs at different bending radius maintained still at a high level. These results suggest that a‐STO thin films are promising for fabricating flexible TFTs.     

Amorphous‐silicon thin‐film transistor on soda‐lime glass

Abstract— Amorphous‐silicon (a‐Si:H) thin‐film transistors (TFTs) on soda‐lime glass were fabricated by using a diffusion barrier and a low‐temperature process at 200°C. The silicon nitride barrier was optimized in terms of diffusion blocking effectiveness, film adhesion, and surface finish. TFTs on soda‐lime glass achieved a saturation mobility 0.47 cm²/V‐sec, threshold voltage of 0 V, an off‐current of 7.7×10^?11 A, and a sub‐threshold swing of 1.0 V/dec. From diffusion experiments, a 30,000‐hour lifetime for the TFT device at 80°C was estimated, and the robustness of the silicon nitride barrier against long‐term migration of sodium was demonstrated.     

Effect on electrical performance of titanium co‐sputtered IZO active‐channel thin‐film transistor

We investigated the electrical performance of Ti–IZO active‐channel layer thin‐film transistors (TFTs) using a radio frequency (RF) magnetron co‐sputtering system to co‐sputter IZO and Ti targets. The samples were fabricated by changing the RF gun power of the IZO. The other parameters such as the RF gun power of the Ti target, oxygen partial pressure [O₂/(Ar + O₂)], and initial and process pressure of the chamber were unchanged. Unlike the sample sputtered only with IZO, the thin films of the Ti–IZO samples could control the oxygen vacancy because Ti reacts with the oxygen in the IZO. Therefore, Ti–IZO thin films can suppress the carrier concentration and thus have an effect on the electrical performance of TFTs.     

A course on thin‐film transistor circuit design for modern displays

A new subject‐specific course on thin‐film transistor (TFT) circuit design is introduced, covering related knowledge of display technologies, TFT device physics, processing, characterization, modeling and circuit design. A design project is required for students to deepen the understanding even more and get hands‐on design experience. This course can be an intense 1‐week course to offer a full training of design engineers in an organized way to meet the ever‐increasing needs in display industry for TFT circuit design specialists. It can also be organized in one semester for electrical engineering Master's and Ph.D. students.     

Process development of inverted‐staggered amorphous InGaZnO thin‐film transistors with wet‐etched electrodes

Process development of inverted‐staggered amorphous InGaZnO thin‐film transistors (a‐IGZO TFTs) with wet‐etched electrodes was employed in this paper. Five metals (Al, Cu, Ti, Ta, and Cr) as well as various etchants were comparatively investigated, indicating H₂O₂ based solution etched Ta films were good candidates for the wet‐etched electrodes of a‐IGZO TFTs. The aforementioned findings along with other improving attempts successfully established inexpensive processing steps and conditions with which stable a‐IGZO TFTs were finally fabricated. The device performance was reasonably good enough (μ_FE of 6.0 cm²/V·s, V_th of 2.5 V, SS of 1.8 V/decade, and I_on/I_off of 10⁶) to meet the requirements of applications especially for small‐sized flat panel displays.     

An electrostatic discharge model for thin‐film transistor fabrication

Electrostatic discharge (ESD) is a significant cause of yield loss in thin‐film transistor (TFT) array manufacturing. TFT arrays are at increased risk relative to other electronic components because the TFTs are unprotected; the array has a large inherent capacitance, and TFT processing includes many chucking and conveyance steps that result in triboelectric charge generation. To reduce or eliminate ESD‐caused fallout, an understanding must be gained of an ESD event's fundamental physics, including the mechanism of charge generation, ESD event physics, and TFT failure modes. An equivalent circuit model has been developed to address the physics of how ESD events occur. The ESD event scenarios modeled with this circuit are as follows: (1) the substrate glass is lifted from the chuck, resulting in a non‐uniform static charge; (2) this charge induces a voltage on the A‐side components; (3) the substrate is lifted, causing a voltage increases; (4) the uneven charge generated results in voltage gradients between TFTs, resulting in an ESD event. This model combines the effects of TFT substrate lifting and charge generation, with a simplified equivalent circuit representing the TFT array. The behavior of this circuit was simulated with a spice model (Electronics Research Laboratory of the University of California, Berkeley, CA, USA.) to characterize the ESD pulse.     

Memory effects of all‐solution‐processed oxide thin‐film transistors using ZnO nanoparticles

Abstract— Non‐volatile memory effects of an all‐solution‐processed oxide thin‐film transistor (TFT) with ZnO nanoparticles (NPs) as the charge‐trapping layer are reported. The device was fabricated by using a soluble MgInZnO active channel on a ZrHfO^x gate dielectric. ZnO NPs were used as the charge‐trapping site at the gate‐insulator—channel interface, and Al was used for source and drain electrodes. Transfer characteristics of the device showed a large clockwise hysteresis, which can be used to demonstrate its memory function due to electron trapping in the ZnO NP charge‐trapping layer. This memory effect has the potential to be utilized as a memory application on displays and disposable electronics.     

A framework for assessing amorphous oxide semiconductor thin‐film transistor passivation

Amorphous oxide semiconductor thin‐film transistors (TFTs) are moving towards commercialization for a variety of display applications. Invariably, display applications require a bottom‐gate TFT configuration in which passivation of the top channel layer surface is required. The objective of this work is to propose a conceptual model framework for assessing TFT passivation schemes, within the context of amorphous oxide semiconductor electronics. This model involves first estimating the energy of the charge neutrality levels (CNLs) for the channel and passivation layers. Then, an energy band diagram is drawn to establish the relative position of these CNLs prior to their establishment of intimate contact. A situation in which the passivation layer CNL is below that of the channel layer CNL is considered undesirable because interface state electronic transfer from the channel to the passivation layer leads to formation of an accumulation layer at this interface. Although the opposite case in which the passivation layer CNL is above that of the channel layer CNL is more desirable, the ideal situation would be when both CNLs align because no interface state electronic transfer would occur. This framework is then employed in a discussion of the passivation of indium gallium zinc oxide and zinc tin oxide bottom‐gate TFTs.     

Modeling of threshold‐voltage‐shift dependency on drain bias in amorphous‐silicon thin‐film transistors in active‐matrix organic light‐emitting‐diode displays

Abstract— A theoretical model to interpret appearances of the threshold voltage shift in hydrogenated amorphous‐silicon (a‐Si:H) thin‐film transistors (TFTs) is developed to better understand the instability of a‐Si:H TFTs for the driving transistors in active‐matrix organic light‐emitting‐diode (AMOLED) displays. This model assumes that the defect creation at channel in a‐Si:H is proportional to the carrier concentration, leading to the defect density varying along the channel depending on the bias conditions. The model interprets a threshold‐voltage‐shift dependency on the drain‐stress bias. The model predicts the threshold voltage shift stressed under a given gate bias applying the drain saturation voltage is 66% of that with zero drain bias, and it even goes down to 50–60% of that when stressed by applying twice the drain saturation voltage.     

Back‐channel‐etched thin‐film transistor using c‐axis‐aligned crystal In–Ga–Zn oxide

Our crystalline In–Ga–Zn oxide (IGZO) thin film has a c‐axis‐aligned crystal (CAAC) structure and maintains crystallinity even on an amorphous base layer. Although the crystal has c‐axis alignment, its a‐axis and b‐axis have random arrangement; moreover, a clear grain boundary is not observed. We fabricated a back‐channel‐etched thin‐film transistor (TFT) using the CAAC‐IGZO film. Using the CAAC‐IGZO film, more stable TFT characteristics, even with a short channel length, can be obtained, and the instability of the back channel, which is one of the biggest problems of IGZO TFTs, is solved. As a result, we improved the process of manufacturing back‐channel‐etched TFTs.     

Multioutputs single‐stage gate driver on array with wide temperature operable thin‐film‐transistor liquid‐crystal display for high resolution application

A hydrogenated amorphous silicon (a‐Si:H) thin‐film transistor (TFT) gate driver with multioutputs (eight outputs per stage) for high reliability, 10.7‐inch automotive display has been proposed. The driver circuit is composed of one SR controller, eight driving TFTs (one stage to eight outputs) with bridging TFTs. The SR controller, which starts up the driving TFTs, could also prevent the noise of gate line for nonworking period. The bridging TFT, using width decreasing which connects between the SR controller and the driving TFT, could produce the floating state which is beneficial to couple the gate voltage, improves the driving ability of output, and reaches consistent rising time in high temperature and low temperature environment. Moreover, 8‐phase clocks with 75% overlapping and dual‐side driving scheme are also used in the circuit design to ensure enough charging time and reduce the loading of each gate line. According to lifetime test results, the proposed gate driver of 720 stages pass the extreme temperature range test (90°C and ?40°C) for simulation, and operates stably over 800 hours at 90°C for measurement. Besides, this design is successfully demonstrated in a 10.7‐inch full HD (1080 × RGB×1920) TFT‐liquid‐crystal display (LCD) panel.     

Design of dual‐outputs‐single‐stage a‐Si:H TFT gate driver for high resolution TFT‐LCD application

A new gate driver has been designed and fabricated by amorphous silicon technology. With utilizing the concept of sharing the noise free block in a single stage for gate driver, dual‐outputs signals could be generated in sequence. By increasing the number of output circuit block in proposed gate driver, number of outputs per stage could also be adding that improves the efficiency for area reduction. Besides, using single driving thin‐film‐transistor (TFT) for charging and discharging, the area of circuit is also decreased by diminishing the size of pulling down TFT. Moreover, the proposed gate driver has been successfully demonstrated in a 5.5‐inch Full HD (1080xRGBx1920) TFT‐liquid‐crystal display panel and passed reliability tests of the supporting foundry.     

Comparative study on extraction methods of threshold voltage for thin‐film transistors

In this work, we proposed three methods on extracting threshold voltage of ploy‐silicon thin‐film transistors, such as, extrapolation of the linear region, transconductance linear extrapolation, and second derivation. Based on these different methods, one can extract various values of threshold voltages, as well as their temperature dependence. In room temperature, the second derivation method is the most appropriate for thin‐film transistors. More remarkably, the different methods show the different temperature dependence of mobility, corresponding to different charge transport mechanisms. That is, hopping dominates the transport mechanism for extrapolation of the linear region method, while it will occur to transform from band‐like to hopping mechanism for the second derivative method.     

Fluorinated indium‐gallium‐zinc oxide thin‐film transistor with reduced vulnerability to hydrogen‐induced degradation

Thin‐film transistors (TFTs) based on amorphous indium‐gallium‐zinc oxide channels with or without fluorination were fabricated. The sensitivity of their electrical characteristics to hydrogen exposure was compared. It is shown that TFTs built with fluorinated channels exhibit significantly improved intrinsic resistance against hydrogen‐induced degradation; hence, they are potentially better suited for integration with hydrogen‐containing devices such as photo‐diodes based on amorphous hydrogenated silicon and TFTs based on low‐temperature polycrystalline silicon. The observed improvement correlates well with a reduced population of oxygen‐related defects and reduced hydrogen incorporation in the fluorinated channels.     

Application of re‐crystallized metal‐induced unilaterally crystallized polycrystalline‐silicon thin‐film‐transistor technology to reflective liquid‐crystaldisplay

Single‐polarizer reflective twisted‐nematic (RTN) liquid‐crystal modes offer larger viewing angles, higher contrast ratios and lower power dissipation compared to regular double‐polarizer transmissive‐ reflective liquid‐crystal implementations. The application of re‐crystallized metal‐induced unilaterally crystallized polycrystalline‐silicon thin‐film‐transistor (TFT) technology to realize active matrices and peripheral circuit components for hand‐held direct‐view RTN‐mode video displays is reported.     

Novel top‐gate zinc oxide thin‐film transistors (ZnO TFTs) for AMLCDs

Abstract— High‐performance top‐gate thin‐film transistors (TFTs) with a transparent zinc oxide (ZnO) channel have been developed. ZnO thin films used as active channels were deposited by rf magnetron sputtering. The electrical properties and thermal stability of the ZnO films are controlled by the deposition conditions. A gate insulator made of silicon nitride (SiN_x) was deposited on the ZnO films by conventional P‐CVD. A novel ZnO‐TFT process based on photolithography is proposed for AMLCDs. AMLCDs having an aperture ratio and pixel density comparable to those of a‐Si:H TFT‐LCDs are driven by ZnO TFTs using the same driving scheme of conventional AMLCDs.     

Evaluation of photoresponse in solution-processable ZnO thin film transistor for radiative sensor applications

Thin film transistor based on the spin-cast ZnO channel layer was fabricated with SiO₂ dielectric layer on Si substrate. The ZnO active layer grown by sol-gel spin-cast caused an increase in the field-effect mobility compared to those of the ZnO TFTs with the channel layer grown by zinc acetate precursor. Under light illumination, the ZnO-TFT in turn-off state exhibited a high drain current, which is 12.82 times higher than dark drain current, whereas in turn-on state is 9.43 times. The photosensing behavior of thin film transistor based on the spin-cast ZnO channel layer indicated more pronounced under a depletion region of 0 V gate bias. The obtained results indicate that the ZnO layer spin coated on SiO₂ gate layer can be an effective and promising way to increase factor for improving the device performance and for light detecting of ZnO thin film transistor and the studied thin film phototransistor can be used in optoelectronic applications.     

Characteristics and stability of improved re‐crystallized metal‐induced laterally crystallized polycrystalline‐silicon thin‐film transistors for display applications

Abstract— The performance of high‐temperature re‐crystallized (RC) metal‐induced laterally crystallized (MILC) polycrystalline‐silicon (poly‐Si) thin‐film transistors (TFT) have been improved by (1) patterning the active islands before MILC, (2) removing nickel‐containing residues using acid cleaning, (3) using heavily boron‐doped poly‐Si gates to achieve threshold voltage symmetry, and (4) double‐implanting n‐type source/drain junctions. A 30‐MHz driver circuit based on this improved technology was demonstrated. The reliability of optimized RC‐MILC poly‐Si TFTs has not been adversely affected by residual nickel‐containing contaminants in the TFT channel regions.     

Active‐matrix organic light‐emitting displays employing two thin‐film‐transistor a‐Si:H pixels on flexible stainless‐steel foil

Abstract— An active‐matrix organic light‐emitting diode (AMOLED) display driven by hydrogenated amorphous‐silicon thin‐film transistors (a‐Si:H TFTs) on flexible, stainless‐steel foil was demonstrated. The 2‐TFT voltage‐programmed pixel circuits were fabricated using a standard a‐Si:H process at maximum temperature of 280°C in a bottom‐gate staggered source‐drain geometry. The 70‐ppi monochrome display consists of (48 × 4) × 48 subpixels of 92 ×369 μm each, with an aperture ratio of 48%. The a‐Si:H TFT pixel circuits drive top‐emitting green electrophosphorescent OLEDs to a peak luminance of 2000 cd/m².     

Transfer‐curve assessment of oxide thin‐film transistors

Abstract— Oxide electronics is an emerging area that is well positioned to strongly and positively impact next‐generation display technology. A metal‐oxide thin‐film transistor (TFT) is the fundamental component of oxide electronics. Unfortunately, some of the claims made in the literature about the performance of oxide TFTs are, in this author's opinion, unreliable. This is true of turn‐on voltage, subthreshold swing, and, especially, channel mobility. Measurement artifacts can lead to unreliable performance estimates. The goal of this contribution is to enumerate some of these artifacts and to outline a general testing procedure for avoiding common oxide‐TFT assessment pitfalls.