开管退火对碲锌镉单晶片沉积相影响的研究

报道了一种CZT单晶片退火的新装置和新工艺,可以方便有效的对CZT单晶片进行开管退火.主要研究了氢气氛下加Cd源开管退火对CZT晶片中沉积相的影响.研究发现:经过开管退火处理后CZT晶片中的沉积相颗粒的密度和尺寸都明显减小,有效消除了Te沉积相,大颗粒的Cd沉积相尺寸也明显减小.     

Cd气氛退火对CdZnTe晶片质量影响

在CdZnTe晶体生长时,有时会产生大颗粒的沉积相,严重的影响了CdZnTe晶片的质量,通过电子探针测试证明其为Cd沉积相。采用Cd气氛退火来消除Cd沉积相,可以改善CdZnTe晶片的质量。实验发现：在较高的温度（600℃）条件下,退火可以有效的消除大颗粒（〉5μm）的Cd沉积相,改善CdZnTe晶片红外透过率、X射线双晶回摆曲线半峰宽（FWHM）和腐蚀坑密度（EPD）。在此条件下对CdZnTe晶片进行退火,有助于提高CdZnTe晶片的性能。     

CdZnTe衬底沉积相成分分析

采用扫描电子显微镜技术对Cd Zn Te单晶片中的沉积相进行成分分析研究,结果表明通过红外显微系统观察到的Cd Zn Te晶片中常见的"放射状"沉积相和"链状"沉积相Cd含量富集,确认为Cd沉积相;另外,扫描电镜能谱仪对沉积相颗粒分析表明,Cd Zn Te晶体中的杂质元素易在Cd沉积相中富集。     

富铟熔体生长InP单晶的晶体缺陷及物理特性

通过磷注入法合成并利用液封直拉法(LEC)生长了富铟InP单晶,将晶锭进行定向切割、研磨和抛光,得到InP抛光片.用金相显微镜、扫描电镜、快速扫描光荧光谱(PL-Mapping)技术、高分辨率XRD射线衍射技术研究了富铟非掺InP单晶样品特性.结果表明,在富铟条件下生长的InP单晶会出现富铟夹杂,这种富铟夹杂可导致其周围位错密度升高,同时富铟夹杂在晶片内分布也是不均匀的,在晶片中心部分富铟夹杂的密度高,在边缘部分密度低.对富铟夹杂形成及不均匀分布的原因进行了分析,讨论了富铟夹杂对PL-Mapping发光峰峰值的影响.     

改进的垂直布里奇曼法生长CdZnTe晶体中的成分偏离现象

采用多种测试方法,对改进的垂直布里奇曼法生长Cd0.96Zn0.04Te晶体中的成分偏离标准化学计量比现象及其对晶体性能的影响进行了研究.X射线能谱成分测试表明,在晶锭的头部即初始结晶位置,(Cd Zn)/Te比大于1;而在中部及末端,小于1.表明这种方法生长的CZT晶体仍然存在对标准化学计量比的偏离现象,开始结晶是在富Cd熔体中,生长至中后段则是在富Te条件下进行的.PL谱测试表明,富Cd的晶片内存在大量Te空位,严重富Te的晶片内Cd空位及其杂质复合体等引起的缺陷密度显著增加.晶体红外透过率测试结果表明,接近化学计量配比的CZT晶片具有高的红外透过率.     

改进的垂直布里奇曼法生长CdZnTe晶体中的成分偏离现象

采用多种测试方法,对改进的垂直布里奇曼法生长Cd0.96Zn0.04Te晶体中的成分偏离标准化学计量比现象及其对晶体性能的影响进行了研究.X射线能谱成分测试表明,在晶锭的头部即初始结晶位置,(Cd+Zn)/Te比大于1;而在中部及末端,小于1.表明这种方法生长的CZT晶体仍然存在对标准化学计量比的偏离现象,开始结晶是在富Cd熔体中,生长至中后段则是在富Te条件下进行的.PL谱测试表明,富Cd的晶片内存在大量Te空位,严重富Te的晶片内Cd空位及其杂质复合体等引起的缺陷密度显著增加.晶体红外透过率测试结果表明,接近化学计量配比的CZT晶片具有高的红外透过率.     

液封直拉富铟InP中铟夹杂的纵向和横向分布

采用光学显微镜与红外透射显微镜相结合的方法,研究了磷化铟(InP)晶片中铟夹杂的形貌,通过比较含有铟夹杂的晶体与晶片,总结了铟夹杂在富铟磷化铟中的纵向与横向分布行为,并分析了熔体组分配比度、固液界面形貌以及温度梯度对铟夹杂分布行为的影响。在含有铟夹杂的单晶片中发现铟夹杂的一种特殊环形分布行为,对比和它相邻的晶片,发现这种环形分布呈现出沿生长方向直径逐渐变小的趋势,初步分析与固液界面呈微凸的形貌有关。在这种特殊分布中,发现部分铟夹杂呈四方对称分布。结合磷化铟的晶体结构,分析这种对称分布与固液界面处的{111}晶面有关。     

InSb(111)A面腐蚀坑成因分析

采用光学显微镜和光学轮廓仪分析了InSb晶片(111)A面经特定腐蚀剂腐蚀后出现的两种特征腐蚀坑,并通过多次腐蚀试验观察了这两种腐蚀坑形貌的演变。从理论上对腐蚀坑形貌的成因进行了分析,结果显示1类特征腐蚀坑的成因是由于晶片固有的位错缺陷,2类特征腐蚀坑可能是由于晶片表面存在一定深度的损伤层引起的。     

碳化硅晶片表面质量差异影响因素研究

分析了金刚石线锯多线切割150 mm SiC晶片的表面形貌及质量,通过测试SiC片Si面和C面的表面粗糙度(Ra),发现C面Ra值约为Si面的2倍。在切割过程中晶片向Si面弯曲,使锯丝侧向磨粒对Si面磨削修整作用更强,从而使晶片Si面更加光滑。此外,通过显微截面法测试了SiC晶片两面的损伤层深度。结果表明,Si面损伤层深度约为7.89 μm,明显低于C面的13.8 μm,显微镜下观察到截面边缘更加平整。该方法进一步证明了多线切割时晶片向Si面弯曲,使锯丝侧向磨粒对Si面的磨削效果更强,从而造成SiC晶片两面表面形貌和质量存在差异。     

富铟熔体生长InP晶体中的微观缺陷

通过原位磷注入液封直拉(LEC)法在富铟熔体中生长了100方向的磷化铟单晶,并研究了晶体内缺陷形态及形成机制。在富铟熔体中生长的磷化铟晶锭中发现,多种形态富铟夹杂物镶嵌在磷化铟基体中。在晶片的抛光过程中,由于局部受力不均匀导致富铟夹杂周围的晶体出现裂纹。通过研究发现,除了磷化铟晶体的各向异性外,局部的冷却条件也控制着晶体凝固过程,进而控制着富铟夹杂物的形态。由于磷化铟基体与富铟夹杂物的热膨胀系数不同,在富铟多面体夹杂物产生了很大的应力,进而导致富铟夹杂物附近出现了位错聚集现象。经讨论给出了这些夹杂物的形成机制及其对晶体质量的影响。     

Uniform precipitation of oxygen in large diameter wafers

In the present stage of development, 300 mm crystals often contain a transition from vacancy-rich to interstitial-rich. Due to this radially varying concentration of intrinsic point defects, the radial size distribution of grown-in oxide precipitate nuclei is also inhomogeneous in these wafers. In order to achieve a radially uniform bulk defect density for internal gettering, a slow temperature ramp induced growth of all grown-in oxide precipitate nuclei is the appropriate procedure to overcome problems resulting from the inhomogeneous size distribution of grown-in nuclei. This approach is based on the observation that in contrast to the nuclei size distribution, the nuclei density distribution is homogeneous over the wafer, independent of the dominant intrinsic point defect.     

快速退火气氛对300mm CZ硅片吸杂效应和表面微观结构的影响

研究了N2和N2/NH3混合气两种不同气氛快速退火处理硅片对洁净区和氧沉淀分布的影响.研究发现:N2/NH3混合气氛处理的硅片在后序热处理中表层形成很薄的洁净区同时体内形成高密度的氧沉淀;而N2气氛处理的硅片的沽净区较厚、氧沉淀密度较低.但是两种气氛下延长恒温时间都可以降低洁净区厚度,增加氧沉淀密度.X射线光电子能谱和原子力显微镜扫描的结果显示N2/NH3混合气氛处理使表面出现了强烈的氮化反应,利用氮化反应町以解释快速退火气氛对洁净区分布的影响.     

快速退火气氛对300mm CZ硅片吸杂效应和表面微观结构的影响

研究了N2和N2/NH3混合气两种不同气氛快速退火处理硅片对洁净区和氧沉淀分布的影响.研究发现:N2/NH3混合气氛处理的硅片在后序热处理中表层形成很薄的洁净区同时体内形成高密度的氧沉淀;而N2气氛处理的硅片的沽净区较厚、氧沉淀密度较低.但是两种气氛下延长恒温时间都可以降低洁净区厚度,增加氧沉淀密度.X射线光电子能谱和原子力显微镜扫描的结果显示N2/NH3混合气氛处理使表面出现了强烈的氮化反应,利用氮化反应町以解释快速退火气氛对洁净区分布的影响.     

Simulating the Effects of Internal Mechanical Stresses on the Decomposition Kinetics of a Supersaturated Oxygen Solution in Silicon

We justify and exactly formulate a method for simulating the effect of mechanical stresses induced in a system silicon matrix–oxygen precipitate (SiO₂) on the rates of fundamental processes determining the kinetics of precipitation. The developed model is based on the classical theory of kinetics of the first-order phase transitions with regard to the observed features of the SiO₂ particle growth in silicon (two-stage precipitation) and the main relations of the theory of elasticity. The proposed approach is used to establish and analyze the dependences of the main kinetic parameters describing the variations in the number of critical nuclei of the precipitate phase on the characteristics of the interfacial mechanical stresses induced and developed during the postcrystallization cooling of silicon wafers.     

重掺〈100〉硅单晶抛光片条纹状起伏缺陷研究

重掺〈100〉硅单晶片抛光后经微分干涉显微镜观测。抛光片边缘区域存在条纹状起伏缺陷。通过分析条纹状起伏缺陷与重掺硅单品中杂质的分布状况和〈100〉品面本身腐蚀特性的关系，阐述了条纹状起伏缺陷形成的机理。通过工艺试验，对比了不同工艺条件下抛光片表面微观形貌状况，分析了抛光过程中各工艺条件对表面条纹起伏缺陷的影响，采用3步抛光工艺，得到了表面平整和一致性好的抛光片表面，抛光片边缘尤条纹起伏缺陷。     

Chromium distribution in multicrystalline silicon: comparison of simulations and experiments

We studied the precipitation of chromium in multicrystalline silicon during the crystallization process and temperature treatments typical for solar cell processing. A model which was already successfully used for simulating heterogeneous precipitation of iron is transferred to chromium, allowing two‐dimensional simulations of dissolved chromium and precipitate density. The observed accordance with spatially resolved measurements demonstrates the similarity of chromium to iron precipitation and the ability of our model to predict the dissolved chromium concentration in multicrystalline silicon. After the crystallization process, a high impact of chromium on the carrier lifetime of wafers originating from an ingot intentionally contaminated with 20 ppma chromium in the melt was observed. The concentration of dissolved chromium was significantly reduced by phosphorus diffusion gettering or oxidation at 815°C. Copyright © 2012 John Wiley & Sons, Ltd.     

根据红外透过率推断CdZnTe晶片的性能

采用傅里叶变换红外光谱仪测试了性能各异的多个CdZnTe晶片的红外透过率．研究表明，红外透过率的大小可以定性反映CdZnTe晶片的性能：红外透过率越高的晶片，其成分偏离越小，位错密度越低，电阻率越高．根据红外透过率大小随着波数的变化，红外透过率图谱可以分为4种，每一种图谱对应着具有不同性能的CdZnTe晶片，从晶片对红外光的吸收机理出发，对实验结果进行了初步分析。     

Spatial characterization of process variations via MOS transistortime constants in VLSI and WSI

This paper is the first large-scale experimental characterization of spatial process variations for a parameter that is directly involved in timing issues: the MOS transistor time constant. This is achieved by measuring the oscillation period of highspeed (500 MHz) CMOS ring oscillators that are implemented at different locations on individual dies and over wafers. Novel phenomena are observed, improving our understanding of how process variations affect the performance of synchronous systems, particularly in clock distribution networks. We observed four components contributing to period variations: an environment-dependent component, a process-dependent component of lower spatial frequency, a random component analogous to white noise, and a component depending on the geometry of the power-supply distribution network     

A directed-graph classifier of semiconductor wafer-test patterns

A technique for training an expert system for semiconductor wafer fabrication process diagnosis is described. The technique partitions an existing set of electrically tested semiconductor wafers into groups so that all wafers within each group have similar spatial distributions of the electrical test data across selected die sites. The spatial distribution of test data from the selected die sites on each wafer is referred to as the test pattern of that wafer. A directed graph that is developed by the partitioning algorithm then efficiently classifies a new incoming wafer to one of the groups established during partitioning on the basis of its test pattern. The distribution of known processing histories of wafers within the group to which the new incoming wafer is classified provides a provisional diagnosis of the incoming wafer's process history     

SOI/bulk hybrid technology on SIMOX wafers for high performancecircuits with good ESD immunity

A new SOI/bulk hybrid technology with devices on both the thin film and the bottom substrate of SIMOX wafers has been studied. By fabricating ESD protection circuits on the substrate of SIMOX wafers, ESD reliability of high performance CMOS SOI circuits can be significantly improved. Despite the higher surface defect density and micro-roughness on the bottom substrate of SIMOX wafers compared to ordinary bulk wafers, similar electron mobility, intrinsic thermal oxide properties and hot-carrier degradation are observed among MOSFET's fabricated on the different substrates. Thus, the hybrid technology is capable of combining the advantages both of SOI and bulk technology in fabricating high performance circuits