Effect of GaAs surface pretreatment on electrical properties of MBE-ZnSe/GaAs substrate interfaces

Interface properties of MBE-grown ZnSe/GaAs substrate systems formed on variously pretreated GaAs surfaces, which include standard chemically etched (5H₂SO₄:1H₂O₂: 1H₂O), (NH₄)₂S_x-, NH₄I-, and HF-pretreated surfaces, are investigated by capacitance-voltage (C-V) and deep level transient spectroscopy (DLTS) measurements. A HF-pretreated and annealed ZnSe/p-GaAs sample showed marked reduction of interface state density, N_ss, with N_ss,_min below 4 x 10¹¹cm^-2 eV^-1 near E_c- E_FS= 1.0 eV. The value is about one order of magnitude smaller than that of the standard chemically etched interface, and comparable to (NH₄)₂S_x- pretreated interface. Nevertheless, C-V characteristics of ZnSe/nGaAs samples, which were measured for the first time, indicate that interface Fermi level, E_FS, is not completely unpinned due to the interface states located above the midgap. A consistent result was obtained by DLTS method in determining E_FS position. The influence of N_ss distribution on vertical current conduction is also analyzed. It is found that U-shaped interface states with N_ss(E) > 1 x 10¹³ cm^-2 eV^-1 above the midgap may cause an excess voltage drop larger than a few volts at the interface.     

Adaptation of admittance analysis to extract interface traps of a-Si:H/c-Si heterojunctions

Complete admittance expressions, adapted from the equations previously presented for Metal/Oxide/Semiconductor (MOS) structure, were derived and modified admittance approach was successfully applied on a-Si:H/c-Si heterojunction to deduce surface state density (N_ss) by employing capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements. Through the approach, N_ss was determined as 6×10¹² cm⁻² eV⁻¹ that was mutually checked by continuum model, used previously for evaluating N_ss in MOS structure. Furthermore, locating such an amount at the interface of a-Si:H and c-Si, experimentally measured C–V curve was reproduced through AFORS-HET simulation program. Presence of such a large amount of N_ss was originated due to native oxide layer, confirmed through spectroscopic elipsometry measurement.     

Interface profile optimization in novel surface passivation scheme for InGaAs nanostructures using Si interface control layer

This paper attempts to control and optimize the interface atomic profiles of a novel surface passivation scheme for InGaAs nanostructures, using a silicon interface control layer (ICL). An in-situ x-ray photoelectron spectroscopy characterization technique was used to establish a process sequence that satisfies the conditions of maintenance of pseudomorphic matching to InGaAs, prevention of direct oxidation of InGaAs, and formation of a good SiO₂/Si interface with minimal suboxide components. It is shown that the above conditions can be satisfied by a new process that is a formation of the thermal SiO₂ at the SiO₂-Si interface by repetition of deposition/oxidation/annealing cycle. A large reduction of interface state density (N_ss) was realized by the optimization of the new process, resulting in a minimum N_ss of 4 × 10¹¹ cm⁻² eV⁻¹. The silicon ICL technique was successfully applied to the passivation of InGaAs wire structures.     

The interface states analysis of the MIS structure as a function of frequency

The energy distribution of interface states (N_ss) and their relaxation time (τ) were of the fabricated the Al/SiO₂/p-Si (MIS) structures were calculated using the forward bias current-voltage (I-V), capacitance-frequency (C-f) and conductance-frequency (G-f) measurements. Typical ln[I/(1 − exp(−qV/kT)] versus V characteristics of MIS structure under forward bias show one linear region. From this region, the slope and the intercept of this plot on the current axis allow to determine the ideality factor (n), the barrier height (Φ_b) and the saturation current (I_S) evaluated to 1.32, 0.77 eV and 3.05 × 10⁻⁹ A, respectively. The diode shows non-ideal I-V behaviour with ideality factor greater than unity. This behaviour is attributed to the interfacial insulator layer at metal-semiconductor interface, the interface states and barrier inhomogeneity of the device. The energy distribution of interface states (N_ss) and their relaxation time (τ) have been determined in the energy range from (0.37 − E_v) to (0.57 − E_v) eV. It has been seen that the N_ss has almost an exponential rise with bias from the mid gap toward the top of valance band. In contrary to the N_ss, the relaxation time (τ) shows a slow exponential rise with bias from the top of the E_v towards the mid gap energy of semiconductor. The values of N_ss and τ change from 6.91 × 10¹³ to 9.92 × 10¹³ eV⁻¹ cm⁻² and 6.31 × 10⁻⁴ to 0.63 × 10⁻⁴ s, respectively.     

The effects of surface states and series resistance on the performance of Au/SnO2/n-Si and Al/SnO2/p-Si (MIS) Schottky barrier diodes

We have fabricated two types of Schottky barrier(SBDs),Au/SnO₂/n-Si (MIS1) and Al/SnO₂/p-Si (MIS2), to investigate the surface (N_ss) and series resistance (R_s) effect on main electrical parameters such as zero-bias barrier height (Φ_Bo) and ideality factor (n) for these SBDs. The forward and reverse bias current–voltage (I–V) characteristics of them were measured at 200 and 295 K, and experimental results were compared with each other. At temperatures of 200 and 295 K, Φ_Bo, n, N_ss and R_s for MIS1 Schottky diodes (SDs) ranged from 0.393 to 0.585 eV, 5.70 to 4.75, 5.42×10¹³ to 4.27×10¹³ eV^?1 cm^?2 and 514 to 388 Ω, respectively, whereas for MIS2 they ranged from 0.377 to 0.556 eV, 3.58 to 2.1, 1.25×10¹⁴ to 3.30×10¹⁴ eV^?1 cm^?2 and 312 to 290 Ω, respectively. The values of n for two types of SBDs are rather than unity and this behavior has been attributed to the particular distribution of N_ss and interfacial insulator layer at the metal/semiconductor interface. In addition, the temperature dependence energy density distribution profiles of N_ss for both MIS1 and MIS2 SBDs were obtained from the forward bias I–V characteristics by taking into account the bias dependence of effective barrier height (Φ_e) and R_s. Experimental results show that both N_ss and R_s values should be taken into account in the forward bias I–V characteristics. It has been concluded that the p-type SBD (MIS2) shows a lower barrier height (BH), lower R_s, n and N_ss compared to n-type SBD (MIS1), which results in higher current at both 200 and 295 K.     

Low frequency noise characterization in 0.13 μm p-MOSFETs. Impact of scaled-down 0.25, 0.18 and 0.13 μm technologies on 1/f noise

This paper presents an experimental analysis of the noise measurements performed in 0.13 μm technology p-MOS transistors operating from weak to strong inversion in ohmic and saturation regimes. The 1/f noise origin is interpreted in terms of carrier number with correlated mobility fluctuations. The contribution of the access resistance noise is noticed for large overdrive voltages. The slow oxide trap density N_t(E_F) and the Coulomb scattering noise parameter α_s have been extracted. Then the 1/f noise level in the three scaled-down p-MOSFETs generations (0.25, 0.18 and 0.13 μm) is compared. The variation of the noise parameter values is discussed with respect to the technology node. The highest oxide trap density is obtained for the thinnest gate oxide. It is concluded that the oxide thinning should lead to noise reduction only if the product t_ox². N_t is taken into consideration. This trend will be significant in future scaled-down MOSFETs.     

Effect of high-temperature H2-anneals on the slow-trapping instability of MOS structures

It is shown that the slow-trapping instability upon negative bias-temperature aging of MOS structures (poly-Si and Al-gate) can be significantly reduced by a high temperature (800–900°C) H₂-anneal prior to Al metallization. Additional data are presented on the effects of high (700–900°C) and low temperature (450°C) H₂ annealing of MOS structures containing n-(111) Si, dry HCl oxide and B-doped poly-Si. The midgap N_ss (range: 8×10¹¹ to 1.5×10¹⁰ cm^?2 eV^?1) is reduced by both high and low temperature H₂ anneals whereas the Q_ss (range: 7×10¹¹ to 1×10¹¹ cm^?2 eV^?1) is reduced mainly by the high-temperature H₂-anneals. Presence of B near the interface is believed to cause an abnormal voltage asymmetry of the slow-trapping drift, i.e. ΔV_FB(-BT) < ΔV_FB(+BT). These effects are discussed in the light of Deal's model of the structure of the Si/SiO₂ interface.     

Improved Interface and Electrical Properties by Inserting an Ultrathin SiO2 Buffer Layer in the Al2O3/Si Heterojunction

An ultrathin SiO₂ interfacial buffer layer is formed using the nitric acid oxidation of Si (NAOS) method to improve the interface and electrical properties of Al₂O₃/Si, and its effect on the leakage current and interfacial states is analyzed. The leakage current density of the Al₂O₃/Si sample (8.1 × 10^?9 A cm^?2) due to the formation of low‐density SiO_x layer during the atomic layer deposition (ALD) process, decreases by approximately two orders of magnitude when SiO₂ buffer layer is inserted using the NAOS method (1.1 × 10^?11 A cm^?2), and further decreases after post‐metallization annealing (PMA) (1.4 × 10^?12 A cm^?2). Based on these results, the influence of interfacial defect states is analyzed. The equilibrium density of defect sites (N_d) and fixed charge density (N_f) are both reduced after NAOS and then further decreased by PMA treatment. The interface state density (D_it) at 0.11 eV decreases about one order of magnitude from 2.5 × 10¹² to 7.3 × 10¹¹ atoms eV^?1 cm^?2 after NAOS, and to 3.0 × 10¹⁰ atoms eV^?1 cm^?2 after PMA. Consequently, it is demonstrated that the high defect density of the Al₂O₃/Si interface is drastically reduced by fabricating ultrathin high density SiO₂ buffer layer, and the insulating properties are improved.     

Interface states under LOCOS bird's beak region

A method has been developed which allows the extraction of the density of electrically active defects in the bird's beak region of LOCOS isolation of a MOS structure. The measurements were performed on a special structure with enhanced edge effects using quasi-static techniques. The experimental results are compared with simulations using a model which allows for the inclusion of surface states in the bird's beak region. It is found that the best fit is obtained for a uniform energy distribution with N_ss = 1E12 cm⁻² eV⁻¹, while the states are situated in the bird's beak region up to 1800 Å from the gate oxide edge.     

The wavelet transform based processing means for 1/f noise in millimeter wave focal plane array

After briefly introducing the characteristics of 1/f noise in millimeter wave focal plane array detectors, the paper analyses the relation of wavelet transform and 1/f noise in detail, suggests the fashion of decorrelating 1/f noise using the wavelet transform and deduces the relative expressions. The results of computer simulation show good effectiveness.     

Effect of epilayer characteristics and processing conditions on the thermally oxidized SiO2/SiC interface

The optimization of the SiO₂/SiC interface is critical for the development of SiC MOS devices. We investigate the effects of several variables spanning both epilayer attributes and processing conditions relative to our control oxidation process. Varying the shallow vicinal angle of the wafer does not affect the interface. There is a definite degradation of the interface as the epilayer doping density is increased. Sacrificial oxidation appears to reduce the number of border traps in the final oxide. Fluorine annealing has no effect on the interface quality. A low temperature (950°C) re-oxidation, which follows a bulk oxide growth at 1150°C, reduces D _it to the mid-10¹⁰ cm⁻²eV⁻¹ range near midgap and Q_f to a reacord low 5×10¹¹ cm⁻².     

ZrON/GeON 双钝化层改善Ge MOS器件的界面特性和电特性

本文研究了利用等离子体氮化形成ZrON/GeON双钝化层制备Ge MOS器件的界面特性和电特性。结果发现,相比于N2等离子处理,NH3等离子处理制备的双钝化层显著改善了器件的界面和电特性,获得了低的界面态密度 (Dit = 1.64×1011 cm-2 eV-1)和栅极漏电流(Jg = 9.32×10-5 A cm-2@Vfb +1 V),小的电容等效厚度 (CET = 1.11 nm)以及高的k值 (32). XPS分析表明,由NH3等离子体分解出的H原子和NH基团可以有效促进Ge表面不稳定低k GeOx的挥发,从而形成了高质量的GeON钝化层;且NH3等离子体氮化导致更多氮在ZrON/GeON中结合,能更有效阻止O、Ti、Ge等元素间的相互扩散,从而获得好的界面质量和电特性。     

Low-frequency noise characteristics in the MOSFETs processed in 65 nm technology

Low-frequency noise behavior in the MOSFETs processed in 65 nm technology is investigated in this paper. Low-frequency noise for NMOS transistors agrees with McWhorter''s theory (carrier number fluctuation), low-frequency noise in the sub-threshold regime agrees with McWhorter''s theory for PMOS transistors while it agree with Hooge''s theory (carrier mobility fluctuation) in the channel strong inversion regime. According to carrier number fluctuation model, the extracted trap densities near the interface between channel and gate oxide for NMOS and PMOS transistor are 3.94×10¹⁷ and 3.56×10¹⁸ cm^-3/eV respectively. According to carrier mobility fluctuation model, the extracted average Hooge''s parameters are 2.42×10^-5 and 4×10^-4. By consideration of BSIM compact model, it is shown that two noise parameters (NOIA and NOIB) can model the intrinsic channel noise. The extracted NOIA and NOIB are constants for PMOS and their values are equal to 3.94×10¹⁷ cm^-3/eV and 9.31×10^-4 V^-1. But for NMOS, NOIA is also a constant while NOIB is inversely proportional to the effective gate voltage. The extracted NOIA and NOIB for NMOS are equal to 3.56×10¹⁸ cm^-3/eV and 1.53×10^-2 V^-1. Good agreement between simulation and experimental results is achieved.     

The frequency-dependent electrical characteristics of interfaces in the Sn/p-Si metal semiconductor structures

The purpose of this paper is to investigate frequency-dependent electrical characteristics of the interface states in Sn/p-Si metal semiconductor (MS) Schottky structures. To yield quantitative information about their frequency (f) and voltage (V) dependent characteristics, Sn/p-Si MS structures have been studied by using capacitance (C) and conductance (G/ω) measurements over a wide range of frequencies (50 kHz-1 MHz). The increase in capacitance at lower frequencies is seen as a signature of interface states, and the densities of which are evaluated to be of the order of ≅10¹⁰ cm⁻² eV⁻¹. The presence of the interfaces states (N_SS) is also evidenced as a peak in the capacitance-frequency characteristics that increases in magnitude with decreasing frequencies. Furthermore, the voltage and frequency dependence of series resistance (R_S) were calculated from the C-V and G/ω-V measurements and plotted as functions of voltage and frequency. The effect of R_S on C and G/ω is found noticeable at high frequencies. The C-V-f and G/ω-V-f characteristics of studied structures show fairly large frequency dispersion especially at low frequencies due to N_SS in equilibrium with the semiconductor. The experimental values of interface state densities and series resistance from C-V-f and G/ω-V-f measurements were obtained in the ranges of 3.46 × 10¹⁰−1.26 × 10⁹ cm⁻² eV⁻¹ and 71.1-57.3 Ω, respectively. Experimental results show that both the R_S and N_SS values should be taken into account in determining frequency-dependent electrical characteristics.     

Electrical properties of ultrathin oxide grown by high pressure oxidation and N2O nitridation for ULSI device applications

For the first time, the feasibility of ultrathin oxides grown by high pressure oxidation (HIPOX) technology in O₂ ambient and nitrided in N₂O ambient with rapid thermal processing has been investigated in order for them to be used as a gate oxide of ULSI devices. The dielectric breakdown electric field (E _BR) and the midgap interface trap density (D _itm) of the nitrided-HIPOX oxide are ?13:9MVcm^?1 and 2 × 10¹⁰cm^?2eV^?1 respectively which are almost the same as those of the control oxide and the nitrided-control oxide. The time-tobreakdown (t_BD) of the nitrided-HIPOX oxide is longer than that of the control oxide at low electric field (<10^?4 A cm^?2) owing to the combination of nitrogen and defects near the Si?SiO₂ interface during nitridation. The lifetimes of the nitrided-HIPOX oxides increase initially, reaching a maximum value of 1:2 × 10⁹ s at a stress current density of 1 × 10^?6 A cm^?2,corresponding to over 10 years, and then decrease as nitridation proceeds.     

Investigation on interfacial and electrical properties of Ge MOS capacitor with different NH3-plasma treatment procedure

The effects of different NH₃-plasma treatment procedures on interfacial and electrical properties of Ge MOS capacitors with stacked gate dielectric of HfTiON/TaON were investigated. The NH₃-plasma treatment was performed at different steps during fabrication of the stacked gate dielectric, i.e. before or after interlayer (TaON) deposition, or after deposition of high-k dielectric (HfTiON). It was found that the excellent interface quality with an interface-state density of 4.79×10¹¹ eV^-1cm^-2 and low gate leakage current (3.43×10^-5A/cm² at V_g=1 V) could be achieved for the sample with NH₃-plasma treatment directly on the Ge surface before TaON deposition. The involved mechanisms are attributed to the fact that the NH₃-plasma can directly react with the Ge surface to form more Ge-N bonds, i.e. more GeO_xN_y, which effectively blocks the inter-diffusion of elements and suppresses the formation of unstable GeO_x interfacial layer, and also passivates oxygen vacancies and dangling bonds near/at the interface due to more N incorporation and decomposed H atoms from the NH₃-plasma.     

Comparison of MOS capacitors on n- and p-type GaN

The electrical characteristics of both n- and p-type GaN metal-oxide semiconductor (MOS) capacitors utilizing plasma-enhanced CVD-SiO₂ as the gate dielectric were measured. Both capacitance and conductance techniques were used to obtain the MOS properties (such as interface state density). Devices annealed at 1000°C/30 min. in N₂ yielded an interface state density of 3.8×10¹⁰ cm⁻² eV⁻¹ at 0.19 eV from the conduction band edge, and it decreased to 1.1×10¹⁰ cm⁻² eV⁻¹ deeper into the band gap. A total fixed oxide charge density of 8×10¹² q cm⁻² near the valence band was estimated. Unlike the symmetric interface state density distribution in Si, an asymmetric interface state density distribution with lower density near the conduction band and higher density near the valence band was determined.     

Modeling and Understanding the Compact Performance of h-BN Dual-Gated ReS2 Transistor

In this study, high-performance few-layered ReS₂ field-effect transistors (FETs), fabricated with hexagonal boron nitride (h-BN) as top/bottom dual gate dielectrics, are presented. The performance of h-BN dual gated ReS₂ FET having a trade-off of performance parameters is optimized using a compact model from analytical choice maps, which consists of three regions with different electrical characteristics. The bottom h-BN dielectric has almost no defects and provides a physical distance between the traps in the SiO₂ and the carriers in the ReS₂ channel. Using a compact analyzing model and structural advantages, an excellent and optimized performance is introduced consisting of h-BN dual-gated ReS₂ with a high mobility of 46.1 cm² V⁻¹ s⁻¹, a high current on/off ratio of ≈10⁶, a subthreshold swing of 2.7 V dec⁻¹, and a low effective interface trap density (N_t,eff) of 7.85 × 10¹⁰ cm⁻² eV⁻¹ at a small operating voltage (<3 V). These phenomena are demonstrated through not only a fundamental current–voltage analysis, but also technology computer aided design simulations, time-dependent current, and low-frequency noise analysis. In addition, a simple method is introduced to extract the interlayer resistance of ReS₂ channel through Y-function method as a function of constant top gate bias.     

ICP-induced defects in GaN characterized by capacitance analysis

The defects induced by inductively coupled plasma reactive ion etching (ICP-RIE) on a Si-doped gallium nitride (GaN:Si) surface have been analyzed. According to the capacitance analysis, the interfacial states density after the ICP-etching process may be higher than 5.4 × 10¹² eV⁻¹ cm⁻², compared to around 1.5 × 10¹¹ eV⁻¹ cm⁻² of non-ICP-treated samples. After the ICP-etching process, three kinds of interfacial states density are observed and characterized at different annealing parameters. After the annealing process, the ICP-induced defects could be reduced more than one order of magnitude in both N₂ and H₂ ambient. The H₂ ambient shows a better behavior in removing ICP-induced defects at a temperature around 500 °C, and the interfacial states density around 2.2 × 10¹¹ eV⁻¹ cm⁻²can be achieved. At a temperature higher than 600 °C, the N₂ ambient provides a much more stable interfacial states behavior than the H₂ ambient.