Temperature dependence of MOS transistor characteristics below saturation

The temperature dependence of MOS transistor characteristics in the region below saturation is studied theoretically and experimentally. The variation of channel conductance with temperature is shown to be due to the variation of the threshold voltage and of the inversion layer mobility. Both variations can be predicted in reasonable agreement with experimental observations. It is shown that the role of fast surface states in determining the temperature dependence is negligible.     

A d.c. model for an MOS-transistor in the saturation region

A d.c. model for an MOS-transistor, operating in the saturation region, is presented. Drain current as well as drain conductance are shown to be in good agreement with measurements.The saturation is characterised by two parameters f and z which can be determined from measured device characteristics. The saturation voltage is defined as the drain voltage at which the lateral component of the surface electric field at the channel end equals the value ν_sc/μ₀.     

An analytical model for high electron mobility transistors

In this paper we present a new model for HEMT's which is based on a single analytical function that describes the electron concentrations in the two dimensional electron gas and in the AlGaAs layer. Besides accounting for the AlGaAs conduction, the model includes the effect of mobility degradation, channel length modulation in the saturation region and the series resistances R_S and R_D. The model results in closed form expressions for the current, transconductance, output conductance and gate capacitance. Finally, the theoretical predictions of the model are compared with the experimental data and shown to be in good agreement over a wide range of bias conditions     

The saturation characteristics of high-voltage transisitors

It is shown that the saturation characteristic of high-voltage NPvN transistors can only be explained by a lowering of the v-layer resistance due to conductivity modulation. A semi-quantitative model is developed which explains this modified saturation region. An experimental method of isolating the resistive portion of the external collector-base (CB) voltage is presented. The results verify that the CB junction may be forward-biased even when the characteristic seemingly indicates that the transistor is unsaturated. Data is also presented showing how variations in collector resistivity and thickness alter the saturation region.     

Current tuning and the concept of avalanche resonance in IMPATT diodes under large signal operating conditions

The concept of current tuning, i.e. the increase of optimum frequency with current density, is well-known in IMPATT diodes. An explanation of the phenomenon by postulating an avalanche resonance frequency was derived by Gilden and Hines from small-signal theory. Difficulties arise however when the small-signal theory is extrapolated to large signal operation. This paper provides a coherent explanation of the zero conductance and susceptance frequencies (which can be related to the avalanche resonance concept in an idealised diode model) and current tuning by utilizing a modified approach to Gilden and Hines theory which can then be extrapolated to large signal behaviour. Large signal computer simulation of diodes is used to verify the conclusions on the zero conductance and susceptance frequencies and current tuning under large signal conditions with varying frequency, drive level and current density. By examining the waveforms of the simulated diodes the cause of the zero conductance frequency (avalanche resonance at small signal levels) and current tuning can be shown to be due to the perturbation of the avalanche region electric field by the space charge of the drifting charge bunch.     

New short-channel n-MOSFET current-voltage model in stronginversion and unified parameter extraction method

A semiempirical strong inversion current-voltage (I-V) model for submicrometer n-channel MOSFETs which is suitable for circuit simulation and rapid process characterization is proposed. The model is based on a more accurate velocity-field relationship in the linear region and finite drain conductance due to the channel length modulation effect in the saturation region. The parameter extraction starts from the experimental determination of the MOSFET saturation current and saturation voltage by differentiating the output characteristics in a unified and unambiguous way. These results are used in order to systematically extract the device and process parameters such as the effective electron saturation velocity and mobility, drain and source series resistances, effective gate length and characteristic length for channel length modulation, and short-channel effects. The values agree well with other independent measurements. The results of experimental studies of wide n-MOSFETs with nominal gate length of 0.8, 1.0, and 1.2 μm fabricated by an n-well CMOS process are reported. The calculated I-V characteristics using the extracted parameters show excellent agreement with the measurement results     

Tunneling in MIS structures—I Theory

Quantum mechanical tunneling through insulating barriers has received considerable attention in recent years, especially in metal-insulator-metal systems and p−n junctions. It is the purpose of this paper to discuss tunneling in the MIS contact. In this paper we define the d.c. currents which flow and then calculate the voltage distribution in the contact. It is found that as long as the semiconductor spacecharge region is of the order of the insulator thickness ( 50 Å) considerable voltage drops across the semiconductor. Using this, a voltage region of low conductance is shown to exist, over which the metal Fermi level is opposite the forbidden gap of the semiconductor. This region is shown to be greater than the semiconductor energy gap. In addition, the a.c. frequency dependent currents which flow in an MIS contact due to interface states are calculated. It is shown that interface states can contribute to the a.c. conductance via two mechanisms; time lag in trapping and recombination of carriers in the semiconductor bands and tunneling via interface states. Both of these mechanisms are discussed and the conditions under which one or the other make the major contribution to the a.c. conductance is analyzed.     

A simple analytical model for hot-carrier MOSFETs

Several second-order effects such as mobility degradation, carrier velocity saturation, and channel-length modulation are included in the model. The source-drain series resistances are accounted for, and a simple formula to calculate the output conductance without creating a discontinuity at the transition from the linear to the saturation region is proposed. The accuracy of the model is confirmed by comparing its theoretical predictions with the experimental data available in the literature. The model is used to estimate the lateral electric field at the drain to which hot-carrier effects are sensitive     

The effects of fixed bulk charge on the characteristics of metal-oxide-semiconductor transistors

The theory of the characteristics of the MOS transistors is developed based on a model in which both the bulk charge due to the ionized impurity in the semiconductor substrate and the difference between the electrostatic potential and the voltage drop in the channel are included. A detailed comparison of the theory is made with experimental data of gate capacitance, drain current voltage characteristics, and transconductance characteristics on both N-channel and P-channel silicon devices with thin (2000 A) and thick (6200 and 8400 A) oxides under the gate electrode. The correlation is good using the surface mobility as the adjustable parameter. Mobility reduction in the saturation transconductance characteristics is predicted in the theory and demonstrated in the experimental data. It arises entirely from the bulk charge, which modifies the device characteristics, and is not associated with some basic surface scattering phenomena, which further reduce the mobility. It is also demonstrated experimentally that to evaluate a physically meaningful surface mobility from the conductance of the channel, the interface surface state charge Qsscannot be assumed constant in the devices used in this study.     

薄膜全耗尽SOI短沟道MOSFET准二维电流模型

本文在分析薄膜全耗尽SOI器件特殊物理效应的基础上,建立了可细致处理饱和区工作特性的准二维电流模型。该模型包括了场效应载流子迁移率、速度饱和以及短沟道效应等物理效应,可以描述薄膜全耗尽SOI器件所特有的膜厚效应、正背栅耦合(背栅效应)等对器件特性的影响,并且保证了电流、电导及其导数在饱和点的连续性。将模型模拟计算结果与二维器件数值模拟结果进行了对比,在整个工作区域(不考虑载流子碰撞离化的情况下)二者吻合得很好。     

Analytical expressions for the static MOS transistor characteristics based on the gradual channel model

Analytical solutions are derived from Pao and Sah's double integral formula for the theoretical static I–V characteristics of MOS transistors including both the diffusion and drift currents based on the gradual channel model. Expressions for the entire saturation, non-saturation and low level current regions are given, while the specific importance of the theory is seen in the cross-over region between low level and normal operation. Reddi and Sah's formula for channel shrinkage is modified and included to account for the small drain conductance in the saturation region by taking the drain avalanche breakdown voltage into consideration. The solutions are compared with experimental data, and the effectiveness and the limit of the theory is quickly examined.     

A charge-sheet capacitance model based on drain current modeling

Analytical models of the drain current and the capacitances of a MOSFET are formulated using the charge-sheet approach. Mobility reduction due to velocity saturation and interface scattering of carriers are taken into account. A saturation criterion is developed from the condition of output conductance continuity. The capacitance modeling does not require additional parameters not contained in the DC model. Comparison with experimental data confirms that the theory is useful for analog circuit simulation down to channel lengths of about 1 μm     

Holding time degradation in dynamic MOS RAM by injection-induced electron currents

The holding time degradation of a dynamic MOS RAM caused by a peripheral MOS device operated in the saturation region is discussed. It is shown that the process taking place is injection of electrons into a positively biased substrate region from a grounded junction. This junction becomes forward biased due to the resistive potential drop on the substrate caused by the high substrate current of the short-channel MOS device operated in the saturation region. The model presented in the literature of secondary-impact ionization of holes in the depletion-region edge being responsible for the degradation phenomenon is shown to be inconsistent with experimental results and theoretically improbable.     

Theory and experiments of low-frequency generation-recombination noise in MOS transistors

A theoretical model for the generation-recombination (g-r) noise in MOS transistors is presented. This model takes into account the charge induced on all electrodes by the charge fluctuation of the impurity center in the depletion region. The model gives a finite equivalent gate noise resistance at saturation. Gold-doped and no-gold control devices were fabricated to verify the theory experimentally. The drain-voltage dependence of the g-r noise, which is shown to be distinctly different from the 1/f noise and thermal noise, is used to check the theory. Good agreement between theory and experiment is obtained.     

An injection level dependent theory of the MOS transistor in saturation

A qualitative and quantitative theory of the MOS transistor in saturation is developed, taking into account the fact that the carrier concentration in the drain region is not negligible. With reference to the behavior in saturation, an injection level is defined. This level is directly related to two parameters: the drain saturation field EDSand the effective depth of the drain region xD. A division of the current domain in low, medium, and high levels is proposed. For low injection levels (for which the saturation field is smaller than the critical field), an iterative procedure for the calculation of the drain saturation conductance is given. A method for determining the channel configuration is presented. Inconsistencies in the pinchoff concept are revealed by the calculation of this configuration and by the analysis of the validity domain of the equations based on gradual approximation.     

多晶硅/氧化硅界面的二次离子质谱分析

利用二次离子质谱仪对多晶硅/氧化硅界面进行分析,发现多晶硅/氧化硅界面不是突变的,而存在着一个过渡区;根据多晶硅薄膜的成核理论,分析该过渡区形成的物理起源和机理,并利用"氧化层电导"模型,定量分析过渡区对器件栅氧化层电导的影响.     

Simulation of the accumulation-punchthrough mode in depletion MOSFETs

An analytical model is developed for a depletion MOSFET with a built-in channel operating in the accumulation-punchthrough mode. The model equations take into account several important effects associated with this mode of operation, including charge sharing between the channel and the source and drain regions. Closed-form expressions are derived for the output I–V characteristics, drain conductance in the linear region, and gate and substrate transconductances in the saturation region. Useful equations for the threshold and saturation voltages are also provided. High accuracy of the model is confirmed by the experimental results.     

Finite-element simulation of GaAs MESFET's with lateral doping profiles and submicron gates

Results of a two-dimensional finite-element simulation of a GaAs MESFET are presented. The simulation is used to determine the drain current and transconductance as well as the two-dimensional voltage, electron density, and electric-field distributions. It is shown that placement of a compensated doping region in the high electric-field region between gate and drain increases the drain current and transconductance by reducing the velocity-saturation effect. The transconductance and drain conductance of the MESFET in the saturation region of devices having different channel heights are compared with previous analysis.