Novel combined through-wafer-groove fabrication approach and its application in wafer level packaging of GaAs CCD

This paper presents a novel combined through-wafer-groove fabrication approach, which is applied to the wafer level packaging (WLP) of GaAs charge coupled devices (CCD) for electrical interconnection. The combined methodology includes mechanical dicing of the groove and wet chemical etching for polishing. The parameters of the mechanical dicing are researched, including feed speed, dicing directions of the wafer, and cutting depth, to minimize the chipping. Two kinds of chemical solution are tried, and the results are discussed. Besides, the etch rate is measured, which provides a guideline for the process design. Finally, GaAs-CCD WLP sample is achieved and the electrical properties are tested to validate the feasibility of this fabrication approach. This methodology is featured by low cost, low process temperature, and good process uniformity.     

Process development of a novel wafer level packaging with TSV applied in high-frequency range transmission

The process development of a novel wafer level packaging with TSV applied in high-frequency range transmission is presented. A specially designed TSV structure (a core TSV and six shielding TSVs) is adopted to connect the components on different sides of the high-resistivity silicon wafer. And the microstrip line in the microwave monolithic integrated circuit is used to transmit high-frequency signal in packaging structure together with the low permittivity intermediate dielectric polymer, benzocyclobutene. The TSV fabrication process and the multi-layer interconnection is illustrated in details. The electrical measurement result of the microstrip lines connected by TSVs reveals the resistances within 0.719 Ω, a return loss better than 23.8 dB and an insertion loss better than 2.60 dB from 14 to 40 GHz.     

基于多晶硅填充的TSV工艺制作

硅通孔( TSV)技术用于MEMS器件可实现器件结构的垂直互联,达到减小芯片面积、降低器件功耗等目的。对TSV结构的刻蚀和填充工艺进行了研究,通过优化ICP刻蚀工艺参数获得了端口、中部、底部尺寸平滑减小、深宽比大于20∶1的硅通孔;利用LPCVD技术实现了基于多晶硅的通孔无缝填充;经测试,填充后通孔绝缘电阻达10 GΩ以上,电绝缘性能良好。     

Wafer-level bonding and direct electrical interconnection of stacked 3D MEMS by a hybrid low temperature process

The presented fabrication technology enables the direct integration of electrical interconnects during low temperature wafer bonding of stacked 3D MEMS and wafer-level packaging. The low temperature fabrication process is based on hydrophilic direct bonding of plasma activated Si/SiO₂ surfaces and the simultaneous interconnection of two metallization layers by eutectic bonding of ultra-thin AuSn connects. This hybrid wafer-level bonding and interconnection technology allows for the integration of metal interconnects and multiple materials in stacked MEMS devices. The process flow is successfully validated by fabricating test structures made out of a two wafer stack and featuring multiple ohmic electrical interconnects.     

圆片级封装铝锗键合后残余应力的测量和分析

以圆片级铝锗键合后的残余应力为研究对象,在键合环下方和周围制作了一系列形状相同的力敏电阻条,通过比较键合前后力敏电阻条的阻值变化,分析电阻条处残余应力的大小及与工艺相关性。结果表明：键合环内外的压阻变化约为键合环下方压阻变化的3倍。这种方法可以作为晶圆级键合质量的有效在线表征手段之一。     

Die separation and packaging of a surface micromachined piezoresistive pressure sensor

The processing steps required to obtain a useful single medical sensor assembly are discussed, starting from an entire silicon wafer with thousands of surface micromachined sensors. Experiences concerning dicing and packaging of a piezoresistive pressure sensor are described, together with proposals for solutions. Problems with fracture of essential sensor structures are solved by use of a wafer protection tape. Existing solutions for flip–chip bonding and design of substrate for electrical interconnection are pushed to their limits due to the very small size of the novel sensor. As many of the processes can be simplified by an improved MEMS design, critical points related to the design are addressed.     

3D System-on-Chip technologies for More than Moore systems

3D integration is a key solution to the predicted performance problems of future ICs as well as it offers extreme miniaturization and cost-effective fabrication of More than Moore products. Through silicon via (TSV) technologies enable high interconnect performance compared to 3D packaging. At present TSVs are associated with a relatively high fabrication cost, but research world wide strive to bring the cost down to an acceptable level. An example of a 3D System-on-Chip (3D-SOC) technology is to introduce a post backend-of-line TSV process as an optimized technology for heterogeneous system integration. The introduced ICV-SLID process, that combines both TSVs and bonding, enables 3D integration of fabricated devices. Reliability issues related to thermo-mechanical stress caused by the TSV formation and the bonding are considered. 3D-SOC technology choices made to realize a heterogeneous ultra-small IC stack for a wireless tire pressure monitoring system (TPMS) as an automotive application are described.     

Ultra thin ICs and MEMS elements: techniques for wafer thinning,stress-free separation,assembly and interconnection

 Ultra thin chips with a thickness below 30 μm offer low system height, low topography and show enhanced mechanical flexibility. These properties enable diverse use possibilities and new applications. However, advanced wafer thinning, adapted assembly and interconnection methods are required for this technology. A new process scheme is proposed that allows manufacturing of ultra thin fully processed wafers. Secure handling is achieved by means of carrier substrates using reversible adhesive tapes for connection of support and device wafers. Well established backgrinding and etching techniques are used for wafer thinning. To avoid mechanical damage of thin ICs the “Dicing-by-Thinning” (DbyT) concept is introduced to process flow. Best results are obtained when preparing dry etched chip grooves at front side of device wafer and opening these trenches during backside thinning. The new process scheme was also applied to wafers with highly topographic surfaces. Results of 40 μm thin wafers with 15 μm high Nickel bumps are presented. Three different assembly methods are described, interconnection through the thin chip, face down assembly and isoplanar contacting. Received: 6 July 2001/Accepted: 26 February 2002 The authors would like to thank M. Küchler (IZM Chemnitz) for preparing and performing trench etching process and A. Ostmann (IZM Berlin) for performance of nickel bumping process. This paper was presented at the Conference of Micro System Technologies 2001 in March 2001.     

TSV constraints related to temperature excursion, pressure during molding, materials used and handling loads

The current paper focuses on several mechanical aspects of a waferlevel packaging approach using a direct face-to-face Chip-to-Wafer (C2W) bonding of a MEMS device on an ASIC substrate wafer. Requirements of minimized inherent stress from packaging and good decoupling from forces applied in manufacturing and application are discussed with particular attention to the presence of through-silicon vias (TSV) in the substrate wafer. The paper deals with FEM analysis of temperature excursion, pressure during molding, materials used and handling load influence on mechanical stress within the TSV system and on wafer level, which can be large enough to disintegrate the system.     

硅通孔键合硅片预对准边缘信息采集与处理

研究硅通孔即TSV(through-silicon vias)键合硅片的预对准边缘信息采集与处理方法。TSV硅片与标准硅片相比,有减薄、键合不同心、边缘毛刺多、存在崩边;缺口被填充、内有鼓胶、镀铜等工艺特点,使得传统基于线阵CCD一维图像采集与处理预对准方法失败。针对TSV硅片的特点,把线阵CCD配合扫描运动采集的一维原始图像集拼接获得二维图像,应用二维图像处理技术提取边缘信息,硅片整周边缘数据用最小二乘圆拟合算法识别出圆心位置,缺口边缘数据用Hough直线变换识别出缺口两条斜边,其交点定位为缺口位置,从而实现TSV硅片的自动预对准。实际测量表明,该方法预对准重复性定位精度<20um、预对准时间<40s,满足指标需求,为光刻机能够曝光TSV硅片提供有力支持。     

基于圆片级阳极键合封装的高g_n值压阻式微加速度计

设计了一种适合于高gn值压阻式微加速度计圆片级封装的结构,解决了芯片制造工艺过程中电极通道建立、焊盘保护、精确划片等关键技术。采用玻璃—硅—玻璃三层阳极键合的方式进行圆片级封装,较好地解决了芯片密封性、小型化和批量化等生产难题。在4 in生产线上制作的高gn值压阻式微加速度计样品,尺寸仅为1 mm×1 mm×0.8 mm;对传感器进行的校准与抗冲击性能测试,结果表明:样品具备105gn的抗冲击能力、0.15μV/gn/V的灵敏度以及200 kHz的谐振频率。     

Electronically controlled etch-mask for silicon bulk micromachining

Wafers that are to be submitted to anisotropic etching in aqueous KOH are conventionally passivated with a silicon dioxide or nitride layer in which backside windows are etched to define the microstructures. A different method to mask the backside of a silicon wafer for this purpose is presented. The method makes use of the phenomenon that silicon is not etched in KOH when biased above the passivation potential. The mask is defined by applying a set of bias voltages to the front of the wafer instead of patterning a deposited passivation layer at the backside, for which an accurate double-sided alignment is required. The feasibility of the method was demonstrated with the fabrication of membranes and suspended masses of various sizes     

Microrivets for MEMS packaging: concept, fabrication, and strengthtesting

Microriveting is introduced as a novel and alternative joining technique to package MEMS devices. In contrast to the existing methods, mostly surface bonding, the reported technique joins two wafer pieces together by riveting, a mechanical joining means. Advantages include wafer joining at room temperature and low voltage, and relaxed requirements for surface preparation. The microrivets, which hold a cap-base wafer pair together, are formed by filling rivet holes through electroplating. The cap wafer has a recess to house the MEMS devices and also has through-holes to serve as rivet molds. The seed layer on the base wafer becomes the base of the rivet. The process requires only simple mechanical clamping of the wafer pair during riveting, compared with the more involved procedures needed for wafer bonding. Directionality of electroplating in an electric field is what makes this process simple and robust. Strength testing is carried out to evaluate the joining with microrivets. Different modes of rivet failure under different loading conditions are identified and investigated. Effective strength between 7 and 11 MPa was measured under normal loading with nickel microrivets. Joining strengths comparable to conventional wafer bonding processes, ease of fabrication with repeatability, and compatibility with batch fabrication show that microriveting is a feasible technique to join wafers for MEMS packaging, especially when hermetic sealing is not essential     

Design and fabrication of an angular microactuator for magneticdisk drives

Angular electrostatic microactuators suitable for use in a two-stage servo system for magnetic disk drives have been fabricated from molded chemical-vapor-deposited (CVD) polysilicon using the HexSil process. A 2.6-mm-diameter device has been shown to be capable of positioning the read/write elements of a 30% picoslider over a ±1-μm range, with a predicted bandwidth of 2 kHz. The structures are formed by depositing polysilicon via CVD into deep trenches etched into a silicon mold wafer. Upon release, the actuators are assembled onto a target wafer using a solder bond. The solder-bonding process will provide easy integration of mechanical structures with integrated circuits, allowing separate optimization of the circuit and structure fabrication processes. An advantage of HexSil is that once the mold wafer has undergone the initial plasma etching, it may be reused for subsequent polysilicon depositions, amortizing the cost of the deep-trench etching over many structural runs and thereby significantly reducing the cost of finished actuators. Furthermore, 100-μm-high structures may be made from a 3-μm deposition of polysilicon, increasing overall fabrication speed     

纳米铜焊膏烧结互连技术研究现状与展望

纳米铜焊膏在低温烧结后可形成耐高温、高导电导热同质互连结构,该互连结构不仅可避免锡基焊料层和烧结银层服役过程中出现桥接短路和电迁移的可靠性问题,还可解决异质互连结构热膨胀系数不匹配的问题,在集成电路和功率器件封装领域具有重要应用价值。近年来,在铜纳米颗粒稳定性和低温烧结性能方面,纳米铜焊膏烧结互连技术取得了重大研究进展。但与纳米银焊膏烧结互连技术相比,纳米铜焊膏的稳定性、低温烧结性能和可靠性仍有较大提升空间。该文从烧结互连机理、烧结工艺调控、铜纳米颗粒表面改性、纳米铜基复合焊膏、互连可靠性和封装应用方面,阐述了纳米铜焊膏烧结互连技术的最新研究进展,并对后续的技术发展和研究思路进行了展望。     

A simple thermo-compression bonding setup for wire bonding interconnection in pressure sensor silicon chip packaging

In the process of piezo-resistive pressure sensor packaging, a simple thermo-compression bonding setup has been fabricated to achieve the wire bonding interconnection of a silicon chip with printed circuit board. An annealed gold wire is joined onto a pad surface with a needle-like chisel under a force of 0.5?C1.5?N/point. The temperature of the substrate was maintained in the range of 150?C200°C and the temperature of the chisel was fixed at around 150°C during wire bonding operation. The tensile strength of the wire bonding was measured with a bonding tester by the destructive-pulling experiment and was found to be at the average of 132?mN/mm². The microstructure of the bonding point was examined by scanning electron microscopy. The interface of the thermo-compression boning was shown to possess an acceptable level of reliability for a micro-electromechanical system (MEMS)-based device. The results showed that this setup can be easily operated for fabrication and is suitable for fabricating not only low-cost pressure sensors, but also other MEMS devices.     

A simple thermo-compression bonding setup for wire bonding interconnection in pressure sensor silicon chip packaging

In the process of piezo-resistive pressure sensor packaging, a simple thermo-compression bonding setup has been fabricated to achieve the wire bonding interconnection of a silicon chip with printed circuit board. An annealed gold wire is joined onto a pad surface with a needle-like chisel under a force of 0.5–1.5 N/point. The temperature of the substrate was maintained in the range of 150–200°C and the temperature of the chisel was fixed at around 150°C during wire bonding operation. The tensile strength of the wire bonding was measured with a bonding tester by the destructive-pulling experiment and was found to be at the average of 132 mN/mm². The microstructure of the bonding point was examined by scanning electron microscopy. The interface of the thermo-compression boning was shown to possess an acceptable level of reliability for a micro-electromechanical system (MEMS)-based device. The results showed that this setup can be easily operated for fabrication and is suitable for fabricating not only low-cost pressure sensors, but also other MEMS devices.

     

Mechanical and electrical bonding between silicon wafer and glass wafer with etched channels containing metal tracks

In this paper a novel process to bond and, at the same time, to electrically connect a silicon wafer to a glass wafer is presented. It consists of a low temperature anodic bonding process between silicon and glass by using a glass wafer with etched channels in order to contain metal tracks. The glass-to-silicon anodic bonding process at low temperatures (not exceeding 300°C) assures a strong mechanical link (Berthold et al. in Transducers 1999, June:7–10, 1999). The electrical contacts between the metal pads on the backside of a silicon wafer and the metal pads on the glass wafer are achieved by sintering and diffusion of metals due to a kind of thermo compression bonding. This bonding method permits a high vertical control due to a well-controlled etching of the cavity depth and to the thickness precision of both metallization (pads on silicon wafers and metal tracks on glass wafer). This IC-processing compatible approach opens up the way to a new electrical connection concept keeping, at the same time, a strong mechanical bond between glass and silicon wafers for an easier fabrication of a more complex micro-system.     

Fabrication of thermal microbridge actuators and characterization of their electrical and mechanical responses

This study presents thermal silicon microbridge actuators which have been made by a novel fabrication process utilizing dry processes for all critical steps. The fabrication process results in microbridges which are fully oxide covered, with excellent surface quality and dimensional control. The microbridges are made in the device layer of a silicon-on-insulator (SOI) wafer which ensures uniform doping profile and accurate thickness control. The electrical and mechanical responses of the bridges were measured upon rapid heating up to near the melting point of silicon. Up to 12 μm mechanical deflection due to thermal expansion was detected by white light interferometry (WLI) which allowed accurate measurement. Mechanical deflection has previously not been measured for silicon microlamps. Thermal conduction in the air gap between the actuator and the neighbouring solid silicon parts was analysed and shown to be more important than convection or radiation, even at very high operation temperatures.     

Reliability study of hermetic wafer level MEMS packaging with through-wafer interconnect

In this paper, we developed a hermetic wafer level packaging for MEMS devices. Au–Sn eutectic bonding technology in a relatively low temperature is used to achieve hermetic sealing, and the vertical through-hole via filled with electroplated copper for the electrical connection is also used. The MEMS package has the size of 1 mm × 1 mm × 700 μm, and a square loop Au–Sn metallization of 70 μm in width for hermetic sealing. The robustness of the package is confirmed by several tests such as shear strength test, reliability tests, and hermeticity test. The reliability issues of Au–Sn bonding technology, and copper through-wafer interconnection are discussed, and design considerations to improve the reliability are also presented. By applying O₂ plasma ashing and fabrication process optimization, we can achieve the void-free structure within the bonding interface. The mechanical effects of copper through-vias are also investigated numerically and experimentally. Several factors which could induce via hole cracking failure are investigated such as thermal expansion mismatch, via etch profile, copper diffusion phenomenon, and cleaning process. Alternative electroplating process is suggested for preventing Cu diffusion and increasing the adhesion performance of the electroplating process.