Ga_(1-x)Al_xAs/GaAs异质结构二维电子气晶体管(TEGFET)

制备了耗尽型和增强型TEGFET,耗尽TEGFE单栅长1μm,其室温跨导g_m=90mS/mm;双栅栅长均为2μm。g_m=75mS/mm。双栅的结果优于本实验室相同结构与尺寸的离子注入型常规双栅MESFET与高掺杂沟道MIS结构肖特基势垒FET的实验结果。双栅耗尽型器件在77K下跨导增加到1.7倍。双栅增强型的TEGFET在室温0.6V栅偏压下,g_m=63mS/mm,在77K下增加到1.4倍。如器件中出现平行电导时,则器件性能退化,它不但使跨导降低,且随栅编压变化很大。文中讨论了这一现象。     

A stable indium-phosphide diffused junction field-effect transistorwith high gain and low leakage

The fabrication and performance of a JFET which is made by diffusing zinc into an epitaxial channel of indium phosphide grown by MOCVD on a semi-insulating InP(Fe) substrate are presented. The total gate length is 2.4 μm. At 0-V gate bias the transconductance is 140 mS/mm, the gate-source capacitance is 3.0 pF/mm, and the output conductance is less than 0.5 mS/mm. At -2-V gate bias the leakage from gate to source is 4 nA/mm. The drift in drain-source current is less than ±1% after 10⁶ s under continual DC bias     

High-speed and high-power GaInAsP/InP junction field-effecttransistor with submicron gate

Depletion-mode GaInAsP/InP junction field-effect transistors have been fabricated on Fe-doped semi-insulating InP substrates using liquid-phase epitaxial growth techniques. The authors achieved transconductance of 24 mS (160 mS/mm), drain-source saturation current at an on gate bias of 486 mA/mm and current cutoff frequency of 18.8 GHz using a GaInAsP channel layer owing to the gate length reduction     

Self-aligned GaAs gate heterojunction SISFET

A self-aligned GaAs gate heterojunction enhancement-mode SISFET with a layer structure of n+-GaAs/undoped Al0.5Ga0.5As/undoped GaAs is fabricated and shows a high transconductance and a low threshold voltage. The highest transconductance at both room temperature and at 77 K ever reported on a long-channel GaAs gate SISFET, 197 mS/mm and 313 mS/mm, respectively, is obtained.     

Self-aligned shallow junction MJFET (metal junction FET) for higherturn-on and breakdown voltages

Simple self-aligned p⁺⁺-gate formation technology for a junction field-effect transistor (JFET) using elemental shallow Zn diffusion from patterned Au/Zn gate metal is reported. This diffusion technology makes it possible to control a very shallow p⁺⁺-layer less than 50 nm. The metal junction FET (MJFET) shows about 0.3 V higher gate turn-on voltage in forward bias and much larger reverse breakdown voltage than the conventional Al-gate MESFET with similar transconductances, typically 200 mS/mm for 1.5-μm gate length quasi-enhancement, and 90 mS/mm for 4-μm gate length deep depletion devices     

Quantum-well p-channel AlGaAs/InGaAs/GaAs heterostructureinsulated-gate field-effect transistors with very high transconductance

Quantum-well p-channel pseudomorphic AlGaAs/InGaAs/GaAs heterostructure insulated-gate field-effect transistors with enhanced hole mobility are described. The devices exhibit room-temperature transconductance, transconductance parameter, and maximum drain current as high as 113 mS/mm, 305 mS/V/mm, and 94 mA/mm, respectively, in 0.8-μm-gate devices. Transconductance, transconductance parameter, and maximum drain current as high as 175 mS/mm, 800 mS/V/mm, and 180 mA/mm, respectively were obtained in 1-μm p-channel devices at 77 K. From the device data hole field-effect mobilities of 860 cm²/V-s at 300 K and 2815 cm²/V-s at 77 K have been deduced. The gate current causes the transconductance to drop (and even to change sign) at large voltage swings. Further improvement of the device characteristics may be obtained by minimizing the gate current. To this end, a type of device structure called the dipole heterostructure insulated-gate field-effect transistor is proposed     

Experimental 0.1 μm p-channel MOSFET withp+-polysilicon gate on 35 Å gate oxide

Very-high-transconductance 0.1 μm surface-channel pMOSFET devices are fabricated with p⁺-poly gate on 35 Å-thick gate oxide. A 600 Å-deep p⁺ source-drain extension is used with self-aligned TiSi₂ to achieve low series resistance. The saturation transconductances, 400 mS/mm at 300 K and 500 mS/mm at 77 K, are the highest reported to date for pMOSFET devices     

Semiconductor-gated InGaAs/InAlAs heterostructure transistors (SISFET's)

We have successfully fabricated FET's with In0.53Ga0.47As channels, lattice-matched In0.52Al0.48As gate barriers, and n+ In0.53- Ga0.47As gates. For a barrier thickness of 600 Å and a gate length of 1.7 µm, the maximum transconductance is 250 mS/mm at T = 300 K. From gate capacitance measurements, the cutoff frequency is inferred to be ft= 15 GHz for this gate length. Self-aligned source and drain implants have been used to permit nonalloyed ohmic contacts with a characteristic resistance of 0.1 Ω.mm. The transconductance remains above 210 mS/mm for forward gate bias up to +1.0 V, confirming the usefulness of this gate structure for enhancement-mode devices.     

High-performance InGaAs junction field-effect transistor with P/Beco-implanted gate

InGaAs junction field-effect transistors (JFETs) are fabricated in metalorganic chemical-vapor-deposition (MOCVD)-grown n-InGaAs and semi-insulating Fe:InP layers on n⁺-InP substrate with a P/Be co-implanted p⁺ self-aligned gate. The device exhibits a transconductance of 245 mS/mm (intrinsic transconductance of 275 mS/mm) at zero gate bias and good pinch-off behavior for a gate length of 0.5 μm. The effective electron velocity is deduced to be 2.8×10⁷ cm/s, equal to the theoretical prediction     

Integrated enhancement- and depletion-mode FET's inmodulation-doped Si/SiGe heterostructures

We present results of enhancement and depletion mode transistors fabricated on the same layer structure of Si/SiGe, without using gate recess. The current in the enhancement mode device is controlled by a p-n junction, while that of the depletion-mode device is controlled by a Schottky barrier. A peak transconductance of 327 mS/mm and 417 mS/mm has been achieved in 0.5-μm gate length depletion and enhancement-mode transistors, respectively     

Realization of n-channel and p-channel high-mobility (Al,GA)As/GaAs heterostructure insulating gate FET's on a planar wafer surface

Self-aligned gate by ion implantation n-channel and p-channel high-mobility (Al,Ga)As/GaAs heterostructure insulated-gate field-effect transistors (HIGFET's) have been fabricated on the same planar wafer surface for the first time. Enhancement-mode n-channel (Al,Ga)As/GaAs HIGFET's have demonstrated extrinsic transconductances of 218 mS/mm at room temperature and 385 mS/mm at 77 K. Enhancement-mode p-channel (Al,Ga)As/GaAs HIGFET's have demonstrated extrinsic transconductances of 28 mS/mm at room temperature and 59 mS/mm at 77 K. There are the highest transconductance values ever reported on a p-channel FET device.     

GaAsxSb1-x/InyAl1-yAsp-channel heterostructure FETs with high transconductance and low gateleakage current

The first known p-channel GaAs_xSb_1-x/In_yAl_1-yAs HFETs on InP are reported. The devices, using a strained-layer GaAs_xSb_1-x channel, have achieved extrinsic transconductances of 40 mS/mm and intrinsic transconductances of 100 mS/mm. In addition to high transconductance, the devices exhibit excellent pinchoff and demonstrate a record gate turn-on voltage of -3 V as a result of extremely low gate leakage currents, making them exceptional candidates for complementary technologies. These outstanding gate characteristics are attributed to the valence band-edge discontinuity of 0.64 eV     

Monolithic integration of Si MOSFET's and GaAs MESFET's

Integration of Si MOSFET's and GaAs MESFET's on a monolithic GaAs/Si (MGS) substrate has been demonstrated. The GaAs MESFET's have transconductance of 150 mS/mm for a gate length of 1 µm, and the Si MOSFET's have transconductance of 19 mS/mm for a gate length of 5 µm and an oxide thickness of 800 Å. These characteristics are comparable to those for devices fabricated on separate GaAs and Si substrates.     

GaAs-MISFETs with insulating gate films formed by direct oxidation and by oxinitridation of recessed GaAs surfaces

Direct oxidation by an ultraviolet (UV) and ozone process and oxinitridation (plasma nitridation after oxidation) of GaAs surfaces were used to form nanometer-scale gate insulating layers for depletion-type recessed gate GaAs-MISFETs. The drain current-drain voltage characteristics of the oxide gate devices exhibit lower transconductance (max. 40 mS/mm), lower breakdown voltage and smaller gate capacitance than the oxinitrided gate devices. The presence of hysteresis in the oxide gate devices is also apparent. The maximum transconductance of the oxinitrided gate devices is 110 mS/mm and they have a sharper pinch-off, compared to the oxide gate devices. In addition, no hysteresis is observed in their current voltage curves. The current gain cutoff frequency of 1.4 /spl mu/m gate-length FETs for both types is 6 GHz. These results correspond well with results obtained from characterization of these insulating films.     

InAlAs/InGaAs/InP HEMTs with high breakdown voltages using double-recess gate process

The DC and RF performance of InAlAs/InGaAs/InP HEMTs fabricated using a double-recess gate process are reported. A gate-drain breakdown voltage as high as 16 V was observed. The HEMTs also exhibited a high source-drain breakdown voltage near pinchoff of 16 V and a low RF output conductance of 6 mS/mm. For a 1.4 mu m gate length, an intrinsic transconductance of 560 mS/mm and f/sub T/ and f/sub max/ values of 16 and 40 GHz, respectively, were achieved.<>     

Modification of transconductance characteristics for ion-implanted GaAs/AlGaAs heterojunction MESFETs

Inverted GaAs/AlGaAs heterostructures grown by MOCVD have been used to fabricate conventional ion-implanted MESFETs. Two types of GaAs/AlGaAs heterojunctions are studied. One type has a compositionally graded AlGaAs layer which provides a built-in field and corresponding quantum well at the heterointerface. The other type has a constant-composition AlGaAs layer. 0.5 mu m gate devices fabricated using the ungraded AlGaAs layer show a maximum extrinsic transconductance G/sub m/ of 280 mS/mm and a small G/sub m/ variation over a gate voltage range of 1.5 V. In comparison, devices fabricated using the graded AlGaAs layer exhibit higher transconductance over all the gate voltages and an enhancement of G/sub m/ up to 420 mS/mm at low gate bias.<>     

1-μm Enhancement Mode GaAs N-Channel MOSFETs With Transconductance Exceeding 250 mS/mm

In this letter, 1-mum GaAs-based enhancement-mode n-channel devices with channel mobility of 5500 cm²/Vmiddots and g _m exceeding 250 mS/mm have been fabricated. The measured device parameters including threshold voltage V_th, maximum extrinsic transconductance g_m, saturation current I_dss , on-resistance R_on, and gate current are 0.11 V, 254 mS/mm, 380 mA/mm, 4.5 Omegamiddotmm, and < 56 pA for a first wafer and 0.08 V, 229 mS/mm, 443 mA/mm, 4.5 Omegamiddotmm, and < 90 pA for a second wafer, respectively. With an intrinsic transconductance g_mi of 434 mS/mm, GaAs enhancement-mode MOSFETs have reached expected intrinsic device performance     

Inverted GaAs/AlGaAs modulation-doped field-effect transistors with extremely high transconductances

Inverted GaAs/AsGaAs MODFET's with transconductances as high as 1810 mS/mm at 77 K and 1180 mS/mm at 300 K are fabricated using a self-aligned process. The devices have the gate-heterojunction interface spacing of only 100 Å, and the observed values of the transconductance are limited primarily by the source series resistance and by the gate current. The MODFET characteristics are interpreted using the charge control velocity saturation model which takes into account the gate current. The obtained results show a great potential of inverted MODFET's for ultrahigh-speed applications.     

Improved Stability of High-Performance ZnO/ZnMgO Hetero-MISFETs

Improved performance and stability was demonstrated for ZnO/ZnMgO hetero-MISFETs. The MIS gate structures that were formed using either a 50-nm-thick Al₂O₃ or HfO₂ gate dielectric layer were examined by observation of the transfer characteristic hysteresis. A significantly reduced hysteresis of less than 0.1 V was obtained for HfO₂ as compared to that for the Al₂O₃ gate dielectric. By reducing the access resistance, the 1-mum gate devices showed improved transconductance values, as high as 54 mS/mm for Al₂O₃ and 71 mS/mm for HfO₂, which are the highest values ever reported for ZnO-based FETs.     

Depletion-mode GaAs SISFET's by selective ion implantation

Silicon donors have been implanted through the gate and into the (Al,Ga)As insulator of a GaAs SISFET structure in order to produce a negative shift in the device threshold voltage in selective areas of the wafer. The depletion-mode devices fabricated in this manner have controllable threshold voltage, high transconductance (350 mS/mm at 300 K and 380 mS/mm at 77 K for 1-µm gate-length devices), and low gate leakage characteristics. Such devices are suitable for enhance-deplete GaAs SISFET logic circuits.