Review of advanced FPGA architectures and technologies

Field Programmable Gate Array （FPGA） is an efficient reconfigurable integrated circuit platform and has become a core signal processing mieroehip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system inte- gration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, intercon- nects, and embedded resources. Moreover, some important emerging design issues of FPGA archi- tectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development.     

基于分布式算法的高阶FIR滤波器及其FPGA实现

随着FPGA技术的稳步提高,FPGA替代其他技术用于实现高速信号处理已经变得切实可行。针对高阶FIR滤波器十分消耗FPGA硬件资源的问题,提出了一种采用基于位级联的多查找表分布式算法,并以一个32阶8位低通FIR滤波器为例,验证了所提出的方法。仿真结果表明,采用这种方法大大减少了FPGA硬件资源的耗费。     

Configurable logic for digital communications: some signalprocessing perspectives

For the past two decades software programmable digital signal processors and ASICs have provided hardware solutions for signal processing system designers. A new option has become available: field programmable gate arrays. FPGA-based DSP platforms allow the designer to realize a data path that exactly matches the required processing, while at the same time maintaining the flexibility of a software approach. This article presents an overview of some FPGA DSP applications. Several filter designs are presented, and the use of CORDIC arithmetic for constructing an FPGA carrier recovery loop is outlined. In addition to presenting design examples that can be realized using present-generation devices and tools, we take a brief look at how the dynamic reconfiguration aspect of certain FPGAs could be exploited in future-generation communication technologies     

Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies

The design of high performance, high precision, real-time digital signal processing (DSP) systems, such as those associated with wavelet signal processing, is a challenging problem. This paper reports on the innovative use of the residue number system (RNS) for implementing high-end wavelet filter banks. The disclosed system uses an enhanced index-transformation defined over Galois fields to efficiently support different wavelet filter instantiations without adding any extra cost or additional look-up tables (LUT). A selection of a small wordwidth modulus set are the keys for attaining low-complexity and high-throughput. An exhaustive comparison against existing two's complement (2C) designs for different custom IC technologies was carried out. Results reveal a performance improvement of up to 100% for high-precision RNS-based systems. These structures demonstrated to be well suited for field programmable logic (FPL) assimilation as well as for CBIC (cell-based integrated circuit) technologies.     

A new FPGA architecture suitable for DSP applications

A new FPGA architecture suitable for digital signal processing applications is presented.DSP modules can be inserted into FPGA conveniently with the proposed architecture,which is much faster when used in the field of digital signal processing compared with traditional FPGAs.An advanced 2-level MUX(multiplexer) is also proposed.With the added SLEEP MODE PASS to traditional 2-level MUX,static leakage is reduced.Furthermore, buffers are inserted at early returns of long lines.With this kind of buffer,the delay of the long line is improved by 9.8%while the area increases by 4.37%.The layout of this architecture has been taped out in standard 0.13μm CMOS technology successfully.The die size is 6.3×4.5 mm~2 with the QFP208 package.Test results show that performances of presented classical DSP cases are improved by 28.6%-302%compared with traditional FPGAs.     

FPGA-based digit-serial CSD FIR filter for image signal format conversion

This paper proposes the FPGA implementation of the digit-serial Canonical Signed-Digit (CSD) coefficient FIR filters which can be used as format conversion filters in place of the ones employed for the MPEG2 TM 5 (test model 5). Canonical representation of a signed digit (CSD) is a method used to reduce cost by representing a signed number using the least amount of non-zero digits, thereby reducing the number of multiply operations. As Field Programmable Gate Arrays (FPGAs) have grown in capacity, improved in performance, and decreased in cost, they are becoming a viable solution for performing computationally intensive tasks, with the ability to tackle applications formerly reserved for custom chips and programmable digital signal processing (DSP) devices. A digit-serial CSD FIR filter design is realized and practical design guidelines are provided using FPGAs. An analysis of the performance comparison of bit-serial, serial distributed arithmetic, and digit-serial CSD FIR filters on a Xilinx XC4000XL-series FPGA is described. The results show that the proposed digit-serial CSD FIR filter is compact and an efficient implementation of real-time DSP applications on FPGAs.     

基于CPCI的红外图像实时处理系统

提出了一种基于CPCI总线、采用FPGA DSP架构的高性能红外图像信号实时处理系统。在该系统中,FPGA芯片XC2VP20-5FG676负责控制采样并作为红外图像信号的预处理单元,DSP芯片TMS320C6416T构成高速处理单元,PCI接口芯片PCI9054实现标准的32位PCI总线接口,从而构成了一个可用于红外信号采集处理的通用标准化硬件平台。该方案充分结合了不同处理器件的优点,具有处理能力强、数据传输速度快、接口可靠方便和编程灵活等特点。实验证明,系统能够满足红外图像实时采集处理的要求。     

基于DSP FPGA GPP-CPU的软件无线电信号处理平台的硬件设计

DSP FPGA构成的数字硬件系统以其强通用性、灵活性、高处理速度而使其在诸多领域有广泛的应用;GPP(General Purpose Processor)功能强大,不仅可以做复杂的控制算法,还具有强大的数字信号处理能力。本文介绍了一种基于DSP FPGA GPP-CPU的软件无线电信号处理通用硬件平台的设计。     

基于DSP和CPLD的金属磁记忆检测仪设计

设计了一种以DSP+CPLD为控制核心的高性能金属磁记忆检测仪,用以快速检测铁磁材料的漏磁信号,判断材料应力集中区域。文中简述了磁记忆检测仪的主要电路及其工作原理,重点介绍了系统的硬件和软件设计。该检测仪利用DSP快速的运算处理能力,以及CPLD高效的逻辑控制和时序协调功能,保证了系统的快速信号采样、高速数据处理和实时信号显示。     

The TaPaSCo Open-Source Toolflow

The integration of FPGA-based accelerators into a complete heterogeneous system is a challenging task faced by many researchers and engineers, especially now that FPGAs enjoy increasing popularity as implementation platforms for efficient, application-specific accelerators for domains such as signal processing, machine learning and intelligent storage. To lighten the burden of system integration from the developers of accelerators, the open-source TaPaSCo framework presented in this work provides an automated toolflow for the construction of heterogeneous many-core architectures from custom processing elements, and a simple, uniform programming interface to utilize spatially distributed, parallel computation on FPGAs. TaPaSCo aims to increase the scalability and portability of FPGA designs through automated design space exploration, greatly simplifying the scaling of hardware designs and facilitating iterative growth and portability across FPGA devices and families. This work describes TaPaSCo with its primary design abstractions and shows how TaPaSCo addresses portability and extensibility of FPGA hardware designs for systems-on-chip. A study of successful projects using TaPaSCo shows its versatility and can serve as inspiration and reference for future users, with more details on the usage of TaPaSCo presented in an in-depth case study and a short overview of the workflow.

     

基于CSD算法的高阶FIR滤波器优化设计

在通信或雷达领域的高速实时信号处理中,通常包含大量的高速高阶FIR滤波器的设计。例如在雷达信号处理中,要进行数字正交采样和脉冲压缩器的设计,要求滤波器速率高,阶数大,运算量非常大。若使用DSP芯片则需多片处理完成,使得系统的工作延迟长、成本高、功耗大、调试困难。该文根据CSD（Canonic Signed—Digital）算法的思想,实现了高阶高速FIR滤波器的优化设计。该算法可显著降低算法的运算量,可用可编程逻辑器件迅速快捷地完成系统的硬件设计。文中举例用Altera公司的FPGA来实现数字正交采样和脉冲压缩滤波器算法优化,进行了实验验证,最后给出了结果比较和分析,证明这对基于FPGA的高阶FIR滤波器的设计有实际意义。     

基于EMIF接口的图像处理系统设计

设计一种以DSP为核心,FPGA协助数据采集、传输的图像处理平台。DSP运行复杂图像处理算法,通过EMIF接口和FPGA进行高速数据传输。FPGA对EMIF接口进行扩展,将图像传感器、SDRAM存储器、USB接口等统一到EMIF接口,提高系统的集成度和灵活性,实现DSP与FPGA、外设之间数据准确、高效、可靠的传输。实验表明,该系统满足实时性设计需求,易于扩展和升级,具备较强的通用性。     

基于Zynq7020的组合导航处理平台软硬件系统的设计与实现

提出一种基于Zynq处理平台的组合导航系统设计及实现方案,Zynq7020作为新近发展的可扩展处理平台,集成了大规模可编程逻辑器件(FPGA)、低功耗高性能先进ARM处理器,两者通过内部总线互联与通信,满足高集成度、高性能数据处理的应用需求.基于Zynq处理器设计并实现组合导航处理平台,替代原有的FPGA+DSP+ARM导航解算模式,单芯片完成IMU信号采集,信号处理和导航解算等功能,降低整机设计的复杂度和成本.     

FPGA器件设计技术发展综述

现场可编程门阵列(Field Programmable Gate Array,FPGA)作为一种可编程逻辑器件,在短短二十多年里从电子设计的外围器件逐渐演变为数字系统的核心,在计算机硬件、通信、航空航天和汽车电子等诸多领域有着广泛的应用。伴随着半导体工艺技术的进步,FPGA器件的设计技术取得了飞跃性突破。该文在回顾FPGA发展历史的同时,对目前主流FPGA器件的前沿技术进行总结,并对新一代FPGA的发展前景进行展望。     

Guest Editorial: Special Issue on Signal Processing Systems: Part I

The design of high performance, high precision, real-time digital signal processing (DSP) systems, such as those associated with wavelet signal processing, is a challenging problem. This paper reports on the innovative use of the residue number system (RNS) for implementing high-end wavelet filter banks. The disclosed system uses an enhanced index-transformation defined over Galois fields to efficiently support different wavelet filter instantiations without adding any extra cost or additional look-up tables (LUT). A selection of a small wordwidth modulus set are the keys for attaining low-complexity and high-throughput. An exhaustive comparison against existing two's complement (2C) designs for different custom IC technologies was carried out. Results reveal a performance improvement of up to 100% for high-precision RNS-based systems. These structures demonstrated to be well suited for field programmable logic (FPL) assimilation as well as for CBIC (cell-based integrated circuit) technologies.

     

Estimating Power for FPGAs Based on Signal Probability Theory

Power dissipation has become one of the key optimization conditions in logic design on field programmable gate arrays (FPGAs), thus the power estimation is necessary for logic design optimization. Nowadays, signal activity data created by logic simulation based on test vectors is essential to be used to determine the toggle rate of each signals and blocks in power estimation tools provided by field programmable gate array (FPGA) electronic design automation (EDA) tools. The accuracy of power estimation highly depends on the quality of test vectors, especially, pattern coverage. As probability distribution can describe the uncertainty signals, this work provides an algorithm which can estimate FPGAs power more effectively and accurately by using signal probability distribution rather than test vectors.     

雷达视频积累算法在FPGA上的实现

随着超大规模集成电路技术尤其是FPGA技术和数字信号处理技术的迅猛发展,为雷达信号处理技术的工程实现提供了新思路和新方法。采用FPGA技术对雷达的视频信号进行视频积累,克服了DSP处理速度有限、实时性差和ASIC器件灵活性差的问题。以自行研制的雷达信号处理PCI卡为平台,详细介绍了雷达视频积累算法在FPGA芯片上实现的原理和过程,并结合仿真结果说明了利用FPGA进行视频积累的优势,为雷达视频积累的工程实现提出了一条新思路。     

Multidimensional DSP Core Synthesis for FPGA

Current rapid synthesis approaches for reusable dedicated hardware components (cores) for digital signal processing systems are ineffective since they fail to capture and exploit the manner in which the resulting components are used as part of a heterogeneous system. This leads to counter-productive core redesign for each use of the core. This paper presents a solution to this issue which combines a novel but intuitive system modeling technique and associated core generation and integration methodology which generates reuable core architectures which may be optimised via algorithm level transformations. For an example design problem, these provide an effective rapid core synthesis and implementation exploration flow which allows a factor 3.9 throughput increase with no extra hardware expense. John McAllister received a first honours B.Eng degree in Electrical and Electronic Engineering and the degree of PhD from Queen’s University Belfast, UK in 2001 and 2004 respectively.From October 2004 to July 2005 he was a Postdoctoral Research Assistant in the Programmable Systems Laboratory in the System on Chip research group in the Institute for Electronics, Communication and Information Technology (ECIT) at Queen’s University Belfast.In July 2005 he was appointed to a lectureship in SoC technology in the International Centre for System-on-Chip and Advanced Microwireless (SoCAM) project at ECIT. Roger Woods received the degree of B.Sc with Honours in Electrical and Electronic Engineering and degree of Ph.D. from the Queen’s University of Belfast, UK in 1985 and 1990 respectively. From 2003, he has been a Professor at the same university and leads the programmable systems and networks laboratory there. His main research interests are programmable hardware systems using FPGAs, design tools for heterogeneous platforms and low power VLSI. He has published over 120 papers in the area of VLSI and DSP, holds two patents and serves on numerous technical program committees including Workshop on Signal Processing Systems, Field Programmable Logic and Field Programmable Technology. He is a member the IEEE Signal Processing Society Technical Committee for the Design and Implementation of Signal Processing Systems and chair of the IEE Professional Network on Microelectronics and Embedded Systems. Richard Walke received his Ph.D. from Warwick University in 1998 for work on arithmetic, architectures and implementations of adaptive weight calculation in ASIC. Subsequently he worked on the implementation of a range of DSP algorithms in FPGA, specialising in floating-point arithmetic, digital receivers and adaptive beamformers on FPGA. In recent years he has lead work to address the design of heterogeneous systems employing both processor and FPGA. Last year he moved to Xilinx, and is now responsible for the development of their floating-point IP solution. Darren Reilly received first honours B.Eng. Degree in Electronic and Software Engineering from the Queen’s University Belfast in 2002. He is currently pursuing a Ph.D. in Queen’s University Belfast due to finish in September 2005. His research interests lie in the rapid development of efficient architectures for FPGA as part of a system level design flow.