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1.
A monolithic operational amplifier is presented which optimizes voltage noise both in the audio frequency band, and in the low frequency instrumentation range. In addition, the design demonstrates that the requirements for low noise do not necessitate compromising the specifications in other respects. Techniques are set forth for combining low noise with high-speed and precision performance for the first time in a monolithic amplifier. Achieved results are: 3 nV//spl radic/Hz white noise, 80 nV/SUB p-p/ noise from 0.1 to 10 Hz, 17 V//spl mu/s slew rate, 63 MHz gain-bandwidth product, 10 /spl mu/V offset voltage, 0.2 /spl mu/V//spl deg/C drift with temperature, 0.2 /spl mu/V/month drift with time, and a voltage gain of two million.  相似文献   

2.
A single cell supply (operable down to 1.2 V) micropower operational amplifier using compatible low pinchoff voltage JFET's (V/SUB p/=0.4 V) in conjunction with standard bipolar technology has been developed. The subvolt pinchoff JFET's have proved useful in the common-mode feedback-assisted biasing of a simple p-n-p input stage to permit single supply operation, the design of a low-voltage high-performance current mirror and a differential to single-ended converter. The amplifier exhibits excellent ac performance (unity gain slew rate=0.25 V//spl mu/s, unity gain bandwidth=850 kHz) with low power dissipation (245 /spl mu/W).  相似文献   

3.
The realization of a commercially viable, general-purpose quad CMOS amplifier is presented, along with discussions of the tradeoffs involved in such a design. The amplifier features an output swing that extends to either supply rail, together with an input common-mode range that includes ground. The device is especially well suited for single-supply operation and is fully specified for operation from 5 to 15 V over a temperature range of -55 to +125/spl deg/C. In the areas of input offset voltage, offset voltage drift, input noise voltage, voltage gain, and load driving capability, this implementation offers performance that equals or exceeds that of popular general-purpose quads or bipolar of Bi-FET construction. On a 5-V supply the typical V/SUB os/ is 1 Mv, V/SUB os/ drift is 1.3 /spl mu/V//spl deg/C, 1-kHz noise is 36 nV//spl radic/Hz, and gain is one million into a 600-/spl Omega/ load. This device achieves its performance through circuit design and layout techniques as opposed to special analog CMOS processing, thus lending itself to use on system chips built with digital CMOS technology.  相似文献   

4.
The design of a precision general-purpose monolithic analog multiplier-divider based on the principle of the variable transconductance of bipolar transistors is described. The device has two new aspects: first, an eight-transistor multiplier-divider core, and second, an improvement in the accuracy and high-frequency behavior of the input and output circuits having monolithic conversion resistors. The transfer function /spl nu//SUB w/=/spl nu//SUB x//spl nu//SUB y///spl nu//SUB z/ is only dependent on external voltages. An advantage of the multiplier-divider over a multiplier with a fixed internal voltage reference is that the external signal voltages can be accurately related to the relevant reference voltage. Moreover, the additional divider input enlarges the application field. The maximum signal voltages are /spl plusmn/10 V. The untrimmed inaccuracy is typically 2 percent. The nonlinearity is /spl plusmn/0.1 percent. The bandwidth is 6.5 MHz, and the slew rate is 50 V//spl mu/s.  相似文献   

5.
A single-chip (67/spl times/90 mil) integrated-circuit operational amplifier using thin-film resistors and super-gain transistors has been designed to achieve dc follower accuracies of 0.001 percent with 100-k/spl Omega/ source resistance. The circuit achieves gains of 140 dB using thermally balanced layout designs for both input and output stages, nulled drifts of 0.3 /spl mu/V//spl deg/C, and offset currents well under 1 nA. All other dc specifications including power-supply variation error (PSRR), common-mode gain error (CMRR), etc., are in the 1-10 ppm error range; and a procedure is given by which long-term drifts of less than 10 /spl mu/V/month can be assured. AC performance is comparable to general-purpose integrated-circuit operational amplifiers, i.e., f/SUB t/=300 kHz and slew rate of 1.2 V//spl mu/s at gain of ten. The circuit is externally compensated for unity gain with a single 390-pF capacitor and is fully input and output protected.  相似文献   

6.
A fully integrated MOSFET amplifier with very low drift has been built using standard technology. Input offset voltages as low as 5 /spl mu/V and drift values of this offset voltage less than 0.05 /spl mu/V//spl deg/C are measured.  相似文献   

7.
Describes a high speed 16K molybdenum gate (Mo-gate) dynamic MOS RAM using a single transistor cell. New circuit technologies, including a capacitive-coupled sense-refresh amplifier and a dummy sense circuit, enable the achievement of high speed performance in combination with reduced propagation delay in the molybdenum word line due to the low resistivity. The n-channel Mo-gate process was established by developing an evaporation apparatus and by an improved heat treatment to reduce surface charge density. Ultraviolet photolithography for 2 /spl mu/m patterns and HCl oxidation for 400 /spl Aring/ thick gate oxide are used. The 16K word/spl times/1 bit device is fabricated on a 3.2 mm/spl times/4.0 mm chip. Cell size is 16 /spl mu/m/spl times/16 /spl mu/m Access time is less than 65 ns at V/SUB DD/=7 V and V/SUB BB/=-2 V. Power dissipation is 210 mW at 170 ns read-modify-write (RMW) cycle.  相似文献   

8.
A design procedure is evolved based on emitter-base voltage V/SUB EB/ and collector-base voltage V/SUB CB/ as stability parameters with the aim of achieving a gain stabilized transistor amplifier against temperature variations. Silicon transistors have been operated with a fairly stabilized gain in the temperature range from -15/spl deg/ to 270/spl deg/C. The voltage and power gains of this amplifier are found to be reasonably stable against unit to unit replacements. The circuits designed according to this approach are particularly suited for operation of long duration at elevated temperatures. The role of the leakage currents in affecting the operation of a several hour duration at elevated temperatures is investigated experimentally and it is found that the low I/SUB CB0/ units are better suited for such an operation. Further experimentations include the study of the gain stability characteristics of the amplifiers using Darlington pairs, CE-CE tandem connections, two stage RC-coupled amplifier, and the different amplifier.  相似文献   

9.
Describes a 256K molybdenum-polysilicon (Mo-poly) gate dynamic MOS RAM using a single transistor cell. Circuit technologies, including a capacitive-coupled sense-refresh amplifier and a redundant circuitry, enable the achievement of high performance in combination with Mo-poly technology. Electron-beam direct writing and dry etching technologies are fully utilized to make 1 /spl mu/m accurate patterns. The 256K word/spl times/1 bit device is fabricated on a 5.83 mm/spl times/5.90 mm chip. Cell size is 8.05 /spl mu/m/spl times/8.60 /spl mu/m. The additional 4K spare cells and the associated circuits, in which newly developed electrically programmable elements are used, occupy less than 10 percent of the whole chip area. The measured access time is 160 ns under V/SUB DD/=5 V condition.  相似文献   

10.
It is shown that in any kind of field-effect transistor structure, the usual gradual channel approximation solutions developed for v=/spl mu//SUB 0/E also hold in a slightly modified form for v=/spl mu//SUB 0/E/|1+(/spl mu//SUB 0/E/v/SUB s/)| which gives a good approximation to the velocity field relationship in silicon FETs.  相似文献   

11.
Isolated vertical n-p-n transistors were fabricated by a modified 5-/spl mu/m n-well CMOS process. The modification included a decrease in the p/SUP +/ source and drain implant dose and an increase in the final anneal time, but no extra processing steps of masks were required. The n-p-n transistors had generally good characteristics, with H/SUB FE//spl ap/600 and BV/SUB CEO//spl ap/40 V, while the MOS characteristics were unchanged.  相似文献   

12.
The high frequency (HF) behavior of the switched-capacitor (SC) LDI ladder filter is studied. This study shows that using low sampling frequency with respect to the cutoff frequency reduces the HF error due to the reduction in amplifier gain. Design techniques are also given for the HF SC filters, such as double-sampling scheme, a low sampling frequency with an exact synthesis algorithm, as well as a fast-settling folded-cascode amplifier. These techniques are applied to an experimental fifth-order elliptic SC filter fabricated in a 2-/spl mu/m CMOS technology. The experimental results show that a 3.6-MHz cutoff frequency is attained. All the capacitors are scaled down in order to reduce the setting time of the amplifiers. The active area of the filter is 0.9 mm/SUP 2/. The F/SUB sampling//F/SUB cutoff/ is only 5. The circuit operates from /spl plusmn/5 V and typically dissipates 80 mW when sampled at 18 MHz.  相似文献   

13.
The potential of the metal-semiconductor field-effect transistor (MESFET) as a device for a dc-stable fixed-address memory-cell array is described. The implementation of dc-coupled circuits with `normally off' MESFET's having 1-/spl mu/m gate lengths yields several inherent advantages: high packing density, low power dissipation, low-power-delay time product, and low number of masking steps for transistors, diodes, and resistors. To demonstrate these advantages a fixed-address memory array with dc-stable cells has been chosen. The integrated cell area is 2.6 mil. For a supply voltage V/SUB s/=0.6 V, a standby power dissipation per cell of 5 /spl mu/W has been achieved. The cell switches within 4 ns. The differential sense current in the digit lines is /spl Delta/I/SUB s/=6 /spl mu/A.  相似文献   

14.
An operational amplifier capable of operating with power supplies up to /spl plusmn/40 V is discussed. The device exhibits output voltage and input common mode swings to within a few volts of either power supply, has an input offset current of 1 nA, a slew rate of 2 V//spl mu/s, and is internally compensated. This paper describes special circuit and device techniques used to reliably fabricated this amplifier with essentially standard monolithic diffused technology.  相似文献   

15.
A 1M word/spl times/1-bit/256K word/spl times/4-bit CMOS DRAM with a test mode is described. The use of an improved sense amplifier for the half-V/SUB CC/ sensing scheme and a novel half-V/SUB CC/ voltage generator have yielded a 56-ns row access time and a 50-/spl mu/A standby current at typical conditions. High /spl alpha/-particle immunity has been achieved by optimizing the impurity profile under the bit line, based on a triple-layer polysilicon n-well CMOS technology. The RAM, measuring 4.4/spl times/12.32 mm/SUP 2/, is fit to standard 300-mil plastic packages.  相似文献   

16.
This work presents a micro-power low-offset CMOS instrumentation amplifier integrated circuit with a large operating range for biomedical system applications. The equivalent input offset voltage is improved using a new circuit technique of offset cancellation that involves a two-phase clocking scheme with a frequency of 20 kHz. Channel charge injection is cancelled by the symmetrical circuit topology. With the wide-swing cascode bias circuit design, this amplifier realizes a very high power-supply rejection ratio (PSRR), and can be operated at single supply voltage in the range between 2.5-7.5 V. It was fabricated using 0.5-/spl mu/m double-poly double-metal n-well CMOS technology, and occupies a die area of 0.2 mm/sup 2/. This amplifier achieves a 160-/spl mu/V typical input offset voltage, 0.05% gain linearity, greater than 102-dB PSRR, an input-referred rms noise voltage of 45 /spl mu/V, and a current consumption of 61 /spl mu/A at a low supply voltage of 2.5 V. Experimental results indicate that the proposed amplifier can process the input electrocardiogram signal of a patient monitoring system and other portable biomedical devices.  相似文献   

17.
A very high precision 500-nA CMOS floating-gate analog voltage reference   总被引:2,自引:0,他引:2  
A floating gate with stored charge technique has been used to implement a precision voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate analog voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.  相似文献   

18.
A switched-capacitor instrumentation amplifier which uses correlated-double sampling to reduce the amplifier offset is discussed. Additional offset caused by clock-related charge injection is cancelled by a symmetrical differential circuit topology and a three-phase clocking scheme. An experimental low-power test cell has been integrated, showing 100 /spl mu/V equivalent offset voltage and input noise equal to 270 /spl mu/V. For a fixed gain equal to 10- and 9-kHz sampling frequency, the power dissipation is 36 /spl mu/W (power supply: 5 V); the circuit measures only 0.2 mm/SUP 2/.  相似文献   

19.
A DC model useful for I/SUP 2/L upward current gain (/spl beta//SUB /spl mu//) design is described. An expression for /spl beta//SUB /spl mu// is obtained in terms of model parameters which are related to device morphology. Design parameters are identified for a standard bipolar technology and a minimum geometry cell.  相似文献   

20.
A 64-kbit dynamic MOS RAM is developed by using 2 /spl mu/m rule VLSI fabrication technology and low power circuit technology. The 2 /spl mu/m rule VLSI fabrication technology is achieved by improving various aspects of the ultraviolet photolithographic, thin-gate oxidation, arsenic ion implantation, and multilevel interconnection processes. Microminiaturization of the device structure has made the voltage requirements for its MOST threshold voltage and DC supply voltages low. A highly sensitive and low power dissipating sense circuit has been developed for the VLSI RAM. A new level-detecting circuit with a logic threshold which is independent of MOST threshold voltage is proposed. A dynamic address-buffer circuit is also shown. The fabricated 64K RAM has 200 ns of access time, 370 ns of minimum cycle time, and 150 mW of power dissipation under typical supply voltage conditions of V/SUB DD/=7 V and V/SUB BB/=-2 V.  相似文献   

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