Low Weibull slope of breakdown distributions in high-k layers

The reliability of various Al₂O₃, ZrO₂ and Al₂O₃/ZrO₂ double layers with a physical oxide thickness from 3 nm to 15 nm and TiN gate electrodes was studied by measuring time-to-breakdown using gate injection and constant voltage stress. The extracted Weibull slope β of the breakdown distribution is found to be below 2 and shows no obvious thickness dependence. These findings deviate from previous results on intrinsic breakdown in SiO₂, where a strong thickness dependence was explained by the percolation model. Although promising performance on devices with high-k layers as dielectric can be obtained, it is argued that gate oxide reliability is likely limited by extrinsic factors     

A new model for the field dependence of intrinsic and extrinsictime-dependent dielectric breakdown

The field acceleration of intrinsic and extrinsic breakdown is studied. For the intrinsic mode an exp(1/E)-acceleration law is found, while for the extrinsic mode an new exp (E)-acceleration law for Q_BD is proposed. This field acceleration model is implemented in a maximum likelihood algorithm together with a new analytical expression for fitting competing Weibull distributions. With this algorithm an extensive t_BD-data set measured at different stress conditions can be fitted excellently in one single calculation. From the result, predictions of low-field oxide reliability are made and the screening conditions in order to guarantee a pre-set reliability specification are calculated     

Intrinsic and extrinsic reliability of a serial connection of capacitors

The on-wafer serial connection of two capacitors (stacked capacitors) is attractive for two reasons: on one hand the intrinsic reliability and especially the immunity against high voltage pulses increases and on the other hand the early fail risk decreases tremendously. The intrinsic and extrinsic reliability of stacked capacitors are demonstrated using the example of a metal insulator metal capacitor (MIMCAP) with Al₂O₃ dielectric. The intrinsic reliability of a stacked capacitor, where each of the capacitors uses a dielectric of thickness thk, is equal to the intrinsic reliability of a single capacitor with twice the dielectric thickness 2 * thk. The reduction of early fails for a stacked capacitor is a probability effect: if a single capacitor has the probability p to fail early and an early fail of the stacked capacitor is the combination of two single capacitors each of which contains an early fail, then the stacked capacitor fails early with a probability of p². This basic idea is checked by voltage ramp experiments on single and stacked MIM capacitors, where the single MIM capacitors show besides the intrinsic branch a prominent extrinsic branch.     

Impact of inside spacer process on fully self-aligned 250 GHz SiGe:C HBTs reliability performances: a-Si vs. nitride

A critical process aspect of the bipolar device is the oxide isolation between the emitter and the extrinsic base. Indeed, it is a well known fact that the emitter–base junction degradation is mainly due to interface states generation underneath oxide spacer. This study demonstrates the large impact of the inside spacer process in fully-self aligned high speed HBT on its reliability. Several types of electrical stress have been investigated and the stress-induced degradation compared for nitride and a-Si (amorphous silicon) spacers. Aging results coupled with noise measurements and TCAD simulations allowed to explain the different observed behaviors, finally concluding on the significantly higher reliability performances of devices processed with a-Si spacers.     

Reliability of erasing operation in NOR-Flash memories

The erase operation in NOR-Flash memories intrinsically gives rise to a wide threshold voltage distribution causing various reliability issues: read margin reduction; increase of total bitline leakage current and electrical stress during reading and programming. This paper will address and review the erasing operation by analyzing the causes, the reliability issues and the possible solutions of the erased threshold voltage distribution width, the presence of ultrafast bits, the erratic erase phenomenon, the presence of a significant tail (extrinsic behavior) in the erased distribution and the intrinsic oxide degradation during cycling (oxide aging).     

Reliability of ultrathin nitrided oxides grown in low pressure N2O ambient

The influence of N₂O oxynitridation and oxidation pressure on reliability of ultrathin gate oxides from 4 down to 2.5 nm thickness was investigated. A set of different oxidation parameters was applied during oxide growth which comprised oxidation pressure and N₂O partial pressure during rapid thermal oxidation. The reliability of the oxides was tested by constant voltage stress. Evaluation of the resulting times to soft breakdown (t_sbd) for different stress voltages allows to predict a supply (gate) voltage V^10y,max providing an oxide lifetime of 10 years. For this extrapolation, t_sbd was assumed to increase exponentially as stress voltage is reduced. The slope of the extrapolation is found to become steeper as oxides become thinner, which implies higher V^10y,max and thus higher reliability for thinner oxides as under an assumption of a uniform slope for all thicknesses. Further, the results of this extrapolation demonstrate that oxidation in N₂O containing ambient can improve oxide reliability for ultrathin gate oxides.     

Leakage paths identification in NVM using biased data retention

In this paper we propose a way to study leakage paths for electrons during data retention in floating gate non-volatile memories and especially in EEPROM memory cells. We investigate the main leakage paths, through tunnel oxide as well as through the tri-layer stack oxide “oxide/nitride/oxide” (ONO). We used a TCAD simulation of the full EEPROM cell to precisely determine the control gate bias voiding the electric field through ONO or tunnel oxide. Data retention measurements are then performed with simulated bias. We highlight the fact that leakage paths during data retention are different for extrinsic and intrinsic cells. Indeed, extrinsic behavior disappears when voiding electric field across tunnel oxide, showing these cells leak through tunnel oxide, whereas intrinsic behavior is the same whatever the electric field across tunnel oxide, showing charge loss in intrinsic cells is due to another path.     

Quality assessment of thin oxides using constant and ramped stress measurements

Two methods are proposed for obtaining extrinsic oxide lifetime data using fast ramped tests. It is shown that the intersection point between the extrinsic and intrinsic branches of a Weibull plot coincides for ramped and constant stress tests. This is the basis of our fast qualification approach, where intrinsic data are obtained by constant voltage stress and extrinsic data are cumulated with a fast ramped test. The correctness of our approaches is supported by constant voltage and exponentially ramped current measurements.     

Low voltage stress induced leakage current and time to breakdown in ultra-thin (1.2–2.3 nm) oxides

Ultra-thin gate-oxide reliability is an essential factor in CMOS technologies. The low voltage gate current in ultra-thin oxide of metal–oxide–semiconductor devices is very sensitive to electrical stresses. It can be used as a reliability monitor when the oxide thickness becomes too small for traditional electrical measurements. In this paper, the low voltage stress induced leakage current (LVSILC) for various oxide thicknesses ranging from 1.2 to 2.3 nm is investigated during constant voltage stress (CVS). From the LVSILC measurements, we shown that time to breakdown can be deduced as a function of the stress voltage. We also study the effect of elevated stress temperature on the time to breakdown. We show that temperature dependence of the time to breakdown is non-Arrhenius and decreases in a drastic way with a slope of 0.036 decade/°C.     

Study of unipolar pulsed ramp and combined ramped/constant voltage stress on mos gate oxides

MOS gate oxide capacitors over a wide range of oxide thicknesses (10.9–28 nm) were stressed using a unipolar pulsed voltage ramp and combined ramped/constant voltage stress measurements. The reliability measurements were performed with several different bias conditions in order to assess the effects of the measurement conditions on times to breakdown and breakdown fields. In the first part it was verified that the unipolar pulsed ramp yields breakdown distributions which are identical to those of a widely used staircase ramp. In the second part the unipolar pulsed ramp was used for pre-stress prior to a constant stress and measurement results were compared to those of a ramped/constant stress with a staircase ramp. In several cases a ramp prior to a constant stress increases time to breakdown. The observations made in this study imply that the time to breakdown of a constant stress in the Fowler-Nordheim tunneling regime is strongly dependent on charge trapping and, therefore, on the stressing history of the oxide. Finally, it is shown that the combined ramped/constant voltage stress is a valuable tool for monitoring extrinsic and intrinsic breakdown properties when applying stress parameters in the correct way.     

Degradation of AlGaAs/GaAs HBTs induced by hot carriers

In AlGaAs/GaAs HBTs, the instability of the surface states of the extrinsic base, which is revealed by mesa-etching and passivated by Si₃N₄, affects reliability. In this study the reverse constant current stress in an avalanche regime is applied across the emitter–base junction in order to test the stability of the heterojunction and the surface state of the extrinsic base. It has been identified that the surface of the extrinsic base is vulnerable to hot carriers. A new degradation mechanism is suggested and verified by numerical simulation. In addition, a way to improve the reliability is proposed based on the experimental results.     

Dielectric thinning model applied to metal insulator metal capacitors with Al2O3 dielectric

The extrinsic fails of metal insulator metal capacitors (MIMCAPs) with Al₂O₃ dielectric are modeled by a thinning model that is based on the intrinsic reliability model and the assumption that the extrinsic fails behave like an intrinsic dielectric with a reduced thickness. The intrinsic reliability model is developed from voltage acceleration experiments at four temperatures and four dielectric thicknesses. Voltage and thickness dependence of the logarithm of the intrinsic lifetime scales with the electric field and the temperature dependence is described by an Arrhenius factor. The voltage acceleration is not temperature dependent. The thinning model is shown to consistently describe acceleration experiments with random extrinsic fails of unknown root cause at low defect density (0.1 cm⁻²) as well as a systematic extrinsic failure mechanism caused by process induced plasma damage. It is also shown that the random extrinsic fails that were investigated on large area teststructures can be extrapolated to much smaller product typical capacitors. A criteria based on the stored energy is derived that allows to decide, whether an extrinsic fail will cause product failure. These results allow a quantitative prediction of early product fails due to the MIMCAP.     

Effect of oval defects in GaAs on the reliability of SiNx metal–insulator–metal capacitors

In this paper, we will assess the reliability of extrinsic defects in SiN_x metal–insulator–metal (MIM) capacitors as part of a GaAs high voltage (HV) FET process. The epitaxial GaAs layers used for this process contain a density of oval defects. Since the SiN_x is deposited at low temperatures, the MIM capacitors are amorphous and will always contain a certain amount of extrinsic defects. It will be shown that the number of extrinsic defects depends on the presence of the oval defects in the epitaxial GaAs layers. The reliability assessment will be done using electric field breakdown (Ebd), time dependent dielectric breakdown (TDDB) measurements and visual inspection. It will be shown that this combination can lead to an estimate of the lifetime and screening of capacitors containing extrinsic defects.     

用于Turbo迭代译码的log-MAP算法的简化

对用于Turbo迭代译码的对数最大后验概率(log-MAP)译码算法进行了分析和推导。根据Turbo编译码特点以及对格图中分支路径量度特性的分析,得到了简化分支路径量度和外部信息计算的方法。并就log-MAP算法中形如ln(ex+ey)的计算作了分析和化简,进一步减小log-MAP算法的复杂性。最后给出仿真结果并进行了分析。     

On the RF Extrinsic Resistance Extraction for Partially-Depleted SOI MOSFETs

We have investigated the radio frequency (RF) extrinsic resistance extraction for partially-depleted (PD) silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistors (MOSFETs). Although the thick buried oxide in SOI devices can block the substrate coupling, the SOI neutral-body coupling effect is significant for RF applications. An equivalent circuit considering this effect has been proposed. Based on this equivalent circuit, a new model capturing the frequency dependence of extrinsic resistances has been derived. After considering the impact of quasi-neutral body, we have developed a physically accurate RF extrinsic resistance extraction methodology for PD SOI MOSFETs     

An experimental method allowing quantifying and localizing failed cells of an EEPROM CAST after a retention test

Nowadays, data retention, especially on extrinsic cells, is one of the main issues in the reliability of non-volatile memories. The extrinsic data loss can be monitored with a test structure: the cell array stress test (CAST). Unfortunately, the extrinsic cells of a CAST cannot be easily quantified. In this paper, we present a new experimental method, based on the transconductance measurement of an EEPROM CAST, to quantify the extrinsic cells. This method has been verified by a method, based on emission microscopy, presented in a previous paper.     

Fault tolerant adaptive write schemes for improving endurance and reliability of memristor memories

The non-deterministic nature of memristor and its unreliable behavior are the two major concerns hampering its growth and industrial manufacturability. The endurance and reliability of memristor memories are affected not only by the process variations (intrinsic), but also due to the electrical stress created by interfacing peripheral circuits (extrinsic). Concerning the intrinsic faults in transition metal oxide (TMO) memristors, drifting of oxygen vacancies across the device is responsible for SET/RESET operation. It is likely that such drifting might induce switching faults during the device operation, for instance endurance of the memory. Thus, the application of a fixed write pulse may not suffice to achieve successful write operations under these circumstances. To circumvent the above pitfall, we propose here a new technique by designing a fault tolerant adaptable write scheme which can adapt by itself based on the behavior and switching faults. Accordingly, the proposed write scheme identifies the optimal amplitude and the width for write pulse. The proposed write scheme under various memristor faults is found to enhancing the reliability of memristors efficiently. Further, the results are validated by means of Monte-Carlo analysis by infusing the random variations of internal parameters of memristors as well.     

Impact of extrinsic and intrinsic parameter fluctuations on CMOScircuit performance

The yield of CMOS logic circuits satisfying a specific high performance requirement is demonstrated to be significantly influenced by the magnitude of critical-path delay deviations due to both extrinsic and intrinsic parameter fluctuations. To evaluate the impact of these parameter fluctuations, a static CMOS critical-path delay distribution is calculated from rigorously derived device and circuit models that enable projections for future technology generations. Two possible options are explored to attain a desired yield: (1) reduce performance by operating at a lower clock frequency; and (2) increase the supply voltage and, consequently, power dissipation, to satisfy the nominal critical-path delay. For the 50-nm technology generation, the delay and power dissipation increases are 12%-29% and 22%-6%, respectively, for extrinsic parameter standard deviations ranging from (a) 5% for effective channel length and 0% for gate oxide thickness and channel doping concentration to (b) 10% for effective channel length and 5% for gate oxide thickness and channel doping concentration. Combining both extrinsic and intrinsic fluctuations, the delay and power dissipation increase to 18%-32% and 31%-53%, respectively, thus demonstrating the significance of including the random dopant placement effect in future CMOS logic designs     

一种计算随机流网络可靠性的新算法

提出了一种计算随机流网络可靠性的新方法。通过一定的规则生成网络的状态树，使得每一个分支都是全序集合。在生成状态树的同时搜索每一个分支，对状态采用基于割集的方法进行判断。每个分支上的最小的有效状态就是网络的d-下界点。求得所有的d-下界点，进而求出网络的可靠性。     

Estimating effective dielectric thickness for capacitors with extrinsic defects by a statistical method

Simulated capacitor breakdown voltage data are fit to a mixture of two Weibull distributions using the method of maximum likelihood. The dielectric thickness of extrinsic capacitors is estimated as a part of a mixture distribution, allowing simultaneous prediction of failure times using both intrinsic and extrinsic failures. Confidence intervals on the reliability parameters and the 10 year FIT rate at 5 V are successfully estimated using the delta method. The same approach is applied to a real data set with similar results.