Electrical characterisation of SiON/n-Si structures for MOS VLSI electronics

In the present work, we examine the properties of SiON films grown on Si substrates by CVD in order to investigate their suitability as potential materials in replacing SiO₂ in metal-oxide-semiconductor (MOS) devices. Suitable metallization created MOS devices and electrical characterisation took place in order to identify their electrical properties. Electrical measurements included current-voltage (I-V), capacitance-conductance-voltage (C-V) measurements and admittance spectroscopy (Y−ω) allowing determination of the bulk charges and the dielectric response of the films. The analysis of the data also took into account the presence of traps at the Si/SiON interface calculated by a fast conductance technique. The interface states density was of the order of 10¹² eV⁻¹ cm⁻². The dielectric constant was found to lie between 16 and 4.5 and the corresponding bulk trapped charges were found between 8 and 113 μCb cm⁻². Post deposition annealing altered these values showing an improvement of the device behaviour. A short explanation of the above is also provided.     

Titanium-aluminum oxynitride (TAON) as high-k gate dielectric for sub-32 nm CMOS technology

High-k insulators for the next generation (sub-32 nm CMOS (complementary metal-oxide-semiconductor) technology), such as titanium-aluminum oxynitride (TAON) and titanium-aluminum oxide (TAO), have been obtained by Ti/Al e-beam evaporation, with additional electron cyclotron resonance (ECR) plasma oxynitridation and oxidation on Si substrates, respectively. Physical thickness values between 5.7 and 6.3 nm were determined by ellipsometry. These films were used as gate insulators in MOS capacitors fabricated with Al electrodes, and they were used to obtain capacitance-voltage (C-V) measurements. A relative dielectric constant of 3.9 was adopted to extract the equivalent oxide thickness (EOT) of films from C-V curves under strong accumulation condition, resulting in values between 1.5 and 1.1 nm, and effective charge densities of about 10¹¹ cm⁻². Because of these results, nMOSFETs with Al gate electrode and TAON gate dielectric were fabricated and characterized by current-voltage (I-V) curves. From these nMOSFETs electrical characteristics, a sub-threshold slope of 80 mV/dec and an EOT of 0.87 nm were obtained. These results indicate that the obtained TAON film is a suitable gate insulator for the next generation (MOS) devices.     

Ta/Si Schottky diodes fabricated by magnetron sputtering technique

Electrical properties of Ta/n-Si and Ta/p-Si Schottky barrier diodes obtained by sputtering of tantalum (Ta) metal on semiconductors have been investigated. The characteristic parameters of these contacts like barrier height, ideality factor and series resistance have been calculated using current voltage (I-V) measurements. It has seen that the diodes have ideality factors more than unity and the sum of their barrier heights is 1.21 eV which is higher than the band gap of the silicon (1.12 eV). The results have been attributed the effects of inhomogeneities at the interface of the devices and native oxide layer. In addition, the barrier height values determined using capacitance-voltage (C-V) measurements have been compared the ones obtained from I-V measurements. It has seen that the interface states have strong effects on electrical properties of the diodes such as C-V and R_s-V measurements.     

Four-point probe characterization of 4H silicon carbide

We report on four-point probe measurements on SiC wafers as such measurements give erratic data. Current-voltage measurements on n-type SiC wafers doped to 3 × 10¹⁸ cm⁻³ are non-linear and single probe I-V measurements are symmetrical for positive and negative voltages. For comparison, similar measurements of p-type Si doped to 5 × 10¹⁴ cm⁻³ gave linear I-V, well-defined sheet resistance and the single probe I-V curves were asymmetrical indicating typical Schottky diode behavior. We believe that the reason for the non-linearity in four-point probe measurements on SiC is the high contact resistance. Calculations predict the contact resistance of SiC to be approximately 10¹² Ω which is of the order of the input resistance of the voltmeter in our four-point probe measurements. There was almost no change in two-probe I-V curves when the spacing between the probes was changed from 1 mm to 2 cm, further supporting the idea that the I-V characteristics are dominated by the contact resistance.     

Enhanced electrical properties of nominally undoped Si/SiGe heterostructure nanowires grown by molecular beam epitaxy

Electrical properties of epitaxial single-crystalline Si/SiGe axial heterostructure nanowires (NWs) on Si〈1 1 1〉 substrate were measured by contacting individual NWs with a micro-manipulator inside an scanning electron microscope. The NWs were grown by incorporating compositionally graded Si_1−xGe_x segments of a few nm thicknesses in the Si NWs by molecular beam epitaxy. The I-V characteristics of the Si/SiGe heterostructure NWs showed Ohmic behavior. However, the resistivity of a typical heterostructure NW was found to be significantly low for the carrier concentration extracted from the simulated band diagram. Similarly grown pure Si and Ge NWs showed the same behavior as well, although the I-V curve of a typical Si NW was rectifying in nature instead of Ohmic. It was argued that this enhanced electrical conductivities of the NWs come from the current conduction through their surface states and the Ge or Si/SiGe NWs are more strongly influenced by the surface than the Si ones.     

Fabrication and characterization of in situ polymerized n-polyaniline films grown on p-Si heterojunctions

This work presents a study on the fabrication and the electrical transport mechanism of the in situ polymerized n-type polyaniline (PANI) grown on p-type Si to form n-polyaniline/p-Si heterojunction devices. The current-voltage-temperature (I-V-T) characteristics of n-PANI/p-Si devices were investigated in the temperature range of 298-373 K. These devices showed good rectifying behavior and the temperature dependence of the I-V characteristics were successfully explained by the thermionic mechanism in the narrow potential range, V ? 0.4 V. The barrier height, ideality factor and the series resistance values of this structure were obtained from the forward bias I-V characteristics. The capacitance-voltage-temperature (C-V-T) characteristics of n-PANI/p-Si devices were also investigated. The barrier height values obtained from the C-V measurements were found to be higher than that obtained from the I-V measurements at various temperatures. From the capacitance-voltage-frequency (C-V-f) characteristics, it was found that the capacitance remained almost constant up to a certain values of the frequency in the lower and higher sides of the frequency scale. The higher values of capacitance at low frequencies were attributed to the excess capacitance resulting from the interface states in equilibrium with the p-Si side that can follow the AC signal.     

Annealing temperature effect on electrical and structural properties of Cu/Au Schottky contacts to n-type GaN

Schottky contacts were fabricated on n-type GaN using a Cu/Au metallization scheme, and the electrical and structural properties have been investigated as a function of annealing temperature by current-voltage (I-V), capacitance-voltage (C-V), Auger electron spectroscopy (AES) and X-ray diffraction (XRD) measurements. The extracted Schottky barrier height of the as-deposited contact was found to be 0.69 eV (I-V) and 0.77 eV (C-V), respectively. However, the Schottky barrier height of the Cu/Au contact slightly increases to 0.77 eV (I-V) and 1.18 eV (C-V) when the contact was annealed at 300 °C for 1 min. It is shown that the Schottky barrier height decreases to 0.73 eV (I-V) and 0.99 eV (C-V), 0.56 eV (I-V) and 0.87 eV (C-V) after annealing at 400 °C and 500 °C for 1 min in N₂ atmosphere. Norde method was also used to extract the barrier height of Cu/Au contacts and the values are 0.69 eV for the as-deposited, 0.76 eV at 300 °C, 0.71 eV at 400 °C and 0.56 eV at 500 °C which are in good agreement with those obtained by the I-V method. Based on Auger electron spectroscopy and X-ray diffraction results, the formation of nitride phases at the Cu/Au/n-GaN interface could be the reason for the degradation of Schottky barrier height upon annealing at 500 °C.     

Electrical characterization and morphological properties of AlN films prepared by dc reactive magnetron sputtering

Aluminum nitride (AlN) films were deposited by dc reactive magnetron sputtering on p-Si-(1 0 0) substrate in Ar-N₂ gas mixtures. The effects of nitrogen concentration and sputtering power on AlN films deposition rate, crystallographic orientation, refractive index, and surface morphology are investigated by means of several characterization techniques. The results show that AlN films reasonably textured in (0 0 2) orientation with low surface roughness can be obtained with the deposition rate as high as 70 nm/min by the control of either target power or N₂ concentration in the gas mixture. Increasing the dc discharge power, Al atoms are not completely nitridized and the Al phases appear, as well as the AlN phases. MIS (Metal-Insulator-Semiconductor) structures were fabricated and electrically evaluated by I-V (current-voltage) and C-V (capacitance-voltage) measurements at high frequency (1 MHz). The results obtained from C-V curves indicate that charges at the dielectric/semiconductor interface occur, and the dielectric constant values (extracted under strong accumulation region) are compatible with those found in literature.     

Effect of series resistance on the electrical characteristics and interface state energy distributions of Sn/p-Si (MS) Schottky diodes

In this study, electrical characteristics of the Sn/p-type Si (MS) Schottky diodes have been investigated by current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. The barrier height obtained from C-V measurement is higher than obtained from I-V measurement and this discrepancy can be explained by introducing a spatial distribution of barrier heights due to barrier height inhomogeneities, which are available at the nanostructure Sn/p-Si interface. A modified Norde’s function combined with conventional forward I-V method was used to extract the parameters including barrier height (Φ_b) and the series resistance (R_S). The barrier height and series resistance obtained from Norde’s function was compared with those from Cheung functions. In addition, the interface-state density (N_SS) as a function of energy distribution (E_SS-E_V) was extracted from the forward-bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_b) and series resistance (R_S) for the Schottky diodes. While the interface-state density (N_SS) calculated without taking into account series resistance (R_S) has increased exponentially with bias from 4.235 × 10¹² cm⁻²eV⁻¹ in (E_SS - 0.62) eV to 2.371 × 10¹³ cm⁻²eV⁻¹ in (E_SS - 0.39) eV of p-Si, the N_SS obtained taking into account the series resistance has increased exponentially with bias from of 4.235 × 10¹² to 1.671 × 10¹³ cm⁻²eV⁻¹ in the same interval. This behaviour is attributed to the passivation of the p-doped Si surface with the presence of thin interfacial insulator layer between the metal and semiconductor.     

Ultrathin insulating silica layers prepared from adsorbed TEOS, H2O and NH3 as a catalyst

Homogeneous ultrathin silica films were deposited without need of any expensive equipment and high-temperature processes (t?200 °C). Repeated adsorption of tetraethoxysilane (TEOS) multimolecular layers and their subsequent reaction with H₂O/NH₃ mixed vapours at atmospheric pressure and room temperature were used. By preparing the Al/SiO₂/N-Si MOS structure conditions were attained for electrical characterisation of the thin oxide layer by capacitance (C-V) and current (I-V) measurements. These measurements confirmed acceptable insulating properties of the oxide, the maximum breakdown field intensity being E_bd=5.4 MV/cm. The total defect charge of the MOS structure was positive, affected by a high trap density at the Si-SiO₂ interface.     

Influence of rapid thermal annealing temperature on structure and electrical properties of high permittivity HfTiO thin film used in MOSFET

HfTiO thin films were prepared by r.f. magnetron co-sputtering on Si substrate. To improve the electrical properties, HfTiO thin films were post heated by rapid thermal annealing (RTA) at 400 °C, 500 °C, 600 °C and 700 °C in nitrogen. It was found that the film is amorphous below 700 °C and at 700 °C monoclinic phase HfO₂ has occurred. With the increase of the annealing temperature, the film becomes denser and the refractive index increases. By electrical measurements, we found at 500 °C annealed condition, the film has the best electrical property with the largest dielectric constant of 44.0 and the lowest leakage current of 1.81 × 10⁻⁷ A/cm², which mainly corresponds to the improved microstructure of HfTiO thin film. Using the film annealed at 500 °C as the replacement of SiO₂ dielectric layer in MOSFET, combining with TiAlN metal electrode, a 10 μm gate-length MOSFET fabricated by three-step photolithography processes. From the transfer (I_DS–V_G) and output (I_DS–V_DS) characteristics, it shows a good transistor performance with a threshold voltage (V_th) of 1.6 V, a maximum drain current (I_ds) of 9 × 10⁻⁴ A, and a maximum transconductance (G_m) of 2.2 × 10⁻⁵ S.     

Thin titanium oxide films deposited by e-beam evaporation with additional rapid thermal oxidation and annealing for ISFET applications

Titanium oxide (TiO₂) has been extensively applied in the medical area due to its proved biocompatibility with human cells [1]. This work presents the characterization of titanium oxide thin films as a potential dielectric to be applied in ion sensitive field-effect transistors. The films were obtained by rapid thermal oxidation and annealing (at 300, 600, 960 and 1200 °C) of thin titanium films of different thicknesses (5 nm, 10 nm and 20 nm) deposited by e-beam evaporation on silicon wafers. These films were analyzed as-deposited and after annealing in forming gas for 25 min by Ellipsometry, Fourier Transform Infrared Spectroscopy (FTIR), Raman Spectroscopy (RAMAN), Atomic Force Microscopy (AFM), Rutherford Backscattering Spectroscopy (RBS) and Ti-K edge X-ray Absorption Near Edge Structure (XANES). Thin film thickness, roughness, surface grain sizes, refractive indexes and oxygen concentration depend on the oxidation and annealing temperature. Structural characterization showed mainly presence of the crystalline rutile phase, however, other oxides such Ti₂O₃, an interfacial SiO₂ layer between the dielectric and the substrate and the anatase crystalline phase of TiO₂ films were also identified. Electrical characteristics were obtained by means of I-V and C-V measured curves of Al/Si/TiO_x/Al capacitors. These curves showed that the films had high dielectric constants between 12 and 33, interface charge density of about 10¹⁰/cm² and leakage current density between 1 and 10⁻⁴ A/cm². Field-effect transistors were fabricated in order to analyze I_D x V_DS and log I_D × Bias curves. Early voltage value of −1629 V, R_OUT value of 215 MΩ and slope of 100 mV/dec were determined for the 20 nm TiO_x film thermally treated at 960 °C.     

On the profile of frequency and voltage dependent interface states and series resistance in (Ni/Au)/Al0.22Ga0.78N/AlN/GaN heterostructures by using current-voltage (I-V) and admittance spectroscopy methods

In order to explain the experimental effect of interface states (N_ss) and series resistance (R_s) of device on the non-ideal electrical characteristics, current-voltage (I-V), capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics of (Ni/Au)/Al_0.22Ga_0.78N/AlN/GaN heterostructures were investigated at room temperature. Admittance measurements (C-V and G/ω-V) were carried out in frequency and bias voltage ranges of 2 kHz-2 MHz and (−5 V)-(+5 V), respectively. The voltage dependent R_s profile was determined from the I-V data. The increasing capacitance behavior with the decreasing frequency at low frequencies is a proof of the presence of interface states at metal/semiconductor (M/S) interface. At various bias voltages, the ac electrical conductivity (σ_ac) is independent from frequencies up to 100 kHz, and above this frequency value it increases with the increasing frequency for each bias voltage. In addition, the high-frequency capacitance (C_m) and conductance (G_m/ω) values measured under forward and reverse bias were corrected to minimize the effects of series resistance. The results indicate that the interfacial polarization can more easily occur at low frequencies. The distribution of N_ss and R_s is confirmed to have significant effect on non-ideal I-V, C-V and G/ω-V characteristics of (Ni/Au)/Al_0.22Ga_0.78N/AlN/GaN heterostructures.     

Effect of reactive sputter etching of SiO2 on the properties of subsequently formed MOS systems

We investigated the effects of reactive sputter etching (RSE) of SiO₂ on the electrical properties of the SiSiO₂ system using CHF₃ in a commercial apparatus. SIMS and Auger spectrometry revealed contamination of RSE-exposed Si surfaces with carbon and heavy metals. The generation of crystal defects during thermal reoxidation was observed to be closely related to the level of metal contamination. C-V, C-t and I-V measurements on subsequently formed MOS structures showed, that oxide charge, interface state and mobile ion densities are nearly unaffected by the RSE process. However, minority carrier lifetime in the Si substrate and isolation behavior of the oxide layer are strongly degraded; our results suggest, that both effects are mainly due to metallic impurities. The use of inert cathode materials like quartz reduces metal contamination, but a non-negligible contribution from the grounded metal surfaces of the reactor remains. Carrier lifetime and insulating properties reach the values obtained on wet chemically etched samples only after extended times of plasma excitation in the apparatus. This is attributed to a passivation of the grounded surfaces by the formation of polymer films. Taking advantage of this effect MOSFETs were fabricated by the use of RSE without deterioration of their electrical performance.     

Electrical characteristics and inhomogeneous barrier analysis of Au-Be/p-InSe:Cd Schottky barrier diodes

We have identically prepared Au-Be/p-InSe:Cd Schottky barrier diodes (SBDs) (21 dots) on the InSe:Cd substrate. The electrical analysis of Au-Be/p-InSe:Cd structure has been investigated by means of current-voltage (I-V), capacitance-voltage (C-V) and capacitance-frequency (C-f) measurements at 296 K temperature in dark conditions. The effective barrier heights and ideality factors of identically fabricated Au-Be/p-InSe:Cd SBDs have been calculated from their experimental forward bias current-voltage (I-V) characteristics by applying a thermionic emission theory. The BH values obtained from the I-V characteristics have varied between 0.74 eV and 0.82 eV with values of ideality factors ranging between 1.49 and 1.11 for the Au-Be/p-InSe:Cd SBDs. It has been determined a lateral homogeneous barrier height value of approximately 0.82 eV for these structures from the experimental linear relationship between barrier heights and ideality factors. The Schottky barrier height (SBH) value has been obtained from the reverse-bias C-V characteristics of Au-Be/p-InSe:Cd SBD for only one diode. At high currents in the forward direction, the series resistance effect has been observed. The value of series resistance has been determined from I-V measurements using Cheung’s and Norde’s methods.     

Analysis of electronic parameters and interface states of boron dispersed triethanolamine/p-Si structure by AFM, I-V, C-V-f and G/ω-V-f techniques

The electronic parameters and interface state properties of boron dispersed triethanolamine/p-Si structure have been investigated by atomic force microscopy, I-V, C-V-f and G/ω-V-f techniques. The surface topography and phase image of the TEA-B film deposited onto p-Si substrate were analyzed by atomic force microscopy. The atomic force microscopy results show a homogenous distribution of boron particles in triethanolamine film. The electronic parameters (barrier height, ideality factor and average series resistance) obtained from I-V characteristics of the diode are 0.81 eV, 2.07 and 5.04 kΩ, respectively. The interface state density of the diode was found to be 2.54 × 10¹⁰ eV⁻ cm⁻² under V_g = 0. The obtained D_it values obtained from C-V and G/ω measurements are in agreement with each other. The profile of series resistance dependent on voltage and frequency confirms the presence of interface states in boron dispersed triethanolamine/p-Si structure. It is evaluated that the boron dispersed triethanolamine controls the electronic parameters and interface properties of conventional Al/p-Si diode.     

High resolution electrical characterisation of organic photovoltaic blends

In this work, electrostatic force microscopy (EFM) and conductive atomic force microscopy (C-AFM) are applied to perform high-resolution electrical characterisation of organic photovoltaic films. These films are composed of the C₆₀-derivative PCBM blended with hole conductive conjugated polymers PPV derivatives or P3HT. It is demonstrated that both EFM and C-AFM are able to electrically evidence phase separation in the blends, suggesting in addition higher density of carriers along interfaces. Correlation between the EFM contrast and the photovoltaic properties of the blends was observed. Local spectroscopy (I-V curves) completes the C-AFM investigations, analysing charge transport mechanisms in the P3HT:PCBM blend. Significant modifications of the local electrical properties of P3HT are shown to occur upon blending. Space charge limited current is evidenced in the blend and a hole mobility of 1.7 × 10⁻² cm² V⁻¹ s⁻¹ is determined for P3HT.     

Temperature dependent electrical and dielectric properties of Au/polyvinyl alcohol (Ni, Zn-doped)/n-Si Schottky diodes

The electrical and dielectric properties of Au/PVA (Ni, Zn-doped)/n-Si Schottky diodes (SDs) were studied in the temperature range of 80-400 K. The investigation of various SDs fabricated with different types of interfacial layer is important for understanding the electrical and dielectric properties of SDs. Therefore, in this study polyvinyl alcohol (PVA) film was used as an interfacial layer between metal and semiconductor. The electrical and dielectric properties of Au/PVA (Ni, Zn-doped)/n-Si SDs were calculated from the capacitance-voltage (C-V) and conductance-voltage (G/w-V) measurements. The effects of interface state density (N_ss) and series resistance (R_s) on C-V characteristics were investigated in the wide temperature range. It was found that both of the C-V-T and G/w-V-T curves included two abnormal regions and one intersection point. The dielectric constant (ε″), dielectric loss (ε″), dielectric loss tangent (tan δ) and the ac electrical conductivity (σ_ac) obtained from the measured capacitance and conductance were studied for Au/PVA (Ni, Zn-doped)/n-Si SDs. Experimental results show that the values of ε′, ε″ and tan δ are a strong function of the temperature. Also, the results indicate the interfacial polarization can be more easily occurred at high temperatures.     

Study of ultrathin vanadium nitride as diffusion barrier for copper interconnect

Ultrathin Vanadium nitride (VN) thin film with thickness around 10 nm was studied as diffusion barrier between copper and SiO₂ or Si substrate. The VN film was prepared by reactive ion beam sputtering. X-ray diffraction, Auger electron spectroscopy, scanning electron microscopy and current-voltage (I-V) technique were applied to characterize the diffusion barrier properties for VN in Cu/VN/Si and Cu/VN/SiO₂ structures. The as-deposited VN film was amorphous and could be thermal stable up to 800 °C annealing. Multiple results show that the ultrathin VN film has good diffusion barrier properties for copper.     

Current-voltage characteristics of p-Si/carbon junctions fabricated by pulsed laser deposition

Amorphous carbon/p-Si junctions were fabricated at different temperatures using KrF excimer laser (λ = 248 nm, pulsed duration 20 ns). The current-voltage measurements of the devices showed diode characteristics. The value of various junction parameters such as ideality factor, barrier height, and series resistance were determined from forward bias I-V characteristics, Cheung method, and Norde’s function. There was a good agreement between the diodes parameters obtained from these methods. The ideality factor of ∼1.12 and barrier height of ∼0.37 eV were estimated using current-voltage characteristics for films grown at room temperature.