Electroluminescence from Au/Si/SiO2/p-Si structure

Si/SiO₂ films have been grown using the two-target alternation magnetron sputtering technique. The thickness of the SiO₂ layer in all the films was 8 nm and that of the Si layer in five types of the films ranged from 4 to 20 nm in steps of 4 nm. Visible electroluminescence (EL) has been observed from the Au/Si/SiO₂/p-Si structures at a forward bias of 5 V or larger. A broad band with one peak 650–660 nm appears in all the EL spectra of the structures. The effects of the thickness of the Si layer in the Si/SiO₂ films and of input electrical power on the EL spectra are studied systematically.     

SiO2/Si上石墨烯薄膜的化学气相沉积法制备及其性能表征

以铜为催化剂,采用聚甲基丙烯酸甲酯(PMMA)和甲烷为碳源的化学气相沉积两步法,在SiO₂/Si衬底上制备了石墨烯薄膜。利用拉曼光谱分析了薄膜的层数和质量,利用光学显微镜(OM)和扫描电子显微镜(SEM)分析了薄膜的尺寸与表面形貌。实验探究了生长时间、氢气流量和气体总压强等工艺参数对石墨烯薄膜层数和质量的影响,最终在优化条件下制得10μm级质量较高的多层石墨烯薄膜。     

SOI planar photonic crystal fabrication: Etching through SiO2/Si/SiO2 layer systems using fluorocarbon plasmas

Dry plasma etching of sub-micron structures in a SiO₂/Si/SiO₂ layer system using Cr as a mask was performed in a fluorocarbon plasma. It was determined that the best anisotropy could be achieved in the most electropositive plasma. A gas composition yielding the desired SOI planar photonic crystal structures was optimized from the available process gases, Ar, He, O₂, SF₆, CF₄, c-C₄F₈, CHF₃, using DC bias data sets. Application of the c-C₄F₈/(noble gas) chemistry allowed fabrication of the desired SOI planar photonic crystal. The average etching rates for the pores and ridge waveguide regions were about 71 and 97 nm/min, respectively, while the average SiO₂/Si/SiO₂ to Cr etching selectivity for the ridge waveguide region was about 33:1 in case of the c-C₄F₈/90%Ar plasma with optimized parameters.     

不同氧化退火工艺下SiO2/SiC界面特性研究

The effect of the different re-oxidation annealing （ROA） processes on the SiO2/SiC interface charac- teristics has been investigated. With different annealing processes, the flat band voltage, effective dielectric charge density and interface trap density are obtained from the capacitance-voltage curves. It is found that the lowest interface trap density is obtained by the wet-oxidation annealing process at 1050 ℃ for 30 min, while a large num- ber of effective dielectric charges are generated. The components at the SiO2/SiC interface are analyzed by X-ray photoelectron spectroscopy （XPS） testing. It is found that the effective dielectric charges are generated due to the existence of the C and H atoms in the wet-oxidation annealing process.     

氧化硅RIE刻蚀工艺研究

利用反应等离子刻蚀技术对SiO2进行干法刻蚀,研究了不同刻蚀条件对刻蚀速率、刻蚀选择比、刻蚀面粗糙度、刻蚀均匀性等的影响。分析得出了刻蚀侧壁角度与刻蚀选择比以及抗蚀掩模自身的侧壁角度之间存在的数学关系,这为如何获得垂直的刻蚀侧壁提供了参考。     

氧化硅RIE刻蚀工艺研究

利用反应等离子刻蚀技术对SiO₂进行干法刻蚀, 研究了不同刻蚀条件对刻蚀速率、刻蚀选择比、刻蚀面粗糙度、刻蚀均匀性等的影响。分析得出了刻蚀侧壁角度与刻蚀选择比以及抗蚀掩模自身的侧壁角度之间存在的数学关系, 这为如何获得垂直的刻蚀侧壁提供了参考。     

基于SiO2溶胶的稳定性的Cu/SiO2催化体系在化学机械抛光中的应用研究

There is a lot ofhydroxyl on the surface ofnano SiO2 sol used as an abrasive in the chemical mechanical planarization （CMP） process, and the chemical reaction activity of the hydroxyl is very strong due to the nano effect. In addition to providing a mechanical polishing effect, SiO2 sol is also directly involved in the chemical reaction. The stability of SiO2 sol was characterized through particle size distribution, zeta potential, viscosity, surface charge and other parameters in order to ensure that the chemical reaction rate in the CMP process, and the surface state of the copper film after CMP was not affected by the SiO2 sol. Polarization curves and corrosion potential of different concentrations of SiO2 sol showed that trace SiO2 sol can effectively weaken the passivation film thickness. In other words, SiO2 sol accelerated the decomposition rate of passive film. It was confirmed that the SiO2 sol as reactant had been involved in the CMP process of copper film as reactant by the effect of trace SiO2 sol on the removal rate of copper film in the CMP process under different conditions. In the CMP process, a small amount of SiO2 sol can drastically alter the chemical reaction rate of the copper film, therefore, the possibility that Cu/SiO2 as a catalytic system catalytically accelerated the chemical reaction in the CMP process was proposed. According to the van＇t Hoff isotherm formula and the characteristics of a catalyst which only changes the chemical reaction rate without changing the total reaction standard Gibbs free energy, factors affecting the Cu/SiO2 catalytic reaction were derived from the decomposition rate of Cu （OH）2 and the pH value of the system, and then it was concluded that the CuSiO3 as intermediates of Cu/SiO2 catalytic reaction accelerated the chemical reaction rate in the CMP process. It was confirmed that the Cu/SiO2 catalytic system generated the intermediate of the catalytic reaction （CuSiO3） in the CMP process through the removal rate of copper film, infrared spectrum and AFM diagrams in different pH conditions. FinalLy it is concluded that the SiO2 sol used in the experiment possesses stable performance; in the CMP process it is directly involved in the chemical reaction by creating the intermediate of the catalytic reaction （CuSiO3） whose yield is proportional to the pH value, which accelerates the removal of copper film.     

二氧化硅纳米花的制备及发光特性研究

采用磁控溅射和化学气相沉积技术制备出二氧化硅纳米花。利用扫描电子显微镜(SEM),X射线光电子能谱(XPS)和傅里叶红外吸收谱(FTIR)对上述纳米结构进行结构表征。用荧光光谱仪(PL)对其光致发光特性进行了研究。结果表明在激发波长为325nm时,在394nm处出现一个发光峰,表现出良好的发光特性。     

Effect of H2O evolving from TEOS based SiO2 film on the EEPROM cell characteristic

In this paper, we investigate the effect of water (H₂O) molecules evolving from silicon dioxide (SiO₂) film deposited by low pressure chemical vapor deposition (LPCVD) at 670 °C on the transistor characteristic of an electrically erasable programmable read only memory (EEPROM) cell. Fourier Transform Infra red (FT-IR) analysis reveals that H₂O is captured during film deposition and diffused to silicon surface during high thermal processing. The diffused H₂O molecules lower threshold voltage (V_t) of cell transistor and, thus, leakage current of the cell transistor is increased. In erased cell, V_t lowering is 0.25 V in which it increases leakage current of cell transistor from 1 to 100 pA. This results in the lowering of high voltage margin of a 512 Kb EEPROM from 2.8 to 2.6 V at 85 °C.     

利用金作为催化剂在不同衬底上制备二氧化硅纳米线

利用金作为催化剂分别在二氧化硅及硅衬底上制备出二氧化硅纳米线。用扫描电子显微镜（SEM）及x射线光电子能谱（XPS）对纳米线进行了结构表征。SEM结果表明二氧化硅纳米线的长度为几个纳米,直径为20-150纳米。XPS结果给出硅与氧的原子比为1:2,说明所得到的为二氧化硅纳米线。二氧化硅纳米线的生长机理为气-液-固（VLS）机制。实验发现退火时间影响二氧化硅纳米线的形貌。我们也讨论了衬底对纳米线生长的影响。     

A comparative study of depth profiling of interface states using charge pumping and low frequency noise measurement in SiO2/HfO2 gate stack nMOSFETs

Charge pumping and low frequency noise measurements for depth profiling have been studied systematically using a set of gate stacks with various combinations of IL and HfO₂ thicknesses. The distribution of generated traps after HCI and PBTI stress was also investigated. The drain-current power spectral density made up all of the traps of IL in 0 < z < T_IL and the traps of HfO₂ in T_IL < z < T_HK. The traps near the Si/SiO₂ interface dominated the 1/f noise at higher frequencies, which is common in SiO₂ dielectrics. For the HfO₂/SiO₂ gate stack, however, the magnitude of the 1/f noise did not significantly change after HCI and PBTI because of more traps in the bulk HfO₂ film than at the bottom of the interface.     

基于PECVD的SiO2薄膜制备研究进展

二氧化硅(SiO₂)薄膜因其卓越的光学性能,在半导体器件、集成电路、光学涂层等领域具有巨大的应用潜力。然而,SiO₂薄膜制备过程中面临表面粗糙度、杂质控制和致密性等问题。为解决这些问题,研究者们通过工艺改进和表面修饰等手段来提高SiO₂薄膜的性能。在众多SiO₂薄膜制备技术中,等离子体增强化学气相沉积(Plasma-Enhanced Chemical Vapor Deposition, PECVD)技术由于沉积SiO₂薄膜所需温度低、原位生长等优势,成为制备SiO₂薄膜最常用的方法。综述了用PECVD技术制备SiO₂薄膜的发展历程,并探讨了关键工艺参数和后处理工艺对薄膜质量的影响。对PECVD技术的深入研究,有助于实现对SiO₂薄膜生长的更精准控制,进一步拓展其广泛的应用前景。     

Influence of temperature on the etching rate of SiO2 in CF4 + O2 plasma

The plasmochemical etching of SiO₂ in CF₄ + O₂ plasma is considered. During the experiment SiO₂ films are etched in CF₄ + O₂ plasma at temperatures of 300 and 350 K. The dependences of plasmochemical etching rates of SiO₂ on O₂ content in the feed are measured. The experimental measurements are compared with theoretical calculations. The obtained theoretical results are used to predict the real dimensions of etched trenches. It is found that decrease in temperature reduces lateral undercutting due to decreased desorption of formed SiF₄ molecules from the sidewalls.     

Characterization of the effects of nitrogen and hydrogen passivation on SiO2/4H-SiC interface by low temperature conductance measurements

In this work we investigate the effects of NO annealing and forming gas (FG) an-nealing on the electrical properties of SiO2/SiC interface by low-temperature con-ductance measurements. With nitrogen passivation, the density of interface states (DIT) is significantly reduced in the entire energy range, and the shift of flatband voltage, ΔVFB, is effectively suppressed to less than 0.4 V. However, very fast states are ob-served after NO annealing and the response frequencies are higher than 1 MHz at room temperature. After additional FG annealing, the DIT and ΔVFB are further re-duced. The values of the DIT decrease to less than 1011 cm-2eV-1 for the energy range of EC-ET≥0.4 eV. It is suggested that the fast states in shallow energy levels origi-nated from the N atoms accumulating at the interface by NO annealing. Though FG annealing has a limited effect on these shallow traps, hydrogen can terminate the re-sidual Si and C dangling bonds corresponding to traps at deep energy levels and im-prove the interface quality further. It is indicated that NO annealing in conjunction with FG annealing will be a better post-oxidation process method for high perfor-mance SiC MOSFETs.     

湿法氧化Al0.85Ga0.15As时SiO2层的保护作用

本文研究了有无氧化硅保护层时Al0.85Ga0.15As层的高温湿法氧化。实验结果表明：氧化硅层对Al0.85Ga0.15As层的高温侧向湿法氧化速率基本无影响;被氧化区域SEM图像的衬度和有氧化硅保护层样品As拉曼峰的缺乏归因于被氧化区域中不存在氧化反应产物As,这有利于提高氧化层的热稳定性;有SiO2保护层样品的发光强度比无SiO2保护层样品的发光强度强的多,且具有SiO2保护层样品的发光峰位和半高全宽与氧化前的样品基本一致,而无SiO2保护层样品的发光峰位红移,半高宽展宽,这是由于氧化硅层阻止了GaAs盖层的氧化。     

Influence of activated polymer on the etching rate of SiO2 in CF4 + H2 plasma

The reactive ion etching (RIE) of SiO₂ in CF₄ + H₂ plasma is considered. The influence of activated polymer on the RIE rate of SiO₂ in CF₄ + H₂ plasma is determined by extrapolation of experimentally measured kinetics of the etching rate. It is found that the increased surface coverage by CF₂ radicals suppresses the RIE rate of SiO₂ in CF₄ + H₂ plasma during the initial stages of the etching process. The formation of activated polymer becomes pronounced when adsorbed CF₂ radicals are slowly activated. The activated polymer intensifies the etching reaction and enhances the etching rate. At the same time, the activated polymer intensifies the polymerization reactions. The increased surface coverage by the polymer suppresses the RIE rate of SiO₂ in CF₄ + H₂ plasma at later stages of the etching process.     

SiO2/聚合物Y分支波导型热光开关研究

为提高波分复用(WDM)光通信网中核心器件光开关 的响应速度,设计并制备了SiO₂/聚合物复合型 Y分支结构波导热光开关。器 件选择具有高热导率的SiO₂作为波导的下包层,低成本的聚甲基丙烯酸甲脂-甲基丙烯酸 环氧丙酯共聚物(P(MMA-GMA))作为芯层和上包层,利用束 传播法模拟和优化Y分支波导的设计,通过光刻、刻蚀和蒸发等传统半导体工艺进行器件制 备。实验测得开关插入损耗为12dB, 消光比为18dB,方波驱动的上升和下降响应时间均为200μs。实验结果表明,SiO₂/聚 合物复合波导结构可有效提高热场的扩散速度和折射率调节效率,减小开关的响应时间。     

Characterization of ultra-thin SiO2 by capacitance-voltage and charge pumping measurements

In this paper, we present results on electrical measurements of ultra thin SiO₂ layers (from 3.5 nm down to 1.7 nm), used as gate dielectric in metal-oxide-semiconductors (MOS) devices. Capacitance-voltage (C-V) measurements and simulations on MOS capacitors have been used for extracting the electrical oxide thickness. The SiO₂/Si interface and oxide quality have been analyzed by charge pumping (CP) measurements. The mean interface traps density is measured by 2-level CP, and the energy distribution within the semiconductor bandgap of these traps are investigated by 3-level charge pumping measurements. A comparison of the energy distribution of the SiO₂/Si interface traps is made using classical and quantum simulations to extract the surface potential as a function of the gate signal. When the gate oxide thickness <3.5 nm, we prove that it is mandatory to take into account the quantum effects to obtain a more accurate energy distribution of the SiO₂/Si interface traps. We also explain the increase of the apparent interface traps density measured by 2-levels CP with the increase of the oxide thickness, for transistors made from the same technological process.     

Charging effects in CdSe nanocrystals embedded in SiO2 matrix produced by rf magnetron sputtering

Charging effects in CdSe nanocrystals embedded in SiO₂ matrix fabricated by rf magnetron co-sputtering technique were electrically characterized by means of capacitance-voltage (C-V) combined with current-voltage (I-V). The presence of CdSe nanocrystals was demonstrated by X-ray diffraction technique. The average size of nanocrystals was found to be approximately 3 nm. The carriers transport in the CdSe/SiO₂ structure was shown to be a combination of Fowler-Nordheim tunnelling and Poole-Frenkel mechanisms. A memory effect was demonstrated and a retention time was measured.     

Isotropic etch for SiO2 microcantilever release with ICP system

Inductively coupled plasma (ICP) system has been widely used for anisotropic silicon etching because it offers high aspect ratio with a vertical side wall. The isotropic etching capability of the ICP system, however, has not gained much attention, even though it possesses advantages in profile control and high etching rate over wet isotropic etching or conventional RIE (reactive ion etching). We report here an isotropic dry etching process to release microcantilever beams. Investigations have covered chamber pressure, plasma source power, substrate power, SF₆ (sulfur hexafluoride) flow rate relating to Si etching rate, undercutting rate, and isotropic ratio. The SiO₂ (silicon dioxide) cantilevers were successfully released from the Si substrate and the optimized silicon etching rate was 9.1 μm per minute. The etching profiles were analyzed by scanning electron micrographs (SEM).