Growth Behavior of Cubic Boron Nitride Films in a Two‐Step Process: Changing Bias Voltage,Gas Composition,and Substrate Temperature

In the deposition of cubic boron nitride (cBN) films by DC‐bias‐assisted DC jet chemical vapor deposition in an Ar–N₂–BF₃–H₂ gas system, the balance between growth and etching and its relation to the deposition conditions were investigated. A two‐step process was designed to optimize the nucleation and growth separately, and a critical bias voltage for the growth of cBN after nucleation was observed. It was found that etching occurred when the bias voltage was below this critical value. Under optimized conditions, the crystallinity and crystal size of the cBN films were improved during the second step. Furthermore, cBN films showing clear crystal facets were obtained.     

Simulation and fabrication of high voltage AlGaN/GaN based Schottky diodes with field plate edge termination

In this paper, we report the breakdown voltage (BV) of AlGaN/GaN based Schottky diodes with field plate edge termination. Simulation and fabrication of AlGaN/GaN Schottky diodes were carried out. The simulations were performed using the commercial 2-D device simulator DESSIS. From the simulations, it is found that for a given gate-Ohmic distance (L_gd) of 10 μm, 2DEG of 1 × 10¹³ cm⁻² and field plate length (L_FP) of 2.5 μm, highest BV can be obtained for a silicon nitride thickness of 8000 Å and this BV value is more than 5 times that for a Schottky diode without field plate. The breakdown voltages were also simulated for different field plate lengths. The BV values obtained on the fabricated Schottky diodes are compared with the simulation data and the experimental results follow the trend obtained from the simulation. Simulations were also carried out on a Schottky diode with field plate placed over a stepped insulator with L_gd = 10 μm, L_FP = 5 μm and 2DEG = 1 × 10¹³ cm⁻² and the obtained BV values are about 7 times that without field plate.     

Analysis of electronic parameters and interface states of boron dispersed triethanolamine/p-Si structure by AFM, I-V, C-V-f and G/ω-V-f techniques

The electronic parameters and interface state properties of boron dispersed triethanolamine/p-Si structure have been investigated by atomic force microscopy, I-V, C-V-f and G/ω-V-f techniques. The surface topography and phase image of the TEA-B film deposited onto p-Si substrate were analyzed by atomic force microscopy. The atomic force microscopy results show a homogenous distribution of boron particles in triethanolamine film. The electronic parameters (barrier height, ideality factor and average series resistance) obtained from I-V characteristics of the diode are 0.81 eV, 2.07 and 5.04 kΩ, respectively. The interface state density of the diode was found to be 2.54 × 10¹⁰ eV⁻ cm⁻² under V_g = 0. The obtained D_it values obtained from C-V and G/ω measurements are in agreement with each other. The profile of series resistance dependent on voltage and frequency confirms the presence of interface states in boron dispersed triethanolamine/p-Si structure. It is evaluated that the boron dispersed triethanolamine controls the electronic parameters and interface properties of conventional Al/p-Si diode.     

Tandem small molecule organic photovoltaic cells with broad spectral response up to 1 μm and a high open-circuit voltage

We report a series-connected small molecule tandem photovoltaic cell utilizing two donors with complementary photovoltaic characteristics, lead phthalocyanine (PbPc) in the front subcell and boron subphthalocyanine chloride (SubPc) in the back subcell, to achieve both near infrared (NIR) response up to 1 μm and high open-circuit voltage (V_OC) of more than 1.5 V in the same device. We find that the C₆₀ layer thickness in the front subcell has a critical impact on the overall optical structure and photovoltaic performance of the tandem device. By combining transfer matrix calculations with subcell-selective spectral measurements, we are able to tune the optical field distribution inside the active layers and increase the photocurrent outputs from both subcells, leading to EQE > 30% over the wavelength range 400 nm < λ < 900 nm. This optimized tandem cell exhibits J_SC = (5.5 ± 0.1) mA/cm², fill factor = 0.54, V_OC = 1.53 V, and a power conversion efficiency of (4.5 ± 0.2)%.     

Improved electrical characteristics and reliability of amorphous InGaZnO metal-insulator-semiconductor capacitor with high κ HfOxNy gate dielectric

High κ HfO_xN_y film was deposited on amorphous InGaZnO (a-IGZO) by radio-frequency reactive sputtering using an HfO₂ target in nitrogen plus argon ambience, the electrical characteristics and reliability of a-IGZO metal-insulator-semiconductor (MIS) capacitors were investigated. Experimental results indicate that the nitrogen incorporation into HfO₂ can produce a strong nitride interfacial barrier layer, thus lead to reducing the interface state density, suppressing the hysteresis voltage, and decreasing the gate-leakage current. Improved performance has been achieved for HfO_xN_y gate dielectric a-IGZO MIS capacitors, with a interface state density of 5.1 × 10¹¹ eV⁻¹ cm⁻², a gate-leakage current density of 3.9 × 10⁻⁵ A/cm² at V_fb + 1 V, an equivalent permittivity of 24, and a hysteresis voltage of 105 mV. Moreover, the enhanced reliability of Al/HfO_xN_y/a-IGZO MIS capacitor is observed with a small degradation of electrical characteristics after a high field stressing at 10 MV/cm for 3600 s.     

Low operational voltage and high performance organic field effect memory transistor with solution processed graphene oxide charge storage media

Low voltage organic field effect memory transistors are demonstrated by adapting a hybrid gate dielectric and a solution processed graphene oxide charge trap layer. The hybrid gate dielectric is composed of aluminum oxide (AlO_x) and [8-(11-phenoxy-undecyloxy)-octyl]phosphonic acid (PhO-19-PA) plays an important role of both preventing leakage current from gate electrode and providing an appropriate surface energy to allow for uniform spin-casting of graphene oxide (GO). The hybrid gate dielectric has a breakdown voltage greater than 6 V and capacitance of 0.47 μF/cm². Graphene oxide charge trap layer is spin-cast on top of the hybrid dielectric and has a resulting thickness of approximately 9 nm. The final device structure is Au/Pentacene/PMMA/GO/PhO-19-PA/AlO_x/Al. The memory transistors clearly showed a large hysteresis with a memory window of around 2 V under an applied gate bias from 4 V to −5 V. The stored charge within the graphene oxide charge trap layer was measured to be 2.9 × 10¹² cm⁻². The low voltage memory transistor operated well under constant applied gate voltage and time with varying programming times (pulse duration) and voltage pulses (pulse amplitude). In addition, the drain current (I_ds) after programming and erasing remained in their pristine state after 10⁴ s and are expected to be retained for more than one year.     

Electrical and photovoltaic properties of a n-Si/chitosan/Ag photodiode

The electrical and photovoltaic properties of AuSb/n-Si/chitosan/Ag diode have been investigated. The ideality factor, barrier height and Richardson constant values of the diode at room temperature were found to be 1.91, 0.88 eV and 121.4 A/cm² K², respectively. The ideality factor of the diode is higher than unity, suggesting that the diode shows a non-ideal behaviour due to series resistance and barrier height inhomogeneities. The barrier height and ideality factor values of Ag/CHT/n-Si diode at room temperature are significantly larger than that of the conventional Ag/n-Si Schottky diode. The φ_B value obtained from C-V measurement is higher than that of φ_B value obtained from I-V measurement. The discrepancy between φ_B(C-V) and φ_B(I-V) barrier height values can be explained by Schottky barrier height inhomogeneities. AuSb/n-Si/chitosan/Ag diode indicates a photovoltaic behaviour with open circuit voltage (V_oc = 0.23 V) and short-circuit current density (J_sc = 0.10 μA/cm⁻²) values.     

Liquid crystal electrography: Electric field mapping and detection of peak electric field strength in AlGaN/GaN high electron mobility transistors

The liquid crystal mixture E7, based on cyanobiphenyl, has been successfully employed to map electric field strength and distribution in AlGaN/GaN high electron mobility transistors. Using a transmitted light image through crossed polarizers the optical response of the liquid crystal deposited onto the surface of the devices was recorded as a function of source–drain bias, V_ds. At a critical voltage of 4 V the preferred direction of orientation of the long axes of the liquid crystal molecules in the drain access region aligned with one of the polarizers resulting in reduced transmitted light intensity. This indicates that at this electric field strength molecule orientation in most of the liquid crystal film is dominated by the electric field effect rather than the influence of surface anchoring. The experimental results were compared to device simulations. Electric field strength above the surface at V_ds = 4 V was simulated to reach or exceed 0.006 MV/cm. This electric field is consistent with the field expected for E7 to overcome internal elastic energy. This result illustrates the usefulness of liquid crystals to directly determine and map electric fields in electronic devices, including small electric field strengths.     

Organic nonvolatile memory transistors based on fullerene and an electron-trapping polymer

We report for the first time organic n-type nonvolatile memory transistors based on a fullerene (C₆₀) semiconductor and an electron-trapping polymer, poly(perfluoroalkenyl vinyl ether) (CYTOP). The transistors with a Si++/SiO₂/CYTOP/C₆₀/Al structure show good n-type transistor performance with a threshold voltage (V_th) of 2.8 V and an electron mobility of 0.4 cm² V⁻¹ s⁻¹. Applying gate voltages of 50 or −45 V for about 0.1 s to the devices induces the reversible shifts in their transfer characteristics, which results in a large memory window (ΔV_th) of 10 V. A memory on/off ratio of 10⁵ at a small reading voltage below 5 V and a retention time greater than 10⁵ s are achieved. The memory effect in the transistor is ascribed to electrons trapped at the CYTOP/SiO₂ interface. Because of the use of high-electron-mobility C₆₀, the switching voltages of our memory transistors become significantly lower than those of conventional memory transistors based on pentacene.     

Effect of axial halogen substitution on the performance of subphthalocyanine based organic photovoltaic cells

To probe the influence of molecular dipole on the open circuit voltage (V_OC) of molecular heterojunction organic solar cells, we study axially fluorinated boron subphthalocyanine/fullerene (SubPc-F/C₆₀) junctions. These exhibit an open-circuit voltage V_OC = 1.00 V, a value closer to the HOMO–LUMO offset at the donor–acceptor interface = 1.69 eV than the V_OC = 1.06 V measured for junctions between the archetypal chlorinated SubPc and C₆₀, with corresponding HOMO–LUMO offset = 1.84 eV. Aside from the axial halogen substitution, the two compounds exhibit similar molecular structure and optical absorption. The energy levels and structure of the heteromolecular polaron pair are calculated, and the ideal organic diode model for SubPc-Cl is modified accordingly, successfully reproducing the experimental SubPc-F device characteristics. The reproducible difference in V_OC is attributed to the different electric dipole strength between SubPc-F and SubPc-Cl and its influence on polaron pair dynamics at the heterojunction.     

Mobility enhancement by using silk fibroin in F16CuPc organic thin film transistors

High performance n-type F₁₆CuPc organic thin-film transistors (OTFTs) were fabricated on polyethylene terephthalate (PET) using silk fibroin as the gate dielectric. The average field-effect mobility (μ_FE) value in the saturation regime is 0.39 cm² V⁻¹ s⁻¹ approximately one order of magnitude higher than the reported values in the literature. A typical F₁₆CuPc OTFT exhibits an on/off current ratio of 9.3 × 10², a low threshold voltage of 0.65 V, and a subthreshold swing value of 730 mV/decade. The enhancement of μ_FE results from very good crystal quality of F₁₆CuPc on silk fibroin, supported by grazing incidence X-ray diffraction (GIXD) data.     

LP-MOCVD growth of ternary BxGa1−xAs epilayers on (0 0 1)GaAs substrates using TEB, TMGa and AsH3

Zinc-blende B_xGa_1−xAs alloys have been successfully grown on exactly oriented (0 0 1)GaAs substrates using triethylboron, trimethylgallium and arsine sources. The growth has been accomplished in a vertical low-pressure metalorganic chemical vapor deposition (LP-MOCVD) reactor. Boron incorporation behaviors have been extensively studied as a function of growth temperature and gas-phase boron mole fraction. The evolution of surface morphology was also observed.The maximum boron composition of 5.8% is obtained at the optimum growth temperature of 580 °C. RMS roughness over the surface area of 1×1 μm² is only 0.17 nm at such growth conditions. Based on the experimental results, it has been clearly shown that boron incorporation will decrease significantly at higher temperature (>610 °C) or at much lower temperature (?550 °C).     

Influence of rapid thermal annealing temperature on structure and electrical properties of high permittivity HfTiO thin film used in MOSFET

HfTiO thin films were prepared by r.f. magnetron co-sputtering on Si substrate. To improve the electrical properties, HfTiO thin films were post heated by rapid thermal annealing (RTA) at 400 °C, 500 °C, 600 °C and 700 °C in nitrogen. It was found that the film is amorphous below 700 °C and at 700 °C monoclinic phase HfO₂ has occurred. With the increase of the annealing temperature, the film becomes denser and the refractive index increases. By electrical measurements, we found at 500 °C annealed condition, the film has the best electrical property with the largest dielectric constant of 44.0 and the lowest leakage current of 1.81 × 10⁻⁷ A/cm², which mainly corresponds to the improved microstructure of HfTiO thin film. Using the film annealed at 500 °C as the replacement of SiO₂ dielectric layer in MOSFET, combining with TiAlN metal electrode, a 10 μm gate-length MOSFET fabricated by three-step photolithography processes. From the transfer (I_DS–V_G) and output (I_DS–V_DS) characteristics, it shows a good transistor performance with a threshold voltage (V_th) of 1.6 V, a maximum drain current (I_ds) of 9 × 10⁻⁴ A, and a maximum transconductance (G_m) of 2.2 × 10⁻⁵ S.     

Cubic GaN/AlGaN Schottky-barrier devices on 3C-SiC substrates

In this work, we focus on the fabrication of cubic GaN based Schottky-barrier devices (SBDs) and measured current voltage (I-V) characteristics and the critical field for electronic breakdown. Phase-pure cubic GaN and c-Al_xGa_1 − xN/GaN structures were grown by plasma assisted molecular beam epitaxy (MBE) on 200 μm thick free-standing 3C-SiC (1 0 0) substrates, which were produced by HOYA Advanced Semiconductor Technologies Co., Ltd. The thickness of the c-GaN and c-Al_0.3Ga_0.7N epilayers were about 600 and 30 nm, respectively. Ni/In Schottky contacts 300 μm in diameter were produced on c-GaN and c-Al_0.3Ga_0.7N/GaN structures by thermal evaporation using contact lithography. A clear rectifying behavior was measured in our SBDs and the I-V behavior was analyzed in detail, indicating the formation of a thin surface barrier at the Ni-GaN interface. Annealing of the Ni Schottky contacts in air at 200 °C reduces the leakage current by three orders of magnitude. The doping density dependence of breakdown voltages derived from the reverse breakdown voltage characteristics of c-GaN SBDs is investigated. The experimental values of breakdown voltage in c-GaN are in good agreement with theoretical values and show the same dependence on doping level as in hexagonal GaN. From our experimental data, we extrapolate a blocking voltage of 600 V in c-GaN films with a doping level N_D = 5 × 10¹⁵ cm⁻³.     

Effect of a silicon nitride buffer layer on the electrical properties of tantalum pentoxide films

Ta₂O₅ films with a buffer layer of silicon nitride of various thicknesses were deposited on Si substrate by reactive sputtering and submitted to annealing at 700 °C in nitrogen atmosphere. The microstructure and the electrical properties of thin films were studied. It was found that with a buffer layer of silicon nitride the electrical properties of Si_xN_y/Ta₂O₅ film can be improved than Ta₂O₅ film. When the thickness of the buffer layer was 3 nm, the Si_xN_y/Ta₂O₅ film has the highest dielectric constant of 27.4 and the lowest leakage current density of 4.61 × 10⁻⁵ A/cm² (at −1 V). For the Si_xN_y (3 nm)/Ta₂O₅ film, the conduction mechanism of leakage current was also analyzed and showed four types of conduction mechanisms at different applied voltages.     

An oligothiophene dye with triphenylamine as side chains for efficient dye-sensitized solar cells

A novel oligothiophene-cyanoacrylic acid photosensitizer with two triphenylamine side chains (7T-2TPA) is designed and synthesized for dye-sensitized solar cells. 7T-2TPA exhibits broad (250-600 nm) and strong absorption (ε = 5.0 × 10⁴ L mol⁻¹ cm⁻¹ at 496 nm). The optical band gap (E_g) is estimated from the onset absorption edge to be 2.07 eV. The oxidation potential E_ox and reduction potential E_red vs NHE of the dye is 0.93 and −1.14 V, respectively. Dye-sensitized solar cell (DSSC) based on 7T-2TPA exhibits an open-circuit voltage (V_oc) of 724 mV, a short-circuit current density (J_sc) of 16.28 mA cm⁻², a fill factor (FF) of 0.684 and a power conversion efficiency of 8.06%. The efficiency of 8.06% is similar to that for widely used N719-based cell fabricated and measured under the same conditions.     

A new inverter-based charge pump circuit with high conversion ratio and high power efficiency

The current paper presents a new inverter-based charge pump circuit with high conversion ratio and high power efficiency. The proposed charge pump, which consists of a PMOS pass transistor, inverter-based switching transistors, and capacitors, can improve output voltage and conversion ratio of the circuit. The proposed charge pump was fabricated with TSMC 0.35 μm 2P4M CMOS technology. The chip area without pads is only 0.87 mm×0.65 mm. The measured results show that the output voltage of the four-stage charge pump circuit with 1.8 V power supply voltage (V_DD=1.8 V) can be pumped up to 8.2 V. The proposed charge pump circuit achieves efficiency of 60% at 80 μA.     

Ruthenium oxide metal nanocrystal capacitors with high-κ dielectric tunneling barriers for nanoscale nonvolatile memory device applications

The ruthenium oxide metal nanocrystals embedded in high-κ HfO₂/Al₂O₃ dielectric tunneling barriers prepared by atomic layer deposition in the n-Si/SiO₂/HfO₂/ruthenium oxide (RuO_x)/Al₂O₃/Pt memory capacitors with a small equivalent oxide thickness of 8.6 ± 0.5 nm have been investigated. The RuO_x metal nanocrystals in a memory capacitor structure observed by high-resolution transmission electron microscopy show a small average diameter of ∼7 nm with high-density of >1.0 × 10¹²/cm² and thickness of ∼3 nm. The ruthenium oxide nanocrystals composed with RuO₂ and RuO₃ elements are confirmed by X-ray photoelectron spectroscopy. The enhanced memory characteristics such as a large memory window of ΔV ≈ 12.2 V at a sweeping gate voltage of ±10 V and ΔV ≈ 5.2 V at a small sweeping gate voltage of ±5 V, highly uniform and reproducible, a large electron (or hole) storage density of ∼1 × 10¹³/cm², low charge loss of <7% (ΔV ≈ 4.2 V) after 1 × 10⁴ s of retention time are observed due to the formation of RuO_x nanocrystals after the annealing treatment and design of the memory structure. The charge storage in the RuO_x nanocrystals under a small voltage operation (∼5 V) is due to the modified Fowler-Nordheim tunneling mechanism. This memory structure can be useful for future nanoscale nonvolatile memory device applications.     

Pentacene thin-film transistors with sol-gel derived amorphous Ba0.6Sr0.4TiO3 gate dielectric

An amorphous Ba_0.6Sr_0.4TiO₃ (BST) film with the thickness of 200 nm was deposited on indium-tin-oxide (ITO)-coated glass substrate through sol-gel route and post-annealing at 500 °C. The dielectric constant of the BST film was determined to be 20.6 at 100 kHz by measuring the Ag/BST/ITO parallel plate capacitor, and no dielectric tunability was observed with the bias voltage varying from −5 to 5 V. The BST film shows a dense and uniform microstructure as well as a smooth surface with the root-mean-square (RMS) roughness of about 1.4 nm. The leakage current density was found to be 3.5 × 10⁻⁸ A/cm² at an applied voltage of −5 V. The transmittance of the BST/ITO/glass structure is more than 70% in the visible region. Pentacene based transistor using the as-prepared BST film as gate insulator exhibits a low threshold voltage of −1.3 V, the saturation field-effect mobility of 0.68 cm²/Vs, and the current on/off ratio of 3.6 × 10⁵. The results indicate that the sol-gel derived BST film is a promising high-k gate dielectric for large-area transparent organic transistor arrays on glass substrate.     

Enhanced performance of dye-sensitized solar cells with novel 2,6-diphenyl-4H-pyranylidene dyes

Novel 2,6-diphenyl-4H-pyranylidene derivatives were designed and synthesized as dyes for dye-sensitized solar cells (DSSC). Dyes 2a, b with a phenyl substituent showed high DSSC energy conversion efficiencies of 5.3% (J_sc = 10.3 mA/cm², V_oc = 0.72 V, FF = 0.72) and 4.7% (J_sc = 8.9 mA/cm², V_oc = 0.73 V, FF = 0.72) at 100 mW/cm² under simulated AM 1.5 G solar light conditions. These values are twice better than that of dye 1 without the phenyl substituent under the same conditions. Both the photocurrent density (J_sc) and open circuit voltage (V_oc) of DSSCs based on dyes 2a, b are increased compared with 1. It can be attributed to their twisted structures, absorption abilities and proper energy levels. This result shows that the tetraphenylpyranylidene is a promising electron-donor unit for high-efficiency DSSCs.