FPGA-based System for Real-Time Video Texture Analysis

This paper describes a novel system for real-time video texture analysis. The system utilizes hardware to extract second-order statistical features from video frames. These features are based on the Gray Level Co-occurrence Matrix (GLCM) and describe the textural content of the video frames. They can be used in a variety of video analysis and pattern recognition applications, such as remote sensing, industrial and medical. The hardware is implemented on a Virtex-XCV2000E-6 FPGA programmed in VHDL. It is based on an architecture that exploits the symmetry and the sparseness of the GLCM and calculates the features using integer and fixed point arithmetic. Moreover, it integrates an efficient algorithm for fast and accurate logarithm approximation, required in feature calculations. The software handles the video frame transfers from/to the hardware and executes only complementary floating point operations. The performance of the proposed system was experimentally evaluated using standard test video clips. The system was implemented and tested and its performance reached 133 and 532 fps for the analysis of CIF and QCIF video frames respectively. Compared to the state of the art GLCM feature extraction systems, the proposed system provides more efficient use of the memory bandwidth and the FPGA resources, in addition to higher processing throughput, that results in real time operation. Furthermore, its fundamental units can be used in any hardware application that requires sparse matrix representation or accurate and efficient logarithm estimation.

数字阵列雷达接收链路的噪声检测方法

在数字阵列雷达中,接收通道的性能直接影响着雷达整机的探测性能。接收链路中有模拟电路、数字电路,每个环节都可能出现噪声异常抬高现象,造成接收链路的性能指标下降,影响雷达系统的性能。文中依据雷达接收链路架构以及接收链路的噪声组成,分析了链路中噪声异常产生的影响,并以模/数(A/D)芯片噪声异常为例对雷达性能影响进行了仿真。基于噪声检测原理和器件特征,给出了数字阵列雷达接收链路噪声检测的两种方法,包括绝对值判别法和通道间比幅法,可实时定位故障链路,保证雷达任务顺利进行。     

基于FPGA的SER/DES在量子密码通讯中的应用

在远距离量子密钥分发(QKD)系统中,使用基于场可编程门阵列(FPGA,field programmable gatearray)的串行器/解串器(SER/DES,serializer/deserializer)技术完成了500 Mbit/s的量子传输速率,利用低频(2 MHz)的同步信号完成对发射方和接收方的同步。根据QKD实验的需要,完成了信号甄别、伪随机数产生器、时间同步和数据编码等功能,成功搭建了基于诱骗态的远距离QKD系统。     

基于FPGA的160路数据采集系统设计

目前,数据采集系统对采样率、分辨率和抗干扰能力的要求越来越高.尤其是在典型的多路采集 多路开关 单路A/D转换器的数据采集中,采集速度受到限制.为此,介绍了一种基于现场可编程门阵列(FPGA)的高速多路数据采集系统设计和实现.采用模拟开关级联的方法,有效地达到了160路采集速度.采用该方法设计的采集卡能有效完成多路同步高速数据采集任务.且成功地用于某装置的输出信号检测.     

Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems

Dynamic Partial Reconfiguration (DPR) enables resource sharing in FPGA-based systems. It can also be used for the mitigation of aging-related permanent faults by increasing the number of redundant Partially Reconfigurable Regions (PRRs). Normally, these PRRs are able to host any of the Partially Reconfigurable Modules (PRMs), or tasks, at one particular instance. This kind of system is called homogeneous. However, the FPGA resource constraints limit the amount of homogeneous redundancy that can be used and hence affect the lifetime of the system. This issue can be addressed by utilizing the heterogeneous approach where each PRR now only hosts a subset of the tasks. Further, the deadlines of the applications must also be taken care of in the design phase to decide the mapping and scheduling of tasks to PRRs. To this end, we propose an application-specific multi-objective system-level design methodology to determine the appropriate number of PRRs and the mapping and scheduling of tasks to the PRRs. Specifically, we propose a lifetime-aware scheduling method that maximizes the system's mean time to failure (MTTF) with different tolerances in the makespan specification of an application. We use the scheduler along with an automated floorplanner for design space exploration at design-time to generate a feasible heterogeneous PRR-based system. Our experiments show that the heterogeneous systems can offer more than 2x lifetime improvement over homogeneous ones. It also offers better scaling with increased tolerance in makespan specification.     

FPGA-based Monte Carlo simulation for fault tree analysis

The reliability analysis of critical systems is often performed using fault-tree analysis. Fault trees are analyzed using analytic approaches or Monte Carlo simulation. The usage of the analytic approaches is limited in few models and certain kinds of distributions. In contrast to the analytic approaches, Monte Carlo simulation can be broadly used. However, Monte Carlo simulation is time-consuming because of the intensive computations. This is because an extremely large number of simulated samples may be needed to estimate the reliability parameters at a high level of confidence.In this paper, a tree model, called Time-to-Failure tree, has been presented, which can be used to accelerate the Monte Carlo simulation of fault trees. The time-to-failure tree of a system shows the relationship between the time to failure of the system and the times to failures of its components. Static and dynamic fault trees can be easily transformed into time-to-failure trees. Each time-to-failure tree can be implemented as a pipelined digital circuit, which can be synthesized to a field programmable gate array (FPGA). In this way, Monte Carlo simulation can be significantly accelerated. The performance analysis of the method shows that the speed-up grows with the size of the fault trees. Experimental results for some benchmark fault trees show that this method can be about 471 times faster than software-based Monte Carlo simulation.     

Comparison of practical methods for an efficient FPGA implementation of STAP

This study investigated and compared the practical methods used for the efficient Field- Programmable Gate Array (FPGA) implementation of space-time adaptive processing (STAP). The most important part of calculating the STAP weights is the QR decomposition (QRD), which can be implemented using the modified Gram-Schmidt (MGS) algorithm. The results show that the method that uses QRD with less computational burden leads to a more effective implementation. Its structure was parameterised with the vector size to create a trade-off between the hardware and performance factors. For this purpose, QRD-MGS algorithm was first modified to increase the speed, and then the STAP weight vector was calculated. The implementation results show that decreasing the vector size decreases the resource utilisation, computational burden and the consumption power. While the computation time increases slightly, the updated rate of the STAP weights is maintained. For example, the STAP weights in a system with 6 antenna arrays, 10 received pulses and 200 range samples computed in 262 µs using a vector size of 17 on the Arria10 FPGA that has a maximum of 155 µs correlates to the QRD-MGS algorithm and 107 µs correlates to the other parts. Therefore, QRD-MGS algorithm is the most important component of the calculation of the STAP weight vector, and its simplification leads to efficient implementation.     

基于FPGA的无刷直流电机数字控制方法研究

为了实现简单且高效的无刷直流电机（BLDC）驱动系统,本文提出了一种简单新型的基于FPGA的数字脉冲宽度调制（PWM）控制器的模型和匹配的控制算法,该控制器将梯形磁通分布的BLDC电机看作是一个数字系统,通过低功率和高功率的交替使用进行速度调节,非常便于设计实现。此外,提出的设计只使用直流环节的一个电流传感器,减少了成本和硬件的复杂性。并通过模拟实验对提出的控制方法进行了证实,结果显示提出方法的最大误差保持低于5%。因此,这种控制技术非常适合不需要高精度的应用。     

VHDL实现PCM码解调程序模块设计

依据VHDL程序设计出针对现场可编程门阵列(FPGA)的脉冲编码调制(PCM)码解调电路.解调数据过程分为位同步、字节同步、帧同步和串并转换,并对相关程序模块进行仿真.通过调试硬件电路,验证了该PCM码解调系统所实现的功能.     

基于FPGA的模糊跨周调制模式的实现

文章提出了一种基于现场可编程门阵列(FPGA)的功率变换的模糊型跨周调制模式(FPSM,Fuzzy Pulse Skip Modulation)的实现方法,并将其应用于单端反激式开关电源的功率变换系统.实验研究表明,FPSM除具有跨周调制(PSM)效率高、响应速度快、鲁棒性强等优点外,较之PSM,它还能有效地降低变换器的输出电压纹波,消除音频噪声的影响.     

FPGA最小系统的数字电源设计

文章介绍了一种FPGA最小系统的数字电源设计方法。FPGA最小系统的数字电源包括FPGA端口电压、内核电压、EEPROM配置芯片内核电压等部分。对数字电源产生、软启动、上电时序控制进行了设计改进,可以有效避免数字电源设计不合理造成的FPGA最小系统工作不稳定的设计隐患,对于稳定可靠的FPGA最小系统设计具有重要意义。     

Frame buffer-less stream processor for accurate real-time interest point detection

A high performance HW accelerator is proposed to extract and refine the Interest Points from images, by accurately calculating the Difference-of-Gaussian and using refinement algorithms from the SIFT method. Unique features of the accelerator consist in an accuracy comparable to the CDVS Test Model, reference software; in the capability to process the incoming pixel in streaming order to minimize the amount of embedded memory and avoid external frame buffers; in the possibility to configure the processor with different area/speed ratios. FPGA synthesis on a Xilinx XC7V2000T returns a maximum operation frequency up of 309 MHz at the fastest corner. Standard cell synthesis with the STMICROELECTRONICS FDSOI 28 nm technology, de-congestioned by the use of DPREG memories in place of SRAM, gives a maximum frequency of 1.2 GHz and a power dissipation of about 1 W at the typical conditions.     

Investigation of Lifting-Based Hardware Architectures for Discrete Wavelet Transform

This paper investigates efficient hardware architectures for implementation of 1-D and 2-D discrete wavelet transforms (DWTs). The architectures are based on the lifting scheme. We propose a general structure to minimize the number of multipliers and adders for 1-D DWTs. Compared to previous conventional architectures, the architecture presented here is more efficient in terms of the required arithmetic units. Moreover, we describe a new frame scan method for a block-based 2-D DWT structure which provides a flexible trade-off between the required internal memory size and external memory access. In contrast, other 2-D DWT structures require a fixed memory size.     

ALO: An ultrasound system for localization and orientation based on angles

This paper presents a low cost system based on ultrasound transducers to obtain the localization and orientation information of a mobile node, such as a robot, in a 2D indoor space. The system applies a new differential time of arrival (DTOA) technique with reduced computational cost, which is called ALO (angle localization and orientation). Instead of directly calculating its position, the system calculates the direction of arrival of the received ultrasonic signal and, through it, its position and orientation. A prototype of a robot has been built in order to show the validity of the method through experimental results.     

On chip novel video streaming system for bi-network multicasting protocols

In the past three decades, tremendous Ethernet-related research has been done, which has led to today's ubiquitous Ethernet technology. On the other hand, with the emergence of new network needs, a new protocol, the IEEE 1394 standard serial bus (or Firewire) was introduced. Firewire is suitable for high-quality audio/video applications which do not perform well in the best-effort-based Ethernet technology. However, since Firewire is a serial bus, it has harsh cable length limitations as compared to Ethernet capabilities.In this paper, we present a novel on-chip system that receives Firewire video and transmits it in multicast mode using Ethernet protocol. A major advantage of this novel system is to utilize the existing Ethernet infrastructure to extend the range of Firewire video streaming to reach remote nodes and make it even accessible to nodes with a single Ethernet interface. This will have tremendous impact on Firewire applications such as deploying Firewire cameras in big-scale security-sensitive buildings or industrial facilities with image-based remote quality control.This novel chip utilizes the concept of Ethernet multicasting transmission mode for video streaming. The proposed chip design converts the IEEE 1394 isochronous traffic to the Ethernet multicast frame format via two off-chip asynchronous write and read buffers.The goal of this research is to design an On Chip Novel Video Streaming System that avoids performance bottlenecks in the software protocol conversion of these two important network protocols. The author decided to study these two networks because of their broad use and cable power provisioning capabilities. The novel system design is implemented using a customized field programmable gate array (FPGA), which enables the integration of various system components on one chip. The designed prototype is studied using both network monitoring tools and analytical techniques, to verify its function and compare it with the existing approaches.Performance measures show that the On Chip Novel Video Streaming System consumes less than 21 mW of power for 100 Mbps and 82 mW of power for 1 Gbps, and utilizes 57% of a Xilinx Spartan 2-100E-6FT256 FPGA resources. Hence, it is possible to incorporate further extensions. Experimental results show that 88% of the network utilization can be achieved, due to the use of the customized, FPGA-based design of bi-network traffic conversion.     

TD-LTE多带宽数字下变频设计与FPGA实现

分时长期演进( TD-LTE )系统为了满足各种环境的需要,支持6种不同的带宽和基带速率。为了满足TD-LTE系统多带宽和多速率的要求,设计了一种兼容TD-LTE多带宽和多速率的多带宽数字下变频方案。方案中采用了时分复用技术、抽取滤波的合理搭配和高性能滤波器实现了资源优化和输出信号的高信噪比。此外,对数字混频器和抗混叠滤波器进行改进,设计出了基于坐标旋转数字计算法( CORDIC)的流水线型混频器和高速并行可配置滤波器。软件仿真和硬件测试证明了TD-LTE多带宽数字下变频的正确性,且具有灵活性、高性能和低资源消耗的特点以及较高的工程实用价值。     

FPGA技术及其发展趋势

FPGA在电子设计领域得到广泛的应用，并成为实现电子系统的一种很重要的手段。本文主要介绍了FPGA的特点、设计流程及其发展趋势。     

一种新型DC/DC变换器实验系统开发

为强化DC/DC变换技术的实践教学,基于多绕组变压器和反激电路原理,开发一套DC/DC变换器教学系统。设计变换器的拓扑结构,分析工作原理及控制策略,计算变换器系统参数,建立数字仿真模型,设计变换器主电路、输出电压采样电路、开关管驱动电路等来搭建变换器实验平台。实验教学应用表明,该变换器实现宽输入/输出电压范围功能的同时,能够提高学生的电力电子技术综合实践能力。     

稀疏多带信号的压缩采样技术的研究

实现宽带压缩采样的结构有多种类型,在分析调制宽带转换器的采样结构的原理的基础上,针对稀疏多带信号的压缩采样,搭建了四通道的宽带压缩采样系统的原型系统平台,其中,混频调制信号是现场可编程门阵列硬件电路产生的序列。采用稀疏多频带信号作为系统的输入测试信号,并且利用另一已知的稀疏多带信号作为系统的同步信号,对宽带压缩采样原型系统进行系统仿真。该系统中的混频调制信号容易生成、实现结构简单、参数设置灵活。软件仿真及硬件测试,验证了该宽带压缩采样系统的硬件平台的正确性和可行性。     

基于FPGA的AES密码协处理器的设计和实现

文章基于FPGA设计了一种能完成AES算法加密的密码协处理器，设计中利用VirtexⅡ系列FPGA的结构特点，对AES算法的实现做了优化。实验证明，这种实现方式用较少的电路资源达到了较高的数据吞吐率。该密码协处理器还提供了和ARM处理器的接口逻辑，实现了用于加／解密和数据输入输出的协处理器指令．作为ARM微处理器指令集的扩展，大大提高了嵌入式系统处理数据加／解的效率，实现数据的安全传输。