FPGA-based System for Real-Time Video Texture Analysis

This paper describes a novel system for real-time video texture analysis. The system utilizes hardware to extract second-order statistical features from video frames. These features are based on the Gray Level Co-occurrence Matrix (GLCM) and describe the textural content of the video frames. They can be used in a variety of video analysis and pattern recognition applications, such as remote sensing, industrial and medical. The hardware is implemented on a Virtex-XCV2000E-6 FPGA programmed in VHDL. It is based on an architecture that exploits the symmetry and the sparseness of the GLCM and calculates the features using integer and fixed point arithmetic. Moreover, it integrates an efficient algorithm for fast and accurate logarithm approximation, required in feature calculations. The software handles the video frame transfers from/to the hardware and executes only complementary floating point operations. The performance of the proposed system was experimentally evaluated using standard test video clips. The system was implemented and tested and its performance reached 133 and 532 fps for the analysis of CIF and QCIF video frames respectively. Compared to the state of the art GLCM feature extraction systems, the proposed system provides more efficient use of the memory bandwidth and the FPGA resources, in addition to higher processing throughput, that results in real time operation. Furthermore, its fundamental units can be used in any hardware application that requires sparse matrix representation or accurate and efficient logarithm estimation.

基于FPGA的160路数据采集系统设计

目前,数据采集系统对采样率、分辨率和抗干扰能力的要求越来越高.尤其是在典型的多路采集 多路开关 单路A/D转换器的数据采集中,采集速度受到限制.为此,介绍了一种基于现场可编程门阵列(FPGA)的高速多路数据采集系统设计和实现.采用模拟开关级联的方法,有效地达到了160路采集速度.采用该方法设计的采集卡能有效完成多路同步高速数据采集任务.且成功地用于某装置的输出信号检测.     

FPGA-based Monte Carlo simulation for fault tree analysis

The reliability analysis of critical systems is often performed using fault-tree analysis. Fault trees are analyzed using analytic approaches or Monte Carlo simulation. The usage of the analytic approaches is limited in few models and certain kinds of distributions. In contrast to the analytic approaches, Monte Carlo simulation can be broadly used. However, Monte Carlo simulation is time-consuming because of the intensive computations. This is because an extremely large number of simulated samples may be needed to estimate the reliability parameters at a high level of confidence.In this paper, a tree model, called Time-to-Failure tree, has been presented, which can be used to accelerate the Monte Carlo simulation of fault trees. The time-to-failure tree of a system shows the relationship between the time to failure of the system and the times to failures of its components. Static and dynamic fault trees can be easily transformed into time-to-failure trees. Each time-to-failure tree can be implemented as a pipelined digital circuit, which can be synthesized to a field programmable gate array (FPGA). In this way, Monte Carlo simulation can be significantly accelerated. The performance analysis of the method shows that the speed-up grows with the size of the fault trees. Experimental results for some benchmark fault trees show that this method can be about 471 times faster than software-based Monte Carlo simulation.     

Comparison of practical methods for an efficient FPGA implementation of STAP

This study investigated and compared the practical methods used for the efficient Field- Programmable Gate Array (FPGA) implementation of space-time adaptive processing (STAP). The most important part of calculating the STAP weights is the QR decomposition (QRD), which can be implemented using the modified Gram-Schmidt (MGS) algorithm. The results show that the method that uses QRD with less computational burden leads to a more effective implementation. Its structure was parameterised with the vector size to create a trade-off between the hardware and performance factors. For this purpose, QRD-MGS algorithm was first modified to increase the speed, and then the STAP weight vector was calculated. The implementation results show that decreasing the vector size decreases the resource utilisation, computational burden and the consumption power. While the computation time increases slightly, the updated rate of the STAP weights is maintained. For example, the STAP weights in a system with 6 antenna arrays, 10 received pulses and 200 range samples computed in 262 µs using a vector size of 17 on the Arria10 FPGA that has a maximum of 155 µs correlates to the QRD-MGS algorithm and 107 µs correlates to the other parts. Therefore, QRD-MGS algorithm is the most important component of the calculation of the STAP weight vector, and its simplification leads to efficient implementation.     

VHDL实现PCM码解调程序模块设计

依据VHDL程序设计出针对现场可编程门阵列(FPGA)的脉冲编码调制(PCM)码解调电路.解调数据过程分为位同步、字节同步、帧同步和串并转换,并对相关程序模块进行仿真.通过调试硬件电路,验证了该PCM码解调系统所实现的功能.     

基于FPGA的模糊跨周调制模式的实现

文章提出了一种基于现场可编程门阵列(FPGA)的功率变换的模糊型跨周调制模式(FPSM,Fuzzy Pulse Skip Modulation)的实现方法,并将其应用于单端反激式开关电源的功率变换系统.实验研究表明,FPSM除具有跨周调制(PSM)效率高、响应速度快、鲁棒性强等优点外,较之PSM,它还能有效地降低变换器的输出电压纹波,消除音频噪声的影响.     

数字阵列雷达接收链路的噪声检测方法

在数字阵列雷达中,接收通道的性能直接影响着雷达整机的探测性能。接收链路中有模拟电路、数字电路,每个环节都可能出现噪声异常抬高现象,造成接收链路的性能指标下降,影响雷达系统的性能。文中依据雷达接收链路架构以及接收链路的噪声组成,分析了链路中噪声异常产生的影响,并以模/数(A/D)芯片噪声异常为例对雷达性能影响进行了仿真。基于噪声检测原理和器件特征,给出了数字阵列雷达接收链路噪声检测的两种方法,包括绝对值判别法和通道间比幅法,可实时定位故障链路,保证雷达任务顺利进行。     

Frame buffer-less stream processor for accurate real-time interest point detection

A high performance HW accelerator is proposed to extract and refine the Interest Points from images, by accurately calculating the Difference-of-Gaussian and using refinement algorithms from the SIFT method. Unique features of the accelerator consist in an accuracy comparable to the CDVS Test Model, reference software; in the capability to process the incoming pixel in streaming order to minimize the amount of embedded memory and avoid external frame buffers; in the possibility to configure the processor with different area/speed ratios. FPGA synthesis on a Xilinx XC7V2000T returns a maximum operation frequency up of 309 MHz at the fastest corner. Standard cell synthesis with the STMICROELECTRONICS FDSOI 28 nm technology, de-congestioned by the use of DPREG memories in place of SRAM, gives a maximum frequency of 1.2 GHz and a power dissipation of about 1 W at the typical conditions.     

Investigation of Lifting-Based Hardware Architectures for Discrete Wavelet Transform

This paper investigates efficient hardware architectures for implementation of 1-D and 2-D discrete wavelet transforms (DWTs). The architectures are based on the lifting scheme. We propose a general structure to minimize the number of multipliers and adders for 1-D DWTs. Compared to previous conventional architectures, the architecture presented here is more efficient in terms of the required arithmetic units. Moreover, we describe a new frame scan method for a block-based 2-D DWT structure which provides a flexible trade-off between the required internal memory size and external memory access. In contrast, other 2-D DWT structures require a fixed memory size.     

ALO: An ultrasound system for localization and orientation based on angles

This paper presents a low cost system based on ultrasound transducers to obtain the localization and orientation information of a mobile node, such as a robot, in a 2D indoor space. The system applies a new differential time of arrival (DTOA) technique with reduced computational cost, which is called ALO (angle localization and orientation). Instead of directly calculating its position, the system calculates the direction of arrival of the received ultrasonic signal and, through it, its position and orientation. A prototype of a robot has been built in order to show the validity of the method through experimental results.     

On chip novel video streaming system for bi-network multicasting protocols

In the past three decades, tremendous Ethernet-related research has been done, which has led to today's ubiquitous Ethernet technology. On the other hand, with the emergence of new network needs, a new protocol, the IEEE 1394 standard serial bus (or Firewire) was introduced. Firewire is suitable for high-quality audio/video applications which do not perform well in the best-effort-based Ethernet technology. However, since Firewire is a serial bus, it has harsh cable length limitations as compared to Ethernet capabilities.In this paper, we present a novel on-chip system that receives Firewire video and transmits it in multicast mode using Ethernet protocol. A major advantage of this novel system is to utilize the existing Ethernet infrastructure to extend the range of Firewire video streaming to reach remote nodes and make it even accessible to nodes with a single Ethernet interface. This will have tremendous impact on Firewire applications such as deploying Firewire cameras in big-scale security-sensitive buildings or industrial facilities with image-based remote quality control.This novel chip utilizes the concept of Ethernet multicasting transmission mode for video streaming. The proposed chip design converts the IEEE 1394 isochronous traffic to the Ethernet multicast frame format via two off-chip asynchronous write and read buffers.The goal of this research is to design an On Chip Novel Video Streaming System that avoids performance bottlenecks in the software protocol conversion of these two important network protocols. The author decided to study these two networks because of their broad use and cable power provisioning capabilities. The novel system design is implemented using a customized field programmable gate array (FPGA), which enables the integration of various system components on one chip. The designed prototype is studied using both network monitoring tools and analytical techniques, to verify its function and compare it with the existing approaches.Performance measures show that the On Chip Novel Video Streaming System consumes less than 21 mW of power for 100 Mbps and 82 mW of power for 1 Gbps, and utilizes 57% of a Xilinx Spartan 2-100E-6FT256 FPGA resources. Hence, it is possible to incorporate further extensions. Experimental results show that 88% of the network utilization can be achieved, due to the use of the customized, FPGA-based design of bi-network traffic conversion.     

FPGA技术及其发展趋势

FPGA在电子设计领域得到广泛的应用，并成为实现电子系统的一种很重要的手段。本文主要介绍了FPGA的特点、设计流程及其发展趋势。     

基于FPGA的AES密码协处理器的设计和实现

文章基于FPGA设计了一种能完成AES算法加密的密码协处理器，设计中利用VirtexⅡ系列FPGA的结构特点，对AES算法的实现做了优化。实验证明，这种实现方式用较少的电路资源达到了较高的数据吞吐率。该密码协处理器还提供了和ARM处理器的接口逻辑，实现了用于加／解密和数据输入输出的协处理器指令．作为ARM微处理器指令集的扩展，大大提高了嵌入式系统处理数据加／解的效率，实现数据的安全传输。     

A system for inverter protection and real-time monitoring

A real-time system for protecting and monitoring a DC/AC converter has been designed and constructed. The proposed system consists of (a) a hardware protection unit for fast reaction, load protection and inverter fail-safe operation and (b) a microcontroller unit for calculating critical parameters of the inverter operation. The control unit malfunctions have not been investigated in this study. The proposed hardware architecture and sensors form a low-cost and reliable control unit. The experimental results show that the proposed system ensures the inverter protection and fail-safe features. The proposed unit can be used to increase the reliability of any power inverter in AC motor drives, renewable energy systems, etc. or can be incorporated in any UPS system.     

非制冷红外成像数字组件的关键设计

近几年随着热成像技术的快速发展。实用化、低成本、高可靠的非制冷焦平面阵列红外探测器应用研发已成为热成像领域最令人关注的焦点之一。并有大量应用产品问世。本文以法国SOFRADIR公司8—12μm非制冷焦平面探测器IDML073-XX-V3为原型。采用DSP、FPGA、探测器的数字驱动和控制等大量新技术实现了红外实时成像。论述了非制冷焦平面探测器技术指标、控制信号以及成像总体技术和实现方法。并重点说明了DSP和FPGA数字信号处理电路的功能和设计方法。以及探测器数字温控原理。该组件结构紧凑、成像清晰、性能稳定,并能满足工业级的使用要求。     

Fully digital jerk-based chaotic oscillators for high throughput pseudo-random number generators up to 8.77 Gbits/s

This paper introduces fully digital implementations of four different systems in the 3rd order jerk-equation based chaotic family using the Euler approximation. The digitization approach enables controllable chaotic systems that reliably provide sinusoidal or chaotic output based on a selection input. New systems are introduced, derived using logical and arithmetic operations between two system implementations of different bus widths, with up to 100× higher maximum Lyapunov exponent than the original jerk-equation based chaotic systems. The resulting chaotic output is shown to pass the NIST SP. 800-22 statistical test suite for pseudo-random number generators without post-processing by only eliminating the statistically defective bits. The systems are designed in Verilog HDL and experimentally verified on a Xilinx Virtex 4 FPGA for a maximum throughput of 15.59 Gbits/s for the native chaotic output and 8.77 Gbits/s for the resulting pseudo-random number generators.     

Design and implementation of robust visual servoing control of an inverted pendulum with an FPGA-based image co-processor

This paper presents the design and implementation of robust real-time visual servoing control with an FPGA-based image co-processor for a rotary inverted pendulum. The position of the pendulum is measured with a machine vision system. The pendulum used in the proposed system is much shorter than those used in published vision-based pendulum control system studies, which makes the system more difficult to control. The image processing algorithms of the machine vision system are pipelined and implemented on a field programmable gate array (FPGA) device to meet real-time constraints. To enhance robustness to model uncertainty and to attenuate disturbance and sensor noise, the design of the stabilizing controller is formulated as a problem of the mixed H₂/H_∞ control, which is then solved using the linear matrix inequality (LMI) approach. The designed control law is implemented on a digital signal processor (DSP). The effectiveness of the controller and the FPGA-based image co-processor is verified through simulation and experimental studies. The experimental results show that the designed system can robustly control an inverted pendulum in real-time.     

Hardware implementation of tag-reader mutual authentication protocol for RFID systems

Radio-frequency identification (RFID) is a recent technology that utilizes radio frequencies to track the object by transmitting a signal with a unique serial identity. Generally, the drawbacks of RFID technology are high cost and authentication systems between a reader and a tag become weak. In this paper, we proposed a protocol for RFID tag–reader mutual authentication scheme which is hardware efficient and consumes less dynamic power. Truncated multipliers are implemented in RFID tag–reader mutual authentication protocol system due to reduction in hardware cost and dynamic power. Experimental evaluation reveals that the proposed protocol with truncated multipliers provides more security than the earlier schemes. The proposed protocol is described in VHDL and simulated using Altera Quartus II. The functional block is implemented as hardware using an Altera DE2 Cyclone II (EP2C35F672C6) Field-Programmable Gate Array (FPGA).     

Design and Implementation of a Novel HomePlug-Based Solution for Low Cost and High Performance Smart Home Networking

As the smart home is the end-point power consumer, it is the major part to be controlled in a smart micro grid. There are so many challenges for implementing a smart home system in which the most important ones are the cost and simplicity of the implementation method. It is clear that the major share of the total cost is referred to the internal controlling system network; although there are too many methods proposed but still there is not any satisfying method at the consumers’ point of view. In this paper, a novel solution for this demand is proposed, which not only minimizes the implementation cost, but also provides a high level of reliability and simplicity of operation; feasibility, extendibility, and flexibility are other leading properties of the design.     

基于IEEE 802．16d OFDM系统的FPGA设计

研究基于IEEE 802．16d OFDM系统的FPGA实现。首先探讨了基于802．16d的OFDM系统FPGA设计的构架。然后采用VHDL硬件描述语言实现了发送端和接收端各个模块。最后选用了Altera公司CycloneⅡ系列的EP2C35F484C6芯片,在QuartusⅡ软件环境下对VHDL代码进行了综合。